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2020-07-10PCI: brcmstb: Use pci_host_probe() to register hostRob Herring1-16/+4
The brcmstb host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. Link: https://lore.kernel.org/r/[email protected] Tested-by: Nicolas Saenz Julienne <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Nicolas Saenz Julienne <[email protected]> Cc: Nicolas Saenz Julienne <[email protected]> Cc: [email protected] Cc: [email protected]
2020-07-10PCI: host-common: Use struct pci_host_bridge.windows list directlyRob Herring1-28/+14
There's no need to create a temporary resource list and then splice it to struct pci_host_bridge.windows list. Just use pci_host_bridge.windows directly. The necessary clean-up is already handled by the PCI core. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Will Deacon <[email protected]>
2020-07-07PCI: qcom: Replace define with standard valueAnsuel Smith1-10/+5
Lots of define are actually already defined in pci_regs.h, directly use the standard defines. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Support pci speed set for ipq806xSham Muthayyan1-0/+13
Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to some hardware limitations. Add support for speed setting defined by the max-link-speed binding. If not defined the max speed is set to GEN2 by default. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sham Muthayyan <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Add ipq8064 rev2 variantAnsuel Smith1-1/+3
Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit different offset based on the revision. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Add support for tx term offset for rev 2.1.0Ansuel Smith1-1/+16
Add tx term offset support to pcie qcom driver need in some revision of the ipq806x SoC. Ipq8064 needs tx term offset set to 7. Link: https://lore.kernel.org/r/[email protected] Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected] # v4.5+
2020-07-07PCI: qcom: Define some PARF params needed for ipq8064 SoCAnsuel Smith1-0/+24
Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization needed on some ipq8064 based device (Netgear R7800 for example). Without this the system locks on kernel load. Link: https://lore.kernel.org/r/[email protected] Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected] # v4.5+
2020-07-07PCI: qcom: Use bulk clk api and assert on errorAnsuel Smith1-85/+46
Rework 2.1.0 revision to use bulk clk api and fix missing assert on reset_control_deassert error. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Add missing reset for ipq806xAnsuel Smith1-0/+12
Add missing ext reset used by ipq8064 SoC in PCIe qcom driver. Link: https://lore.kernel.org/r/[email protected] Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected] # v4.5+
2020-07-07PCI: qcom: Change duplicate PCI reset to phy resetAbhishek Sahu1-10/+8
The deinit issues reset_control_assert for PCI twice and does not contain phy reset. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abhishek Sahu <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Add missing ipq806x clocks in PCIe driverAnsuel Smith1-5/+33
Aux and Ref clk are missing in PCIe qcom driver. Add support for this optional clks for ipq8064/apq8064 SoC. Link: https://lore.kernel.org/r/[email protected] Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: aardvark: Indicate error in 'val' when config read failsPali Rohár1-1/+3
Most callers of config read do not check for return value. But most of the ones that do, checks for error indication in 'val' variable. This patch updates error handling in advk_pcie_rd_conf() function. If PIO transfer fails then 'val' variable is set to 0xffffffff which indicates failture. Link: https://lore.kernel.org/r/20200528162604.GA323482@bjorn-Precision-5520 Link: https://lore.kernel.org/r/[email protected] Reported-by: Bjorn Helgaas <[email protected]> Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-07PCI: qcom: Fix runtime PM imbalance on errorDinghao Liu1-4/+2
pm_runtime_get_sync() increments the runtime PM usage counter even when it returns an error code, thus a matching decrement is needed on the error handling path to keep the counter balanced. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-07PCI: cadence: Fix runtime PM imbalance on errorDinghao Liu1-2/+1
pm_runtime_get_sync() increments the runtime PM usage counter even it returns an error code. Thus a pairing decrement is needed on the error handling path to keep the counter balanced. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-07PCI: dwc: pci-dra7xx: Fix runtime PM imbalance on errorDinghao Liu1-2/+1
pm_runtime_get_sync() increments the runtime PM usage counter even it returns an error code. Thus a pairing decrement is needed on the error handling path to keep the counter balanced. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-06PCI: vmd: Use Shadow MEMBAR registers for QEMU/KVM guestsJon Derrick1-6/+38
VMD device 28C0 natively assists guest passthrough of the VMD endpoint through the use of shadow registers that provide Host Physical Addresses to correctly assign bridge windows. These shadow registers are only available if VMD config space register 0x70, bit 1 is set. In order to support this mode in existing VMD devices which don't natively support the shadow register, it was decided that the hypervisor could offer the shadow registers in a vendor-specific PCI capability. QEMU has been modified to create this vendor-specific capability and supply the shadow membar registers for VMDs which don't natively support this feature. This patch adds this mode and updates the supported device list to allow this feature to be used on these VMDs. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jon Derrick <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-06PCI: mvebu: Use struct pci_host_bridge.windows list directlyRob Herring1-8/+5
There's no need to create a temporary resource list and then splice it to struct pci_host_bridge.windows list. Just use pci_host_bridge.windows directly. The necessary clean-up is already handled by the PCI core. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Thomas Petazzoni <[email protected]> Cc: Jason Cooper <[email protected]>
2020-07-06PCI: cadence: Use struct pci_host_bridge.windows list directlyRob Herring1-19/+7
There's no need to create a temporary resource list and then splice it to struct pci_host_bridge.windows list. Just use pci_host_bridge.windows directly. The necessary clean-up is already handled by the PCI core. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Tom Joseph <[email protected]>
2020-06-30PCI: Replace http:// links with https://Alexander A. Klimov8-8/+8
Replace http:// links with https:// links. This reduces the likelihood of man-in-the-middle attacks when developers open these links. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. [bhelgaas: also update samsung.com links, drop sourceforge link] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alexander A. Klimov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2020-06-14treewide: replace '---help---' in Kconfig files with 'help'Masahiro Yamada1-1/+1
Since commit 84af7a6194e4 ("checkpatch: kconfig: prefer 'help' over '---help---'"), the number of '---help---' has been gradually decreasing, but there are still more than 2400 instances. This commit finishes the conversion. While I touched the lines, I also fixed the indentation. There are a variety of indentation styles found. a) 4 spaces + '---help---' b) 7 spaces + '---help---' c) 8 spaces + '---help---' d) 1 space + 1 tab + '---help---' e) 1 tab + '---help---' (correct indentation) f) 1 tab + 1 space + '---help---' g) 1 tab + 2 spaces + '---help---' In order to convert all of them to 1 tab + 'help', I ran the following commend: $ find . -name 'Kconfig*' | xargs sed -i 's/^[[:space:]]*---help---/\thelp/' Signed-off-by: Masahiro Yamada <[email protected]>
2020-06-06Merge tag 'pci-v5.8-changes' of ↵Linus Torvalds39-1364/+2714
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "Enumeration: - Program MPS for RCiEP devices (Ashok Raj) - Fix pci_register_host_bridge() device_register() error handling (Rob Herring) - Fix pci_host_bridge struct device release/free handling (Rob Herring) Resource management: - Allow resizing BARs for devices on root bus (Ard Biesheuvel) Power management: - Reduce Thunderbolt resume time by working around devices that don't support DLL Link Active reporting (Mika Westerberg) - Work around a Pericom USB controller OHCI/EHCI PME# defect (Kai-Heng Feng) Virtualization: - Add ACS quirk for Intel Root Complex Integrated Endpoints (Ashok Raj) - Avoid FLR for AMD Starship USB 3.0 (Kevin Buettner) - Avoid FLR for AMD Matisse HD Audio & USB 3.0 (Marcos Scriven) Error handling: - Use only _OSC (not HEST FIRMWARE_FIRST) to determine AER ownership (Alexandru Gagniuc, Kuppuswamy Sathyanarayanan) - Reduce verbosity by logging only ACPI_NOTIFY_DISCONNECT_RECOVER events (Kuppuswamy Sathyanarayanan) - Don't enable AER by default in Kconfig (Bjorn Helgaas) Peer-to-peer DMA: - Add AMD Zen Raven and Renoir Root Ports to whitelist (Alex Deucher) ASPM: - Allow ASPM on links to PCIe-to-PCI/PCI-X Bridges (Kai-Heng Feng) Endpoint framework: - Fix DMA channel release in test (Kunihiko Hayashi) - Add page size as argument to pci_epc_mem_init() (Lad Prabhakar) - Add support to handle multiple base for mapping outbound memory (Lad Prabhakar) Generic host bridge driver: - Support building as module (Rob Herring) - Eliminate pci_host_common_probe wrappers (Rob Herring) Amlogic Meson PCIe controller driver: - Don't use FAST_LINK_MODE to set up link (Marc Zyngier) Broadcom STB PCIe controller driver: - Disable ASPM L0s if 'aspm-no-l0s' in DT (Jim Quinlan) - Fix clk_put() error (Jim Quinlan) - Fix window register offset (Jim Quinlan) - Assert fundamental reset on initialization (Nicolas Saenz Julienne) - Add notify xHCI reset property (Nicolas Saenz Julienne) - Add init routine for Raspberry Pi 4 VL805 USB controller (Nicolas Saenz Julienne) - Sync with Raspberry Pi 4 firmware for VL805 initialization (Nicolas Saenz Julienne) Cadence PCIe controller driver: - Remove "cdns,max-outbound-regions" DT property (replaced by "ranges") (Kishon Vijay Abraham I) - Read 32-bit (not 16-bit) Vendor ID/Device ID property from DT (Kishon Vijay Abraham I) Marvell Aardvark PCIe controller driver: - Improve link training (Marek Behún) - Add PHY support (Marek Behún) - Add "phys", "max-link-speed", "reset-gpios" to dt-binding (Marek Behún) - Train link immediately after enabling training to work around detection issues with some cards (Pali Rohár) - Issue PERST via GPIO to work around detection issues (Pali Rohár) - Don't blindly enable ASPM L0s (Pali Rohár) - Replace custom macros by standard linux/pci_regs.h macros (Pali Rohár) Microsoft Hyper-V host bridge driver: - Fix probe failure path to release resource (Wei Hu) - Retry PCI bus D0 entry on invalid device state for kdump (Wei Hu) Renesas R-Car PCIe controller driver: - Fix incorrect programming of OB windows (Andrew Murray) - Add suspend/resume (Kazufumi Ikeda) - Rename pcie-rcar.c to pcie-rcar-host.c (Lad Prabhakar) - Add endpoint controller driver (Lad Prabhakar) - Fix PCIEPAMR mask calculation (Lad Prabhakar) - Add r8a77961 to DT binding (Yoshihiro Shimoda) Socionext UniPhier Pro5 controller driver: - Add endpoint controller driver (Kunihiko Hayashi) Synopsys DesignWare PCIe controller driver: - Program outbound ATU upper limit register (Alan Mikhak) - Fix inner MSI IRQ domain registration (Marc Zyngier) Miscellaneous: - Check for platform_get_irq() failure consistently (negative return means failure) (Aman Sharma) - Fix several runtime PM get/put imbalances (Dinghao Liu) - Use flexible-array and struct_size() helpers for code cleanup (Gustavo A. R. Silva) - Update & fix issues in bridge emulation of PCIe registers (Jon Derrick) - Add macros for bridge window names (PCI_BRIDGE_IO_WINDOW, etc) (Krzysztof Wilczyński) - Work around Intel PCH MROMs that have invalid BARs (Xiaochun Lee)" * tag 'pci-v5.8-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (100 commits) PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver PCI: Add ACS quirk for Intel Root Complex Integrated Endpoints PCI/DPC: Print IRQ number used by port PCI/AER: Use "aer" variable for capability offset PCI/AER: Remove redundant dev->aer_cap checks PCI/AER: Remove redundant pci_is_pcie() checks PCI/AER: Remove HEST/FIRMWARE_FIRST parsing for AER ownership PCI: tegra: Fix runtime PM imbalance on error PCI: vmd: Filter resource type bits from shadow register PCI: tegra194: Fix runtime PM imbalance on error dt-bindings: PCI: Add UniPhier PCIe endpoint controller description PCI: hv: Use struct_size() helper PCI: Rename _DSM constants to align with spec PCI: Avoid FLR for AMD Starship USB 3.0 PCI: Avoid FLR for AMD Matisse HD Audio & USB 3.0 x86/PCI: Drop unused xen_register_pirq() gsi_override parameter PCI: dwc: Use private data pointer of "struct irq_domain" to get pcie_port PCI: amlogic: meson: Don't use FAST_LINK_MODE to set up link PCI: dwc: Fix inner MSI IRQ domain registration PCI: dwc: pci-dra7xx: Use devm_platform_ioremap_resource_byname() ...
2020-06-04Merge branch 'remotes/lorenzo/pci/vmd'Bjorn Helgaas1-2/+4
- Fix vmd resource address calculation using Host Physical Address shadow register (Jon Derrick) * remotes/lorenzo/pci/vmd: PCI: vmd: Filter resource type bits from shadow register
2020-06-04Merge branch 'remotes/lorenzo/pci/v3-semi'Bjorn Helgaas1-1/+1
- Fix memory leak in probe error paths (Christophe JAILLET) * remotes/lorenzo/pci/v3-semi: PCI: v3-semi: Fix a memory leak in v3_pci_probe() error handling paths
2020-06-04Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas2-7/+5
- Fix error message for failure to get reset GPIO from DT (Pali Rohár) - Fix runtime PM imbalance on error path (both tegra and tegra194) (Dinghao Liu) * remotes/lorenzo/pci/tegra: PCI: tegra: Fix runtime PM imbalance on error PCI: tegra194: Fix runtime PM imbalance on error PCI: tegra: Fix reporting GPIO error value
2020-06-04Merge branch 'remotes/lorenzo/pci/rcar'Bjorn Helgaas9-1181/+1904
- Fix rcar OB window programming (Andrew Murray) - Add rcar suspend/resume support (Kazufumi Ikeda) - Add r8a77961 to DT binding (Yoshihiro Shimoda) - Rename pcie-rcar.c to pcie-rcar-host.c to make room for endpoint mode (Lad Prabhakar) - Move shareable code to pcie-rcar.c (Lad Prabhakar) - Correct PCIEPAMR mask calculation for "size < 128" (Lad Prabhakar) - Add endpoint support for multiple outbound memory windows (Lad Prabhakar) - Add R-Car PCIe endpoint driver and DT bindings (Lad Prabhakar) * remotes/lorenzo/pci/rcar: MAINTAINERS: Add file patterns for rcar PCI device tree bindings PCI: rcar: Add endpoint mode support dt-bindings: PCI: rcar: Add bindings for R-Car PCIe endpoint controller PCI: endpoint: Add support to handle multiple base for mapping outbound memory PCI: endpoint: Pass page size as argument to pci_epc_mem_init() PCI: rcar: Fix calculating mask for PCIEPAMR register PCI: rcar: Move shareable code to a common file PCI: rcar: Rename pcie-rcar.c to pcie-rcar-host.c dt-bindings: pci: rcar: add r8a77961 support PCI: rcar: Add suspend/resume PCI: rcar: Fix incorrect programming of OB windows
2020-06-04Merge branch 'remotes/lorenzo/pci/hv'Bjorn Helgaas1-20/+62
- Release resource in probe failure path (Wei Hu) - Retry PCI bus D0 entry if device state is invalid (Wei Hu) - Use struct_size() to help avoid type mistakes (Gustavo A. R. Silva) * remotes/lorenzo/pci/hv: PCI: hv: Use struct_size() helper PCI: hv: Retry PCI bus D0 entry on invalid device state PCI: hv: Fix the PCI HyperV probe failure path to release resource properly
2020-06-04Merge branch 'remotes/lorenzo/pci/host-generic'Bjorn Helgaas9-61/+51
- Constify struct pci_ecam_ops (Rob Herring) - Support building as modules (Rob Herring) - Eliminate wrappers for pci_host_common_probe() by using DT match table data (Rob Herring) * remotes/lorenzo/pci/host-generic: PCI: host-generic: Eliminate pci_host_common_probe wrappers PCI: host-generic: Support building as modules PCI: Constify struct pci_ecam_ops # Conflicts: # drivers/pci/controller/dwc/pcie-hisi.c
2020-06-04Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas11-20/+414
- Simplify computation of msix_tbl (Jiri Slaby) - Make hisi_pcie_platform_ops static (Zou Wei) - Warn about resources above 4G (Alan Mikhak) - Make intel_pcie_cpu_addr() static (Jason Yan) - Use devm_platform_ioremap_resource_byname() to simplify code and improve error checking (Wei Yongjun) - Fix inner MSI IRQ domain registration so it doesn't confuse debugfs (Marc Zyngier) - Don't use FAST_LINK_MODE on meson (Marc Zyngier) - Add Socionext UniPhier Pro5 PCIe endpoint controller driver and DT description (Kunihiko Hayashi) * remotes/lorenzo/pci/dwc: PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driver dt-bindings: PCI: Add UniPhier PCIe endpoint controller description PCI: dwc: Use private data pointer of "struct irq_domain" to get pcie_port PCI: amlogic: meson: Don't use FAST_LINK_MODE to set up link PCI: dwc: Fix inner MSI IRQ domain registration PCI: dwc: pci-dra7xx: Use devm_platform_ioremap_resource_byname() PCI: dwc: intel: Make intel_pcie_cpu_addr() static PCI: dwc: Program outbound ATU upper limit register PCI: dwc: Make hisi_pcie_platform_ops static PCI: dwc: Clean up computing of msix_tbl
2020-06-04Merge branch 'remotes/lorenzo/pci/cadence'Bjorn Helgaas2-12/+4
- Deprecate 'cdns,max-outbound-regions' and 'cdns,no-bar-match-nbits' bindings in favor of deriving them from 'ranges' and 'dma-ranges' (Kishon Vijay Abraham I) - Read Vendor and Device ID as 32 bits (not 16) from DT (Kishon Vijay Abraham I) * remotes/lorenzo/pci/cadence: PCI: cadence: Fix to read 32-bit Vendor ID/Device ID property from DT PCI: cadence: Remove "cdns,max-outbound-regions" DT property dt-bindings: PCI: cadence: Deprecate inbound/outbound specific bindings
2020-06-04Merge branch 'remotes/lorenzo/pci/brcmstb'Bjorn Helgaas1-4/+33
- Assert fundamental reset on initialization (Nicolas Saenz Julienne) - Remove unnecessary clk_put(); devm_clk_get() handles this automatically (Jim Quinlan) - Fix outbound memory window register stride offset (Jim Quinlan) - Add "aspm-no-l0s" property for brcmstb and disable ASPM L0s when present (Jim Quinlan) - Add property to notify Raspberry Pi firmware of xHCI reset (Nicolas Saenz Julienne) - Add Raspberry Pi VL805 xHCI init function to trigger VL805 firmware load (Nicolas Saenz Julienne) - Wait in brcmstb probe for Raspberry Pi VL805 firmware initialization (Nicolas Saenz Julienne) - Load Raspberry Pi VL805 firmware in USB early handoff quirk (Nicolas Saenz Julienne) * remotes/lorenzo/pci/brcmstb: USB: pci-quirks: Add Raspberry Pi 4 quirk PCI: brcmstb: Wait for Raspberry Pi's firmware when present firmware: raspberrypi: Introduce vl805 init routine soc: bcm2835: Add notify xHCI reset property PCI: brcmstb: Disable L0s component of ASPM if requested dt-bindings: PCI: brcmstb: New prop 'aspm-no-l0s' PCI: brcmstb: Fix window register offset from 4 to 8 PCI: brcmstb: Don't clk_put() a managed clock PCI: brcmstb: Assert fundamental reset on initialization
2020-06-04Merge branch 'remotes/lorenzo/pci/altera'Bjorn Helgaas1-1/+1
- Fix altera whitespace (Colin Ian King) * remotes/lorenzo/pci/altera: PCI: altera: Clean up indentation issue on a return statement
2020-06-04Merge branch 'remotes/lorenzo/pci/aardvark'Bjorn Helgaas1-44/+219
- Train link immediately after enabling link training to avoid issues with Compex WLE900VX and Turris MOX devices (Pali Rohár) - Remove ASPM config and let the PCI core do it (Pali Rohár) - Interpret zero 'max-link-speed' value as invalid (Pali Rohár) - Respect the 'max-link-speed' property and improve link training (Marek Behún) - Issue PERST via GPIO (Pali Rohár) - Add PHY support (Marek Behún) - Use standard PCIe capability macros (Pali Rohár) - Document new 'max-link-speed', 'phys', and 'reset-gpios' properties (Marek Behún) * remotes/lorenzo/pci/aardvark: dt-bindings: PCI: aardvark: Describe new properties PCI: aardvark: Replace custom macros by standard linux/pci_regs.h macros PCI: aardvark: Add PHY support PCI: aardvark: Add FIXME comment for PCIE_CORE_CMD_STATUS_REG access PCI: aardvark: Issue PERST via GPIO PCI: aardvark: Improve link training PCI: of: Zero max-link-speed value is invalid PCI: aardvark: Don't blindly enable ASPM L0s and don't write to read-only register PCI: aardvark: Train link immediately after enabling training
2020-06-04Merge branch 'pci/misc'Bjorn Helgaas7-10/+16
- Clarify that platform_get_irq() should never return 0 (Bjorn Helgaas) - Check for platform_get_irq() failure consistently (Bjorn Helgaas) - Replace zero-length array with flexible-array (Gustavo A. R. Silva) - Unify pcie_find_root_port() and pci_find_pcie_root_port() (Yicong Yang) - Quirk Intel C620 MROMs, which have non-BARs in BAR locations (Xiaochun Lee) - Fix pcie_pme_resume() and pcie_pme_remove() kernel-doc (Jay Fang) - Rename _DSM constants to align with spec (Krzysztof Wilczyński) * pci/misc: PCI: Rename _DSM constants to align with spec PCI/PME: Fix kernel-doc of pcie_pme_resume() and pcie_pme_remove() x86/PCI: Mark Intel C620 MROMs as having non-compliant BARs PCI: Unify pcie_find_root_port() and pci_find_pcie_root_port() PCI: Replace zero-length array with flexible-array PCI: Check for platform_get_irq() failure consistently driver core: platform: Clarify that IRQ 0 is invalid
2020-06-04PCI: uniphier: Add Socionext UniPhier Pro5 PCIe endpoint controller driverKunihiko Hayashi3-2/+396
Add driver for the Socionext UniPhier Pro5 SoC endpoint controller. This controller is based on the DesignWare PCIe core. And add "host" to existing controller descriontions for the host controller in Kconfig. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-06-03Merge tag 'hyperv-next-signed' of ↵Linus Torvalds1-16/+28
git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux Pull hyper-v updates from Wei Liu: - a series from Andrea to support channel reassignment - a series from Vitaly to clean up Vmbus message handling - a series from Michael to clean up and augment hyperv-tlfs.h - patches from Andy to clean up GUID usage in Hyper-V code - a few other misc patches * tag 'hyperv-next-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux: (29 commits) Drivers: hv: vmbus: Resolve more races involving init_vp_index() Drivers: hv: vmbus: Resolve race between init_vp_index() and CPU hotplug vmbus: Replace zero-length array with flexible-array Driver: hv: vmbus: drop a no long applicable comment hyper-v: Switch to use UUID types directly hyper-v: Replace open-coded variant of %*phN specifier hyper-v: Supply GUID pointer to printf() like functions hyper-v: Use UUID API for exporting the GUID (part 2) asm-generic/hyperv: Add definitions for Get/SetVpRegister hypercalls x86/hyperv: Split hyperv-tlfs.h into arch dependent and independent files x86/hyperv: Remove HV_PROCESSOR_POWER_STATE #defines KVM: x86: hyperv: Remove duplicate definitions of Reference TSC Page drivers: hv: remove redundant assignment to pointer primary_channel scsi: storvsc: Re-init stor_chns when a channel interrupt is re-assigned Drivers: hv: vmbus: Introduce the CHANNELMSG_MODIFYCHANNEL message type Drivers: hv: vmbus: Synchronize init_vp_index() vs. CPU hotplug Drivers: hv: vmbus: Remove the unused HV_LOCALIZED channel affinity logic PCI: hv: Prepare hv_compose_msi_msg() for the VMBus-channel-interrupt-to-vCPU reassignment functionality Drivers: hv: vmbus: Use a spin lock for synchronizing channel scheduling vs. channel removal hv_utils: Always execute the fcopy and vss callbacks in a tasklet ...
2020-06-01PCI: tegra: Fix runtime PM imbalance on errorDinghao Liu1-2/+1
pm_runtime_get_sync() increments the runtime PM usage counter even when it returns an error code. Thus a pairing decrement is needed on the error handling path to keep the counter balanced. Also, call pm_runtime_disable() when pm_runtime_get_sync() returns an error code. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Thierry Reding <[email protected]>
2020-05-29PCI: vmd: Filter resource type bits from shadow registerJon Derrick1-2/+4
Versions of VMD with the Host Physical Address shadow register use this register to calculate the bus address offset needed to do guest passthrough of the domain. This register shadows the Host Physical Address registers including the resource type bits. After calculating the offset, the extra resource type bits lead to the VMD resources being over-provisioned at the front and under-provisioned at the back. Example: pci 10000:80:02.0: reg 0x10: [mem 0xf801fffc-0xf803fffb 64bit] Expected: pci 10000:80:02.0: reg 0x10: [mem 0xf8020000-0xf803ffff 64bit] If other devices are mapped in the over-provisioned front, it could lead to resource conflict issues with VMD or those devices. Link: https://lore.kernel.org/r/[email protected] Fixes: a1a30170138c9 ("PCI: vmd: Fix shadow offsets to reflect spec changes") Signed-off-by: Jon Derrick <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-05-29PCI: tegra194: Fix runtime PM imbalance on errorDinghao Liu1-3/+2
pm_runtime_get_sync() increments the runtime PM usage counter even when it returns an error code. Thus a pairing decrement is needed on the error handling path to keep the counter balanced. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Thierry Reding <[email protected]> Acked-by: Vidya Sagar <[email protected]>
2020-05-28PCI: hv: Use struct_size() helperGustavo A. R. Silva1-14/+8
One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct hv_dr_state { ... struct hv_pcidev_description func[]; }; struct pci_bus_relations { ... struct pci_function_description func[]; } __packed; Make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. So, replace the following forms: offsetof(struct hv_dr_state, func) + (sizeof(struct hv_pcidev_description) * (relations->device_count)) offsetof(struct pci_bus_relations, func) + (sizeof(struct pci_function_description) * (bus_rel->device_count)) with: struct_size(dr, func, relations->device_count) and struct_size(bus_rel, func, bus_rel->device_count) respectively. Link: https://lore.kernel.org/r/20200525164319.GA13596@embeddedor Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Wei Liu <[email protected]>
2020-05-27PCI: Add Loongson PCI Controller supportJiaxun Yang3-0/+258
This controller can be found on Loongson-2K SoC, Loongson-3 systems with RS780E/LS7A PCH. The RS780E part of code was previously located at arch/mips/pci/ops-loongson3.c and now it can use generic PCI driver implementation. Signed-off-by: Jiaxun Yang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2020-05-22PCI: dwc: Use private data pointer of "struct irq_domain" to get pcie_portKishon Vijay Abraham I1-1/+1
No functional change. Get "struct pcie_port *" from private data pointer of "struct irq_domain" in dw_pcie_irq_domain_free() to make it look similar to how "struct pcie_port *" is obtained in dw_pcie_irq_domain_alloc() Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
2020-05-22PCI: amlogic: meson: Don't use FAST_LINK_MODE to set up linkMarc Zyngier1-2/+2
The vim3l board does not work with a standard PCIe switch (ASM1184e), spitting all kind of errors - hinting at HW misconfiguration (no link, port enumeration issues, etc). According to the the Synopsys DWC PCIe Reference Manual, in the section dedicated to the PLCR register, bit 7 is described (FAST_LINK_MODE) as: "Sets all internal timers to fast mode for simulation purposes." it is sound to set this bit from a simulation perspective, but on actual silicon, which expects timers to have a nominal value, it is not. Make sure the FAST_LINK_MODE bit is cleared when configuring the RC to solve this problem. Link: https://lore.kernel.org/r/[email protected] Fixes: 9c0ef6d34fdb ("PCI: amlogic: Add the Amlogic Meson PCIe controller driver") Signed-off-by: Marc Zyngier <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Acked-by: Rob Herring <[email protected]>
2020-05-22PCI: dwc: Fix inner MSI IRQ domain registrationMarc Zyngier1-0/+2
On a system that uses the internal DWC MSI widget, I get this warning from debugfs when CONFIG_GENERIC_IRQ_DEBUGFS is selected: debugfs: File ':soc:pcie@fc000000' in directory 'domains' already present! This is due to the fact that the DWC MSI code tries to register two IRQ domains for the same firmware node, without telling the low level code how to distinguish them (by setting a bus token). This further confuses debugfs which tries to create corresponding files for each domain. Fix it by tagging the inner domain as DOMAIN_BUS_NEXUS, which is the closest thing we have as to "generic MSI". Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Jingoo Han <[email protected]>
2020-05-22PCI: dwc: pci-dra7xx: Use devm_platform_ioremap_resource_byname()Wei Yongjun1-5/+3
platform_get_resource() may fail and return NULL, so we had better check its return value to avoid a NULL pointer dereference a bit later in the code. Fix it to use devm_platform_ioremap_resource_byname() instead of calling platform_get_resource_byname() and devm_ioremap(). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Wei Yongjun <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-05-22PCI: dwc: intel: Make intel_pcie_cpu_addr() staticJason Yan1-1/+1
Fix the following sparse warning: drivers/pci/controller/dwc/pcie-intel-gw.c:456:5: warning: symbol 'intel_pcie_cpu_addr' was not declared. Should it be static? Link: https://lore.kernel.org/r/[email protected] Reported-by: Hulk Robot <[email protected]> Signed-off-by: Jason Yan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-05-22PCI: dwc: Program outbound ATU upper limit registerAlan Mikhak2-3/+7
Function dw_pcie_prog_outbound_atu_unroll() does not program the upper 32-bit ATU limit register. Since ATU programming functions limit the size of the translated region to 4GB by using a u32 size parameter, these issues may combine into undefined behavior for resource sizes with non-zero upper 32-bits. For example, a 128GB address space starting at physical CPU address of 0x2000000000 with size of 0x2000000000 needs the following values programmed into the lower and upper 32-bit limit registers: 0x3fffffff in the upper 32-bit limit register 0xffffffff in the lower 32-bit limit register Currently, only the lower 32-bit limit register is programmed with a value of 0xffffffff but the upper 32-bit limit register is not being programmed. As a result, the upper 32-bit limit register remains at its default value after reset of 0x0. These issues may combine to produce undefined behavior since the ATU limit address may be lower than the ATU base address. Programming the upper ATU limit address register prevents such undefined behavior despite the region size getting truncated due to the 32-bit size limit. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alan Mikhak <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
2020-05-22PCI: rcar: Add endpoint mode supportLad Prabhakar4-0/+581
Add support for R-Car PCIe controller to work in endpoint mode. Link: https://lore.kernel.org/r/1588854799-13710-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Lad Prabhakar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]>
2020-05-22PCI: endpoint: Add support to handle multiple base for mapping outbound memoryLad Prabhakar1-8/+8
R-Car PCIe controller has support to map multiple memory regions for mapping the outbound memory in local system also the controller limits single allocation for each region (that is, once a chunk is used from the region it cannot be used to allocate a new one). This features inspires to add support for handling multiple memory bases in endpoint framework. With this patch pci_epc_mem_init() initializes address space for endpoint controller which support single window and pci_epc_multi_mem_init() initializes multiple windows supported by endpoint controller. Link: https://lore.kernel.org/r/1588854799-13710-6-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Lad Prabhakar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
2020-05-18PCI: cadence: Fix to read 32-bit Vendor ID/Device ID property from DTKishon Vijay Abraham I2-4/+4
The PCI Bus Binding specification (IEEE Std 1275-1994 Revision 2.1 [1]) defines both Vendor ID and Device ID to be 32-bits. Fix pcie-cadence-host.c driver to read 32-bit Vendor ID and Device ID properties from device tree. [1] -> https://www.devicetree.org/open-firmware/bindings/pci/pci2_1.pdf Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Tom Joseph <[email protected]>
2020-05-18PCI: cadence: Remove "cdns,max-outbound-regions" DT propertyKishon Vijay Abraham I2-8/+0
"cdns,max-outbound-regions" device tree property provides the maximum number of outbound regions supported by the Host PCIe controller. However the outbound regions are configured based on what is populated in the "ranges" DT property. Avoid using two properties for configuring outbound regions and use only "ranges" property instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Tom Joseph <[email protected]>
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