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2020-08-03PCI: j721e: Add TI J721E PCIe driverKishon Vijay Abraham I5-2/+527
Add support for PCIe controller in J721E SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in both host mode and device mode. Some of the features of the controller are: *) Supports both RC mode and EP mode *) Supports MSI and MSI-X support *) Supports upto GEN3 speed mode *) Supports SR-IOV capability *) Ability to route all transactions via SMMU (support will be added in a later patch). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-28PCI: cadence: Add MSI-X support to Endpoint driverAlan Douglas2-1/+117
Implement ->set_msix() and ->get_msix() callback functions in order to configure MSIX capability in the PCIe endpoint controller. Add cdns_pcie_ep_send_msix_irq() to send MSIX interrupts to Host. cdns_pcie_ep_send_msix_irq() gets the MSIX table address (virtual address) from "struct cdns_pcie_epf" that gets initialized in ->set_bar() call back function. [[email protected]: Re-implement MSIX support in accordance with the re-designed core MSI-X interfaces] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alan Douglas <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-28PCI: hv: Make some functions staticWei Yongjun1-7/+8
sparse report build warning as follows: drivers/pci/controller/pci-hyperv.c:941:5: warning: symbol 'hv_read_config_block' was not declared. Should it be static? drivers/pci/controller/pci-hyperv.c:1021:5: warning: symbol 'hv_write_config_block' was not declared. Should it be static? drivers/pci/controller/pci-hyperv.c:1090:5: warning: symbol 'hv_register_block_invalidate' was not declared. Should it be static? Those functions are not used outside of this file, so mark them static. Link: https://lore.kernel.org/r/[email protected] Reported-by: Hulk Robot <[email protected]> Signed-off-by: Wei Yongjun <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-28PCI: tegra: Remove PLL power suppliesThierry Reding1-8/+2
The Tegra PCI controller driver doesn't need to control the PLL power supplies directly, but rather uses the pads provided by the XUSB pad controller, which in turn is responsible for supplying power to the PLLs. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-07-27PCI: dwc: hisi: Remove non-ECAM HiSilicon hip05/hip06 driverRob Herring1-219/+0
The HiSilicon non-ECAM PCIe has been broken since March 2016 commit 7e57fd1444bf ("PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc()"). The reason is this commit moved the iATU setup code from dw_pcie_host_init() to dw_pcie_setup_rc(), but the hisi driver never calls dw_pcie_setup_rc(). The result is the PCI memory space is never configured and the driver can't work. It's also clear it has an iATU as the config space accesses use it. There's also no dts file using either "hisilicon,hip05-pcie" or "hisilicon,hip06-pcie". Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Zhou Wang <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-07-27PCI: cadence: Fix updating Vendor ID and Subsystem Vendor ID registerKishon Vijay Abraham I1-2/+7
Commit 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe controller") in order to update Vendor ID, directly wrote to PCI_VENDOR_ID register. However PCI_VENDOR_ID in root port configuration space is read-only register and writing to it will have no effect. Use local management register to configure Vendor ID and Subsystem Vendor ID. Link: https://lore.kernel.org/r/[email protected] Fixes: 1b79c5284439 ("PCI: cadence: Add host driver for Cadence PCIe controller") Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-07-27PCI: cadence: Add new *ops* for CPU addr fixupKishon Vijay Abraham I4-13/+24
Cadence driver uses "mem" memory resource to obtain the offset of configuration space address region, memory space address region and message space address region. The obtained offset is used to program the Address Translation Unit (ATU). However certain platforms like TI's J721E SoC require the absolute address to be programmed in the ATU and not just the offset. Add new *ops* for CPU addr fixup for the platform drivers to provide the correct address to be programmed in the ATU. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-27PCI: cadence: Allow pci_host_bridge to have custom pci_opsKishon Vijay Abraham I1-1/+2
Certain platforms like TI's J721E allows only 32-bit configuration space access. In such cases pci_generic_config_read and pci_generic_config_write cannot be used. Add support in Cadence core to let pci_host_bridge have custom pci_ops. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-27PCI: cadence: Add support to start link and verify link statusKishon Vijay Abraham I3-1/+72
Add cdns_pcie_ops to start link and verify link status. The registers to start link and to check link status is in Platform specific PCIe wrapper. Add support for platform specific drivers to add callback functions for the PCIe Cadence core to start link and verify link status. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-07-27PCI: cadence: Convert all r/w accessors to perform only 32-bit accessesKishon Vijay Abraham I2-18/+62
Certain platforms like TI's J721E using Cadence PCIe IP can perform only 32-bit accesses for reading or writing to Cadence registers. Convert all read and write accesses to 32-bit in Cadence PCIe driver in preparation for adding PCIe support in TI's J721E SoC. Also add spin lock to disable interrupts while modifying PCI_STATUS register while raising legacy interrupt since PCI_STATUS is accessible by both remote RC and EP and time between read and write should be minimized. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-27PCI: cadence: Fix cdns_pcie_{host|ep}_setup() error pathKishon Vijay Abraham I2-12/+3
commit bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") while refactoring the Cadence PCIe driver to be used as library, removed pm_runtime_get_sync() from cdns_pcie_ep_setup() and cdns_pcie_host_setup() but missed to remove the corresponding pm_runtime_put_sync() in the error path. Fix it here. Link: https://lore.kernel.org/r/[email protected] Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-07-27PCI: cadence: Use "dma-ranges" instead of "cdns,no-bar-match-nbits" propertyKishon Vijay Abraham I2-17/+263
Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits" property to configure the number of bits passed through from PCIe address to internal address in Inbound Address Translation register. This only used the NO MATCH BAR. However standard PCI dt-binding already defines "dma-ranges" to describe the address ranges accessible by PCIe controller. Add support in Cadence PCIe host driver to parse dma-ranges and configure the inbound regions for BAR0, BAR1 and NO MATCH BAR. Cadence IP specifies maximum size for BAR0 as 256GB, maximum size for BAR1 as 2 GB. This adds support to take the next biggest region in "dma-ranges" and find the smallest BAR that each of the regions fit in and if there is no BAR big enough to hold the region, split the region to see if it can be fitted using multiple BARs. "dma-ranges" of J721E will be dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>; Since there is no BAR which can hold 2^48 size, NO_MATCH_BAR will be used here. Legacy device tree binding compatibility is maintained by retaining support for "cdns,no-bar-match-nbits". Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-07-27PCI: hv: Fix a timing issue which causes kdump to fail occasionallyWei Hu1-34/+37
Kdump could fail sometime on Hyper-V guest because the retry in hv_pci_enter_d0() releases child device structures in hv_pci_bus_exit(). Although there is a second asynchronous device relations message sending from the host, if this message arrives to the guest after hv_send_resource_allocated() is called, the retry would fail. Fix the problem by moving retry to hv_pci_probe() and start the retry from hv_pci_query_relations() call. This will cause a device relations message to arrive to the guest synchronously; the guest would then be able to rebuild the child device structures before calling hv_send_resource_allocated(). Link: https://lore.kernel.org/r/[email protected] Fixes: c81992e7f4aa ("PCI: hv: Retry PCI bus D0 entry on invalid device state") Signed-off-by: Wei Hu <[email protected]> [[email protected]: fixed a comment and commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Michael Kelley <[email protected]>
2020-07-23PCI: rcar: Use struct pci_host_bridge.windows list directlyRob Herring1-41/+4
There's no need to create a temporary resource list and then splice it to struct pci_host_bridge.windows list. Just use pci_host_bridge.windows directly. The necessary clean-up is already handled by the PCI core. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Marek Vasut <[email protected]> Cc: Yoshihiro Shimoda <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: [email protected] Cc: [email protected]
2020-07-23PCI: rcar: Use devm_pci_alloc_host_bridge()Rob Herring1-5/+2
Move to the resource managed devm_pci_alloc_host_bridge() and simplify the error path. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Marek Vasut <[email protected]> Cc: Yoshihiro Shimoda <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: [email protected]
2020-07-23PCI: cadence: Remove private bus number and range storageRob Herring4-26/+24
There's no need to store the bus number or range resource as the driver only needs the bus number which is already in the pci_host_bridge. For endpoint mode, the bus number is always 0. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Tom Joseph <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-07-23PCI: cadence: Use bridge resources for outbound window setupRob Herring1-21/+16
Instead of parsing 'ranges' from DT again, use the bridge window resources. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Tom Joseph <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-07-23PCI: Move setting pci_host_bridge.busnr out of host driversRob Herring7-18/+3
Most host drivers only parse the DT bus range to set the root bus number in pci_host_bridge.busnr. The ones that don't set busnr are buggy in that they ignore what's in DT. Let's set busnr in pci_scan_root_bus_bridge() where we already check for the bus resource and remove setting it in host drivers. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Thomas Petazzoni <[email protected]> Cc: Will Deacon <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: Linus Walleij <[email protected]> Cc: Ryder Lee <[email protected]> Cc: Marek Vasut <[email protected]> Cc: Yoshihiro Shimoda <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2020-07-23PCI: rcar: Use pci_is_root_bus() to check if bus is root busRob Herring1-14/+5
Use pci_is_root_bus() rather than tracking the root bus number to determine if the bus is the root bus or not. This removes storing duplicated data as well as the need for the host bridge driver to have to care about the bus numbers in most cases. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Marek Vasut <[email protected]> Cc: Yoshihiro Shimoda <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: [email protected]
2020-07-23PCI: rockchip: Use pci_is_root_bus() to check if bus is root busRob Herring2-11/+7
Use pci_is_root_bus() rather than tracking the root bus number to determine if the bus is the root bus or not. This removes storing duplicated data as well as the need for the host bridge driver to have to care about the bus numbers in most cases. Also, bridge->busnr is never set so effectively the root bus must be 0. This will be fixed by a subsequent commit. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Shawn Lin <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Heiko Stuebner <[email protected]> Cc: [email protected]
2020-07-23PCI: xilinx: Use pci_is_root_bus() to check if bus is root busRob Herring1-7/+4
Use pci_is_root_bus() rather than tracking the root bus number to determine if the bus is the root bus or not. This removes storing duplicated data as well as the need for the host bridge driver to have to care about the bus numbers in most cases. There was also a bug that the root_busno is never set which means the root bus number is always 0 even if the DT said something else. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Michal Simek <[email protected]> Cc: [email protected] Cc: [email protected]
2020-07-23PCI: xilinx-nwl: Use pci_is_root_bus() to check if bus is root busRob Herring1-7/+3
Use pci_is_root_bus() rather than tracking the root bus number to determine if the bus is the root bus or not. This removes storing duplicated data as well as the need for the host bridge driver to have to care about the bus numbers in most cases. There was also a bug that the pci_host_bridge.busnr is set from root_busno, but root_busno is never set which means the root bus number is always 0 even if the DT said something else. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Michal Simek <[email protected]>
2020-07-23PCI: mobiveil: Use pci_is_root_bus() to check if bus is root busRob Herring2-8/+3
Use pci_is_root_bus() rather than tracking the root bus number to determine if the bus is the root bus or not. This removes storing duplicated data as well as the need for the host bridge driver to have to care about the bus numbers in most cases. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Karthikeyan Mitran <[email protected]> Cc: Hou Zhiqiang <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-07-23PCI: designware: Use pci_is_root_bus() to check if bus is root busRob Herring4-15/+10
Use pci_is_root_bus() rather than tracking the root bus number to determine if the bus is the root bus or not. This removes storing duplicated data as well as the need for the host bridge driver to have to care about the bus numbers in most cases. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Richard Zhu <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]>
2020-07-23PCI: aardvark: Use pci_is_root_bus() to check if bus is root busRob Herring1-7/+6
Use pci_is_root_bus() rather than tracking the root bus number to determine if the bus is the root bus or not. This removes storing duplicated data as well as the need for the host bridge driver to have to care about the bus numbers in most cases. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Thomas Petazzoni <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-07-23PCI: Drop unnecessary zeroing of bridge fieldsRob Herring10-13/+0
The struct pci_host_bridge is 0 initialized when allocated, so there's no need to explicitly set fields to 0. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-07-23PCI: Set default bridge parent deviceRob Herring20-21/+0
The host bridge's parent device is always the platform device. As we already have a pointer to it in the devres functions, let's initialize the parent device. Drivers can still override the parent if desired. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-07-23PCI: versatile: Drop flag PCI_ENABLE_PROC_DOMAINSRob Herring1-1/+0
PCI_ENABLE_PROC_DOMAINS is only used on powerpc and doesn't do anything for the Versatile host driver, so let's drop it. I'm not sure how or why I had this to begin with. PCI_ENABLE_PROC_DOMAINS was never used on ARM. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-07-23PCI: controller: Remove duplicate error messageDejin Zheng4-15/+4
devm_pci_remap_cfg_resource() will print an error message by itself when goes wrong, so remove the duplicate error message. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dejin Zheng <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-07-23PCI: rcar: Fix runtime PM imbalance on errorDinghao Liu1-3/+1
pm_runtime_get_sync() increments the runtime PM usage counter even when the call returns an error code. Thus a corresponding decrement is needed on the error handling path to keep the counter balanced. Link: https://lore.kernel.org/r/[email protected] Fixes: 0df6150e7ceb ("PCI: rcar: Use runtime PM to control controller clock") Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]>
2020-07-23irqdomain/treewide: Free firmware node after domain removalJon Derrick1-0/+3
Commit 711419e504eb ("irqdomain: Add the missing assignment of domain->fwnode for named fwnode") unintentionally caused a dangling pointer page fault issue on firmware nodes that were freed after IRQ domain allocation. Commit e3beca48a45b fixed that dangling pointer issue by only freeing the firmware node after an IRQ domain allocation failure. That fix no longer frees the firmware node immediately, but leaves the firmware node allocated after the domain is removed. The firmware node must be kept around through irq_domain_remove, but should be freed it afterwards. Add the missing free operations after domain removal where where appropriate. Fixes: e3beca48a45b ("irqdomain/treewide: Keep firmware node unconditionally allocated") Signed-off-by: Jon Derrick <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> # drivers/pci Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected]
2020-07-21PCI: aardvark: Don't touch PCIe registers if no card connectedPali Rohár1-0/+7
When there is no PCIe card connected and advk_pcie_rd_conf() or advk_pcie_wr_conf() is called for PCI bus which doesn't belong to emulated root bridge, the aardvark driver throws the following error message: advk-pcie d0070000.pcie: config read/write timed out Obviously accessing PCIe registers of disconnected card is not possible. Extend check in advk_pcie_valid_device() function for validating availability of PCIe bus. If PCIe link is down, then the device is marked as Not Found and the driver does not try to access these registers. This is just an optimization to prevent accessing PCIe registers when card is disconnected. Trying to access PCIe registers of disconnected card does not cause any crash, kernel just needs to wait for a timeout. So if card disappear immediately after checking for PCIe link (before accessing PCIe registers), it does not cause any problems. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-20PCI: loongson: Use DECLARE_PCI_FIXUP_EARLY for bridge_class_quirk()Tiezhu Yang1-3/+3
According to the datasheet of Loongson LS7A bridge chip, the old version of Loongson LS7A PCIE port has a wrong value about PCI class which is 0x060000, the correct value should be 0x060400, this bug can be fixed by "dev->class = PCI_CLASS_BRIDGE_PCI << 8;" at the software level and it was fixed in hardware in the latest LS7A versions. In order to maintain downward compatibility, use DECLARE_PCI_FIXUP_EARLY instead of DECLARE_PCI_FIXUP_HEADER for bridge_class_quirk() to fix it as early as possible. Otherwise, in the function pci_setup_device(), the related code about "dev->class" such as "class = dev->class >> 8;" and "dev->transparent = ((dev->class & 0xff) == 1);" maybe get wrong value without EARLY fixup. Link: https://lore.kernel.org/r/[email protected] Fixes: 1f58cca5cf2b ("PCI: Add Loongson PCI Controller support") Signed-off-by: Tiezhu Yang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-07-20PCI: tegra: Revert tegra124 raw_violation_fixupNicolas Chauvet1-32/+0
As reported in https://bugzilla.kernel.org/206217 , raw_violation_fixup is causing more harm than good in some common use-cases. This patch is a partial revert of commit: 191cd6fb5d2c ("PCI: tegra: Add SW fixup for RAW violations") and fixes the following regression since then. * Description: When both the NIC and MMC are used one can see the following message: NETDEV WATCHDOG: enp1s0 (r8169): transmit queue 0 timed out and pcieport 0000:00:02.0: AER: Uncorrected (Non-Fatal) error received: 0000:01:00.0 r8169 0000:01:00.0: AER: PCIe Bus Error: severity=Uncorrected (Non-Fatal), type=Transaction Layer, (Requester ID) r8169 0000:01:00.0: AER: device [10ec:8168] error status/mask=00004000/00400000 r8169 0000:01:00.0: AER: [14] CmpltTO (First) r8169 0000:01:00.0: AER: can't recover (no error_detected callback) pcieport 0000:00:02.0: AER: device recovery failed After that, the ethernet NIC is not functional anymore even after reloading the r8169 module. After a reboot, this is reproducible by copying a large file over the NIC to the MMC. For some reason this is not reproducible when files are copied to a tmpfs. * Little background on the fixup, by Manikanta Maddireddy: "In the internal testing with dGPU on Tegra124, CmplTO is reported by dGPU. This happened because FIFO queue in AFI(AXI to PCIe) module get full by upstream posted writes. Back to back upstream writes interleaved with infrequent reads, triggers RAW violation and CmpltTO. This is fixed by reducing the posted write credits and by changing updateFC timer frequency. These settings are fixed after stress test. In the current case, RTL NIC is also reporting CmplTO. These settings seems to be aggravating the issue instead of fixing it." Link: https://lore.kernel.org/r/[email protected] Fixes: 191cd6fb5d2c ("PCI: tegra: Add SW fixup for RAW violations") Signed-off-by: Nicolas Chauvet <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Manikanta Maddireddy <[email protected]> Cc: [email protected]
2020-07-17PCI: dwc: Convert to devm_platform_ioremap_resource_byname()Dejin Zheng9-46/+23
Use devm_platform_ioremap_resource_byname() to simplify the code since it contains platform_get_resource_byname() and devm_ioremap_resource() respectively. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dejin Zheng <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Gustavo Pimentel <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-07-14irqdomain/treewide: Keep firmware node unconditionally allocatedThomas Gleixner1-2/+3
Quite some non OF/ACPI users of irqdomains allocate firmware nodes of type IRQCHIP_FWNODE_NAMED or IRQCHIP_FWNODE_NAMED_ID and free them right after creating the irqdomain. The only purpose of these FW nodes is to convey name information. When this was introduced the core code did not store the pointer to the node in the irqdomain. A recent change stored the firmware node pointer in irqdomain for other reasons and missed to notice that the usage sites which do the alloc_fwnode/create_domain/free_fwnode sequence are broken by this. Storing a dangling pointer is dangerous itself, but in case that the domain is destroyed later on this leads to a double free. Remove the freeing of the firmware node after creating the irqdomain from all affected call sites to cure this. Fixes: 711419e504eb ("irqdomain: Add the missing assignment of domain->fwnode for named fwnode") Reported-by: Andy Shevchenko <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Acked-by: Marc Zyngier <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected]
2020-07-14PCI: mvebu: Setup BAR0 in order to fix MSIShmuel Hazan1-4/+12
According to the Armada XP datasheet, section 10.2.6: "in order for the device to do a write to the MSI doorbell address, it needs to write to a register in the internal registers space". As a result of the requirement above, without this patch, MSI won't function and therefore some devices won't operate properly without pci=nomsi. This requirement was not present at the time of writing this driver since the vendor u-boot always initializes all PCIe controllers (incl. BAR0 initialization) and for some time, the vendor u-boot was the only available bootloader for this driver's SoCs (e.g. A38x,A37x, etc). Tested on an Armada 385 board on mainline u-boot (2020.4), without u-boot PCI initialization and the following PCIe devices: - Wilocity Wil6200 rev 2 (wil6210) - Qualcomm Atheros QCA6174 (ath10k_pci) Both failed to get a response from the device after loading the firmware and seem to operate properly with this patch. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Shmuel Hazan <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Thomas Petazzoni <[email protected]>
2020-07-10PCI: controller: Convert to devm_platform_ioremap_resource()Dejin Zheng5-16/+7
Use devm_platform_ioremap_resource() to simplify the code, since t contains platform_get_resource() and devm_ioremap_resource() calls respectively. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dejin Zheng <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-07-10PCI: controller: Convert to devm_platform_ioremap_resource_byname()Dejin Zheng8-25/+13
Use devm_platform_ioremap_resource_byname() to simplify the code, since it calls respectively platform_get_resource_byname() and devm_ioremap_resource(). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dejin Zheng <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Gustavo Pimentel <[email protected]>
2020-07-10PCI: xilinx: Use pci_host_probe() to register hostRob Herring1-12/+1
The xilinx host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. The only difference is pci_assign_unassigned_bus_resources() was called instead of pci_bus_size_bridges() and pci_bus_assign_resources(). This should be the same. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Michal Simek <[email protected]>
2020-07-10PCI: xilinx-nwl: Use pci_host_probe() to register hostRob Herring1-13/+1
The xilinx-nwl host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. The only difference is pci_assign_unassigned_bus_resources() was called instead of pci_bus_size_bridges() and pci_bus_assign_resources(). This should be the same. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Michal Simek <[email protected]>
2020-07-10PCI: rockchip: Use pci_host_probe() to register hostRob Herring2-15/+4
The rockchip host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Shawn Lin <[email protected]> Cc: Heiko Stuebner <[email protected]> Cc: [email protected]
2020-07-10PCI: rcar: Use pci_host_probe() to register hostRob Herring1-17/+1
The rcar host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Cc: Marek Vasut <[email protected]> Cc: Yoshihiro Shimoda <[email protected]> Cc: [email protected]
2020-07-10PCI: iproc: Use pci_host_probe() to register hostRob Herring2-15/+5
The iproc host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. The only difference is pci_assign_unassigned_bus_resources() was called instead of pci_bus_size_bridges() and pci_bus_assign_resources(). This should be the same. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Scott Branden <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Ray Jui <[email protected]> Cc: Scott Branden <[email protected]> Cc: [email protected]
2020-07-10PCI: altera: Use pci_host_probe() to register hostRob Herring1-16/+1
The altera host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. The only difference is pci_assign_unassigned_bus_resources() was called instead of pci_bus_size_bridges() and pci_bus_assign_resources(). This should be the same. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Ley Foon Tan <[email protected]> Cc: Ley Foon Tan <[email protected]> Cc: [email protected]
2020-07-10PCI: xgene: Use pci_host_probe() to register hostRob Herring1-12/+1
The xgene host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Toan Le <[email protected]>
2020-07-10PCI: versatile: Use pci_host_probe() to register hostRob Herring1-13/+1
The versatile host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]>
2020-07-10PCI: v3: Use pci_host_probe() to register hostRob Herring1-12/+1
The v3 host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Cc: Linus Walleij <[email protected]>
2020-07-10PCI: tegra: Use pci_host_probe() to register hostRob Herring1-10/+1
The tegra host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected]
2020-07-10PCI: mobiveil: Use pci_host_probe() to register hostRob Herring1-15/+1
The mobiveil host driver does the same host registration and bus scanning calls as pci_host_probe, so let's use it instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Karthikeyan Mitran <[email protected]> Cc: Hou Zhiqiang <[email protected]>