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2021-11-13Merge tag 'mips_5.16_1' of ↵Linus Torvalds1-1/+2
git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull more MIPS updates from Thomas Bogendoerfer: - Config updates for BMIPS platform - Build fixes - Makefile cleanups * tag 'mips_5.16_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: mips: decompressor: do not copy source files while building MIPS: boot/compressed/: add __bswapdi2() to target for ZSTD decompression MIPS: fix duplicated slashes for Platform file path MIPS: fix *-pkg builds for loongson2ef platform PCI: brcmstb: Allow building for BMIPS_GENERIC MIPS: BMIPS: Enable PCI Kconfig MIPS: VDSO: remove -nostdlib compiler flag mips: BCM63XX: ensure that CPU_SUPPORTS_32BIT_KERNEL is set MIPS: Update bmips_stb_defconfig MIPS: Allow modules to set board_be_handler
2021-11-09PCI: brcmstb: Allow building for BMIPS_GENERICFlorian Fainelli1-1/+2
BMIPS_GENERIC denotes support for the MIPS-based Broadcom STB platforms which this driver can support. Signed-off-by: Florian Fainelli <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
2021-11-06Merge tag 'pci-v5.16-changes' of ↵Linus Torvalds28-409/+3184
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull pci updates from Bjorn Helgaas: "Enumeration: - Conserve IRQs by setting up portdrv IRQs only when there are users (Jan Kiszka) - Rework and simplify _OSC negotiation for control of PCIe features (Joerg Roedel) - Remove struct pci_dev.driver pointer since it's redundant with the struct device.driver pointer (Uwe Kleine-König) Resource management: - Coalesce contiguous host bridge apertures from _CRS to accommodate BARs that cover more than one aperture (Kai-Heng Feng) Sysfs: - Check CAP_SYS_ADMIN before parsing user input (Krzysztof Wilczyński) - Return -EINVAL consistently from "store" functions (Krzysztof Wilczyński) - Use sysfs_emit() in endpoint "show" functions to avoid buffer overruns (Kunihiko Hayashi) PCIe native device hotplug: - Ignore Link Down/Up caused by resets during error recovery so endpoint drivers can remain bound to the device (Lukas Wunner) Virtualization: - Avoid bus resets on Atheros QCA6174, where they hang the device (Ingmar Klein) - Work around Pericom PI7C9X2G switch packet drop erratum by using store and forward mode instead of cut-through (Nathan Rossi) - Avoid trying to enable AtomicOps on VFs; the PF setting applies to all VFs (Selvin Xavier) MSI: - Document that /sys/bus/pci/devices/.../irq contains the legacy INTx interrupt or the IRQ of the first MSI (not MSI-X) vector (Barry Song) VPD: - Add pci_read_vpd_any() and pci_write_vpd_any() to access anywhere in the possible VPD space; use these to simplify the cxgb3 driver (Heiner Kallweit) Peer-to-peer DMA: - Add (not subtract) the bus offset when calculating DMA address (Wang Lu) ASPM: - Re-enable LTR at Downstream Ports so they don't report Unsupported Requests when reset or hot-added devices send LTR messages (Mingchuang Qiao) Apple PCIe controller driver: - Add driver for Apple M1 PCIe controller (Alyssa Rosenzweig, Marc Zyngier) Cadence PCIe controller driver: - Return success when probe succeeds instead of falling into error path (Li Chen) HiSilicon Kirin PCIe controller driver: - Reorganize PHY logic and add support for external PHY drivers (Mauro Carvalho Chehab) - Support PERST# GPIOs for HiKey970 external PEX 8606 bridge (Mauro Carvalho Chehab) - Add Kirin 970 support (Mauro Carvalho Chehab) - Make driver removable (Mauro Carvalho Chehab) Intel VMD host bridge driver: - If IOMMU supports interrupt remapping, leave VMD MSI-X remapping enabled (Adrian Huang) - Number each controller so we can tell them apart in /proc/interrupts (Chunguang Xu) - Avoid building on UML because VMD depends on x86 bare metal APIs (Johannes Berg) Marvell Aardvark PCIe controller driver: - Define macros for PCI_EXP_DEVCTL_PAYLOAD_* (Pali Rohár) - Set Max Payload Size to 512 bytes per Marvell spec (Pali Rohár) - Downgrade PIO Response Status messages to debug level (Marek Behún) - Preserve CRS SV (Config Request Retry Software Visibility) bit in emulated Root Control register (Pali Rohár) - Fix issue in configuring reference clock (Pali Rohár) - Don't clear status bits for masked interrupts (Pali Rohár) - Don't mask unused interrupts (Pali Rohár) - Avoid code repetition in advk_pcie_rd_conf() (Marek Behún) - Retry config accesses on CRS response (Pali Rohár) - Simplify emulated Root Capabilities initialization (Pali Rohár) - Fix several link training issues (Pali Rohár) - Fix link-up checking via LTSSM (Pali Rohár) - Fix reporting of Data Link Layer Link Active (Pali Rohár) - Fix emulation of W1C bits (Marek Behún) - Fix MSI domain .alloc() method to return zero on success (Marek Behún) - Read entire 16-bit MSI vector in MSI handler, not just low 8 bits (Marek Behún) - Clear Root Port I/O Space, Memory Space, and Bus Master Enable bits at startup; PCI core will set those as necessary (Pali Rohár) - When operating as a Root Port, set class code to "PCI Bridge" instead of the default "Mass Storage Controller" (Pali Rohár) - Add emulation for PCI_BRIDGE_CTL_BUS_RESET since aardvark doesn't implement this per spec (Pali Rohár) - Add emulation of option ROM BAR since aardvark doesn't implement this per spec (Pali Rohár) MediaTek MT7621 PCIe controller driver: - Add MediaTek MT7621 PCIe host controller driver and DT binding (Sergio Paracuellos) Qualcomm PCIe controller driver: - Add SC8180x compatible string (Bjorn Andersson) - Add endpoint controller driver and DT binding (Manivannan Sadhasivam) - Restructure to use of_device_get_match_data() (Prasad Malisetty) - Add SC7280-specific pcie_1_pipe_clk_src handling (Prasad Malisetty) Renesas R-Car PCIe controller driver: - Remove unnecessary includes (Geert Uytterhoeven) Rockchip DesignWare PCIe controller driver: - Add DT binding (Simon Xue) Socionext UniPhier Pro5 controller driver: - Serialize INTx masking/unmasking (Kunihiko Hayashi) Synopsys DesignWare PCIe controller driver: - Run dwc .host_init() method before registering MSI interrupt handler so we can deal with pending interrupts left by bootloader (Bjorn Andersson) - Clean up Kconfig dependencies (Andy Shevchenko) - Export symbols to allow more modular drivers (Luca Ceresoli) TI DRA7xx PCIe controller driver: - Allow host and endpoint drivers to be modules (Luca Ceresoli) - Enable external clock if present (Luca Ceresoli) TI J721E PCIe driver: - Disable PHY when probe fails after initializing it (Christophe JAILLET) MicroSemi Switchtec management driver: - Return error to application when command execution fails because an out-of-band reset has cleared the device BARs, Memory Space Enable, etc (Kelvin Cao) - Fix MRPC error status handling issue (Kelvin Cao) - Mask out other bits when reading of management VEP instance ID (Kelvin Cao) - Return EOPNOTSUPP instead of ENOTSUPP from sysfs show functions (Kelvin Cao) - Add check of event support (Logan Gunthorpe) Miscellaneous: - Remove unused pci_pool wrappers, which have been replaced by dma_pool (Cai Huoqing) - Use 'unsigned int' instead of bare 'unsigned' (Krzysztof Wilczyński) - Use kstrtobool() directly, sans strtobool() wrapper (Krzysztof Wilczyński) - Fix some sscanf(), sprintf() format mismatches (Krzysztof Wilczyński) - Update PCI subsystem information in MAINTAINERS (Krzysztof Wilczyński) - Correct some misspellings (Krzysztof Wilczyński)" * tag 'pci-v5.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (137 commits) PCI: Add ACS quirk for Pericom PI7C9X2G switches PCI: apple: Configure RID to SID mapper on device addition iommu/dart: Exclude MSI doorbell from PCIe device IOVA range PCI: apple: Implement MSI support PCI: apple: Add INTx and per-port interrupt support PCI: kirin: Allow removing the driver PCI: kirin: De-init the dwc driver PCI: kirin: Disable clkreq during poweroff sequence PCI: kirin: Move the power-off code to a common routine PCI: kirin: Add power_off support for Kirin 960 PHY PCI: kirin: Allow building it as a module PCI: kirin: Add MODULE_* macros PCI: kirin: Add Kirin 970 compatible PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge PCI: apple: Set up reference clocks when probing PCI: apple: Add initial hardware bring-up PCI: of: Allow matching of an interrupt-map local to a PCI device of/irq: Allow matching of an interrupt-map local to an interrupt controller irqdomain: Make of_phandle_args_to_fwspec() generally available PCI: Do not enable AtomicOps on VFs ...
2021-11-05Merge branch 'remotes/lorenzo/pci/xgene'Bjorn Helgaas1-2/+1
- Use PCI_VENDOR_ID_AMCC macro instead of defining a custom macro in pci-xgene.c (Pali Rohár) * remotes/lorenzo/pci/xgene: PCI: xgene: Use PCI_VENDOR_ID_AMCC macro
2021-11-05Merge branch 'remotes/lorenzo/pci/vmd'Bjorn Helgaas2-10/+37
- Assign a number to each VMD controller to distinguish them in /proc/interrupts (Chunguang Xu) - Don't disable VMD MSI-X remapping if IOMMU remapping is enabled (Adrian Huang) - Add Kconfig dependency on !UML for allyesconfig build issue (Johannes Berg) * remotes/lorenzo/pci/vmd: PCI: vmd: depend on !UML PCI: vmd: Do not disable MSI-X remapping if interrupt remapping is enabled by IOMMU PCI: vmd: Assign a number to each VMD controller
2021-11-05Merge branch 'pci/host/rcar'Bjorn Helgaas2-6/+1
- Remove unneeded includes (Geert Uytterhoeven) * pci/host/rcar: PCI: rcar-host: Remove unneeded includes PCI: rcar-ep: Remove unneeded includes
2021-11-05Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas5-11/+819
- Add Qualcomm PCIe Endpoint controller driver and DT binding (Manivannan Sadhasivam) - Add qcom struct for device-specific details in match data (Prasad Malisetty) - Switch pcie_1_pipe_clk_src from TCXO to pipe clock after PHY init in SC7280 (Prasad Malisetty) - Add .compatible device ID for SC8180x platform (Bjorn Andersson) * remotes/lorenzo/pci/qcom: PCI: qcom: Add sc8180x compatible PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280 PCI: qcom: Replace ops with struct pcie_cfg in pcie match data MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver dt-bindings: PCI: Add Qualcomm PCIe Endpoint controller
2021-11-05Merge branch 'pci/host/mt7621'Bjorn Helgaas3-0/+610
- Add MediaTek MT7621 SoC PCIe host controller (moved from staging) (Sergio Paracuellos) * pci/host/mt7621: MAINTAINERS: Add Sergio Paracuellos as MT7621 PCIe maintainer PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver dt-bindings: PCI: Add MT7621 SoC PCIe host controller # Conflicts: # drivers/pci/controller/Kconfig # drivers/pci/controller/Makefile
2021-11-05Merge branch 'pci/host/kirin'Bjorn Helgaas2-149/+499
- Reorganize to separate out PHY logic (Mauro Carvalho Chehab) - Add support for external PHY in addition to the internal PHY (Mauro Carvalho Chehab) - Use regmap so both kirin driver and PHY can access APB registers (Mauro Carvalho Chehab) - Add support for per-lane PERST# GPIOs on HiKey970 external PEX 8606 PCI bridge (Mauro Carvalho Chehab) - Add "hisilicon,kirin970-pcie" compatible string (Mauro Carvalho Chehab) - Add MODULE_* macros (Mauro Carvalho Chehab) - Allow building as a module (Mauro Carvalho Chehab) - Add power_off support for Kirin 960 PHY (Mauro Carvalho Chehab) - Disable clkreq during poweroff sequence (Mauro Carvalho Chehab) - De-init the dwc driver during remove (Mauro Carvalho Chehab) - Allow removal of kirin driver (Mauro Carvalho Chehab) * pci/host/kirin: PCI: kirin: Allow removing the driver PCI: kirin: De-init the dwc driver PCI: kirin: Disable clkreq during poweroff sequence PCI: kirin: Move the power-off code to a common routine PCI: kirin: Add power_off support for Kirin 960 PHY PCI: kirin: Allow building it as a module PCI: kirin: Add MODULE_* macros PCI: kirin: Add Kirin 970 compatible PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge PCI: kirin: Use regmap for APB registers PCI: kirin: Add support for a PHY layer PCI: kirin: Reorganize the PHY logic inside the driver
2021-11-05Merge branch 'remotes/lorenzo/pci/imx6'Bjorn Helgaas1-1/+1
- Remove unused assignment (Krzysztof Wilczyński) * remotes/lorenzo/pci/imx6: PCI: imx6: Remove unused assignment to variable ret
2021-11-05Merge branch 'pci/host/dwc'Bjorn Helgaas7-41/+51
- Export dw_pcie_ep_reset_bar(), dw_pcie_link_up() so more drivers can be modular (Luca Ceresoli) - Allow dra7xx host and endpoint drivers to be modules (Luca Ceresoli) - Enable dra7xx optional external clock if present (Luca Ceresoli) - Clean up Kconfig dependencies for PCIE_DW_HOST- and PCIE_DW_EP-based drivers (Andy Shevchenko) - Remove visconti redundant dev_err() after platform_get_irq_byname() failure (Krzysztof Wilczyński) - Run dwc .host_init() method before registering MSI interrupt handler so we have a chance to deal with pending interrupts left by bootloader (Bjorn Andersson) - Serialize uniphier INTx masking/unmasking (Kunihiko Hayashi) * pci/host/dwc: PCI: uniphier: Serialize INTx masking/unmasking and fix the bit operation PCI: dwc: Perform host_init() before registering msi PCI: visconti: Remove surplus dev_err() when using platform_get_irq_byname() PCI: dwc: Clean up Kconfig dependencies (PCIE_DW_EP) PCI: dwc: Clean up Kconfig dependencies (PCIE_DW_HOST) PCI: dra7xx: Get an optional clock PCI: dra7xx: Remove unused include PCI: dra7xx: Make it a kernel module PCI: dwc: Export more symbols to allow modular drivers
2021-11-05Merge branch 'pci/host/cadence'Bjorn Helgaas2-1/+3
- Disable PHY when j721e_pcie_probe() fails after initializing it (Christophe JAILLET) - Return success when cdns-pcie probe succeeds instead of doing error cleanup (Li Chen) * pci/host/cadence: PCI: cadence: Add cdns_plat_pcie_probe() missing return PCI: j721e: Fix j721e_pcie_probe() error path
2021-11-05Merge branch 'pci/host/apple'Bjorn Helgaas3-0/+843
- Make of_phandle_args_to_fwspec() generally available (Marc Zyngier) - Allow matching of interrupt-maps local to interrupt controller or PCI device (Marc Zyngier) - Add Apple SoC (e.g., M1) PCIe host controller driver, which enables access to USB type-A, Ethernet, Wi-Fi, Bluetooth devices; these require additional drivers of their own (Alyssa Rosenzweig) - Add apple INTx, per-port, and MSI interrupt support (Marc Zyngier) - Configure apple Requester-ID-to-Stream-ID mapper for IOMMU (DART) support (Marc Zyngier) * pci/host/apple: PCI: apple: Configure RID to SID mapper on device addition iommu/dart: Exclude MSI doorbell from PCIe device IOVA range PCI: apple: Implement MSI support PCI: apple: Add INTx and per-port interrupt support PCI: apple: Set up reference clocks when probing PCI: apple: Add initial hardware bring-up PCI: of: Allow matching of an interrupt-map local to a PCI device of/irq: Allow matching of an interrupt-map local to an interrupt controller irqdomain: Make of_phandle_args_to_fwspec() generally available
2021-11-05Merge branch 'remotes/lorenzo/pci/aardvark'Bjorn Helgaas1-179/+312
- Define macros for PCI_EXP_DEVCTL_PAYLOAD_* (Pali Rohár) - Set Max Payload Size to 512 bytes per Marvell spec (Pali Rohár) - Downgrade PIO Response Status messages to debug level (Marek Behún) - Preserve CRS SV (Config Request Retry Software Visibility) bit in emulated Root Control register (Pali Rohár) - Fix issue in configuring reference clock (Pali Rohár) - Don't clear status bits for masked interrupts (Pali Rohár) - Don't mask unused interrupts (Pali Rohár) - Avoid code repetition in advk_pcie_rd_conf() (Marek Behún) - Retry config accesses on CRS response (Pali Rohár) - Simplify emulated Root Capabilities initialization (Pali Rohár) - Fix several link training issues (Pali Rohár) - Fix link-up checking via LTSSM (Pali Rohár) - Fix reporting of Data Link Layer Link Active (Pali Rohár) - Fix emulation of W1C bits (Marek Behún) - Fix MSI domain .alloc() method to return zero on success (Marek Behún) - Read entire 16-bit MSI vector in MSI handler, not just low 8 bits (Marek Behún) - Clear Root Port I/O Space, Memory Space, and Bus Master Enable bits at startup; PCI core will set those as necessary (Pali Rohár) - When operating as a Root Port, set class code to "PCI Bridge" instead of the default "Mass Storage Controller" (Pali Rohár) - Add emulation for PCI_BRIDGE_CTL_BUS_RESET since aardvark doesn't implement this per spec (Pali Rohár) - Add emulation of option ROM BAR since aardvark doesn't implement this per spec (Pali Rohár) * remotes/lorenzo/pci/aardvark: PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridge PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridge PCI: aardvark: Set PCI Bridge Class Code to PCI Bridge PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridge PCI: aardvark: Read all 16-bits from PCIE_MSI_PAYLOAD_REG PCI: aardvark: Fix return value of MSI domain .alloc() method PCI: pci-bridge-emul: Fix emulation of W1C bits PCI: aardvark: Fix reporting Data Link Layer Link Active PCI: aardvark: Fix checking for link up via LTSSM state PCI: aardvark: Fix link training PCI: aardvark: Simplify initialization of rootcap on virtual bridge PCI: aardvark: Implement re-issuing config requests on CRS response PCI: aardvark: Deduplicate code in advk_pcie_rd_conf() PCI: aardvark: Do not unmask unused interrupts PCI: aardvark: Do not clear status bits of masked interrupts PCI: aardvark: Fix configuring Reference clock PCI: aardvark: Fix preserving PCI_EXP_RTCTL_CRSSVE flag on emulated bridge PCI: aardvark: Don't spam about PIO Response Status PCI: aardvark: Fix PCIe Max Payload Size setting PCI: Add PCI_EXP_DEVCTL_PAYLOAD_* macros
2021-11-04PCI: apple: Configure RID to SID mapper on device additionMarc Zyngier1-2/+163
The Apple PCIe controller doesn't directly feed the endpoint's Requester ID to the IOMMU (DART), but instead maps RIDs onto Stream IDs (SIDs). The DART and the PCIe controller must thus agree on the SIDs that are used for translation (by using the 'iommu-map' property). For this purpose, parse the 'iommu-map' property each time a device gets added, and use the resulting translation to configure the PCIe RID-to-SID mapper. Similarly, remove the translation if/when the device gets removed. This is all driven from a bus notifier which gets registered at probe time. Hopefully this is the only PCI controller driver in the whole system. [bhelgaas: squash indentation from Zhaoyu Liu <[email protected]>: https://lore.kernel.org/r/20211031135544.GA1616@pc] Link: https://lore.kernel.org/r/[email protected] Tested-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Sven Peter <[email protected]>
2021-11-04iommu/dart: Exclude MSI doorbell from PCIe device IOVA rangeMarc Zyngier2-1/+8
The MSI doorbell on Apple HW can be any address in the low 4GB range. However, the MSI write is matched by the PCIe block before hitting the iommu. It must thus be excluded from the IOVA range that is assigned to any PCIe device. Link: https://lore.kernel.org/r/[email protected] Tested-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Sven Peter <[email protected]>
2021-11-04PCI: apple: Implement MSI supportMarc Zyngier1-1/+168
Probe for the 'msi-ranges' property, and implement the MSI support in the form of the usual two-level hierarchy. Note that contrary to the wired interrupts, MSIs are shared among all the ports. Link: https://lore.kernel.org/r/[email protected] Tested-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-11-04PCI: apple: Add INTx and per-port interrupt supportMarc Zyngier1-0/+210
Add support for the per-port interrupt controller that deals with both INTx signalling and management interrupts. This allows the Link-up/Link-down interrupts to be wired, allowing the bring-up to be synchronised (and provide debug information). The framework can further be used to handle the rest of the per port events if and when necessary. Likewise, INTx signalling is implemented so that end-points can actually be used. Link: https://lore.kernel.org/r/[email protected] Link: https://lore.kernel.org/r/[email protected] Tested-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-11-04PCI: kirin: Allow removing the driverMauro Carvalho Chehab1-1/+1
Now that everything is in place at the poweroff sequence, this driver can use module_platform_driver(), which allows it to be removed. Link: https://lore.kernel.org/r/53b40494252444a9b830827922c4e3a301b8f863.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]>
2021-11-04PCI: kirin: De-init the dwc driverMauro Carvalho Chehab1-0/+2
The logic under .remove ops is missing a call to dw_pcie_host_deinit(). Add it, in order to allow the DWC core to be properly cleaned up. Link: https://lore.kernel.org/r/838621e1c84ebaac153ccd9c36ea5e1254c61ead.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]>
2021-11-04PCI: kirin: Disable clkreq during poweroff sequenceMauro Carvalho Chehab1-0/+3
The logic at kirin_pcie_gpio_request() enables some clkreq GPIO lines. Disable them during power-off. Link: https://lore.kernel.org/r/f403e590843de1a581cade2d534d34715706f54e.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]>
2021-11-04PCI: kirin: Move the power-off code to a common routineMauro Carvalho Chehab1-11/+15
Instead of having two copies of the same logic, place the power-off logic in a separate function. No functional changes. Link: https://lore.kernel.org/r/64f6e8da3e5fff38b6c8fcb208ace46efe6555bb.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]>
2021-11-04PCI: kirin: Add power_off support for Kirin 960 PHYMauro Carvalho Chehab1-3/+18
In order to prepare for module unload, add a power_off method for HiKey 960. Link: https://lore.kernel.org/r/b095818b0d7fadae4cae200f481caf7a66e61fb4.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]>
2021-11-04PCI: kirin: Allow building it as a moduleMauro Carvalho Chehab1-1/+1
There's nothing preventing this driver from being loaded as a module. Change its config from bool to tristate. Link: https://lore.kernel.org/r/b5e7cfe9df09b492750bd6db0f0c911eaae8c2d4.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]>
2021-11-04PCI: kirin: Add MODULE_* macrosMauro Carvalho Chehab1-0/+5
This driver misses the MODULE_* macros. Add them. Link: https://lore.kernel.org/r/f7a951d0c2009f5765214fc2e83e24cf41585023.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]>
2021-11-04PCI: kirin: Add Kirin 970 compatibleMauro Carvalho Chehab1-0/+4
Now that everything is in place, add a compatible for Kirin 970. Link: https://lore.kernel.org/r/ac8c730c0300b90d96bdaaf387d458d8949241a9.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]>
2021-11-04PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridgeMauro Carvalho Chehab1-32/+233
On HiKey970, there's a PEX 8606 PCI bridge on its PHY with 6 lanes. Only 4 lanes are connected: lane 0 - connected to Kirin 970 (upstream) lane 4 - M.2 slot lane 5 - mini PCIe slot lane 6 - on-board Ethernet controller Each lane has its own PERST# GPIO pin and needs a clock request. Add support to parse a DT schema containing the above data. HiKey 970 requires a little more waiting time for the PCI bridge - which is outside the SoC - to finish the PERST# reset, and then initialize the eye diagram. Increase the waiting time for the PERST# signals accordingly. [bhelgaas: squash refcount fix from Wan Jiabing <[email protected]>: https://lore.kernel.org/r/[email protected] and drop "parent" refcount per https://lore.kernel.org/all/20211103143059.GA683503@bhelgaas/] Link: https://lore.kernel.org/r/bb391a0e0f0863b66e645048315fab1a4f63f277.1634812676.git.mchehab+huawei@kernel.org Link: https://lore.kernel.org/all/9a365cffe5af9ec5a1f79638968c3a2efa979b65.1634622716.git.mchehab+huawei@kernel.org/ Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]>
2021-11-04PCI: apple: Set up reference clocks when probingAlyssa Rosenzweig1-0/+46
Apple's PCIe controller requires clocks to be configured in order to bring up the hardware. Add the register pokes required to do so. Adapted from Corellium's driver via Mark Kettenis's U-Boot patches. Co-developed-by: Stan Skowronek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stan Skowronek <[email protected]> Signed-off-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-11-04PCI: apple: Add initial hardware bring-upAlyssa Rosenzweig3-0/+252
Add a minimal driver to bring up the PCIe bus on Apple system-on-chips, particularly the Apple M1. This driver exposes the internal bus used for the USB type-A ports, Ethernet, Wi-Fi, and Bluetooth. Bringing up the radios requires additional drivers beyond what's necessary for PCIe itself. Co-developed-by: Stan Skowronek <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stan Skowronek <[email protected]> Signed-off-by: Alyssa Rosenzweig <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Sven Peter <[email protected]>
2021-11-04PCI: vmd: Drop redundant includes of <asm/device.h>, <asm/msi.h>Krzysztof Wilczyński1-2/+0
We already include <linux/device.h> and <linux/msi.h>, which include <asm/device.h> and <asm/msi.h>. Drop the redundant includes of <asm/device.h> and <asm/msi.h>. [bhelgaas: squash in fix from Wan Jiabing <[email protected]>: https://lore.kernel.org/r/[email protected]] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Jonathan Derrick <[email protected]>
2021-11-03PCI: cadence: Add cdns_plat_pcie_probe() missing returnLi Chen1-0/+2
When cdns_plat_pcie_probe() succeeds, return success instead of falling into the error handling code. Fixes: bd22885aa188 ("PCI: cadence: Refactor driver to use as a core library") Link: https://lore.kernel.org/r/DM6PR19MB40271B93057D949310F0B0EDA0BF9@DM6PR19MB4027.namprd19.prod.outlook.com Signed-off-by: Xuliang Zhang <[email protected]> Signed-off-by: Li Chen <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Bjorn Helgaas <[email protected]> Cc: [email protected]
2021-11-03PCI: j721e: Fix j721e_pcie_probe() error pathChristophe JAILLET1-1/+1
If an error occurs after a successful cdns_pcie_init_phy() call, it must be undone by a cdns_pcie_disable_phy() call, as already done above and below. Update the goto to branch at the correct place of the error handling path. Link: https://lore.kernel.org/r/db477b0cb444891a17c4bb424467667dc30d0bab.1624794264.git.christophe.jaillet@wanadoo.fr Fixes: 49e0efdce791 ("PCI: j721e: Add support to provide refclk to PCIe connector") Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Krzysztof Wilczyński <[email protected]>
2021-11-02PCI: kirin: Use regmap for APB registersMauro Carvalho Chehab1-23/+26
The PHY layer need to access APB registers too, for Kirin 970. So place them into a named regmap. Link: https://lore.kernel.org/r/daf0e4bda5a69a5ac8484e70f09351a959805c8c.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]>
2021-11-02PCI: kirin: Add support for a PHY layerMauro Carvalho Chehab1-14/+79
The pcie-kirin driver contains both PHY and generic PCI driver. The best would be, instead, to support a PCI PHY driver, making the driver more generic. However, it is too late to remove the Kirin 960 PHY, as a change like that would make the DT schema incompatible with past versions. So, add support for an external PHY driver without removing the existing Kirin 960 PHY from it. Link: https://lore.kernel.org/r/f38361df2e9d0dc5a38ff942b631f7fef64cdc12.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Kishon Vijay Abraham I <[email protected]> Acked-by: Xiaowei Song <[email protected]>
2021-11-02PCI: kirin: Reorganize the PHY logic inside the driverMauro Carvalho Chehab1-122/+170
The pcie-kirin PCIe driver contains internally a PHY interface for Kirin 960. As the next patches will add support for using an external PHY driver, reorganize the driver in a way that the PHY part will be self-contained. This could be moved to a separate PHY driver, but a change like that would mean a non-backward-compatible DT schema change. Link: https://lore.kernel.org/r/ad2f4aa6bbb71d5c9af0139704672f75f12644fc.1634812676.git.mchehab+huawei@kernel.org Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Xiaowei Song <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]>
2021-10-29PCI: aardvark: Fix support for PCI_ROM_ADDRESS1 on emulated bridgePali Rohár1-0/+9
This register is exported at address offset 0x30. Link: https://lore.kernel.org/r/[email protected] Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: [email protected]
2021-10-29PCI: aardvark: Fix support for PCI_BRIDGE_CTL_BUS_RESET on emulated bridgePali Rohár1-0/+27
Aardvark supports PCIe Hot Reset via PCIE_CORE_CTRL1_REG. Use it for implementing PCI_BRIDGE_CTL_BUS_RESET bit of PCI_BRIDGE_CONTROL register on emulated bridge. With this, the function pci_reset_secondary_bus() starts working and can reset connected PCIe card. Custom userspace script [1] which uses setpci can trigger PCIe Hot Reset and reset the card manually. [1] https://alexforencich.com/wiki/en/pcie/hot-reset-linux Link: https://lore.kernel.org/r/[email protected] Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: [email protected]
2021-10-29PCI: aardvark: Set PCI Bridge Class Code to PCI BridgePali Rohár1-0/+20
Aardvark controller has something like config space of a Root Port available at offset 0x0 of internal registers - these registers are used for implementation of the emulated bridge. The default value of Class Code of this bridge corresponds to a RAID Mass storage controller, though. (This is probably intended for when the controller is used as Endpoint.) Change the Class Code to correspond to a PCI Bridge. Add comment explaining this change. Link: https://lore.kernel.org/r/[email protected] Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: [email protected]
2021-10-29PCI: aardvark: Fix support for bus mastering and PCI_COMMAND on emulated bridgePali Rohár1-16/+38
From very vague, ambiguous and incomplete information from Marvell we deduced that the 32-bit Aardvark register at address 0x4 (PCIE_CORE_CMD_STATUS_REG), which is not documented for Root Complex mode in the Functional Specification (only for Endpoint mode), controls two 16-bit PCIe registers: Command Register and Status Registers of PCIe Root Port. This means that bit 2 controls bus mastering and forwarding of memory and I/O requests in the upstream direction. According to PCI specifications bits [0:2] of Command Register, this should be by default disabled on reset. So explicitly disable these bits at early setup of the Aardvark driver. Remove code which unconditionally enables all 3 bits and let kernel code (via pci_set_master() function) to handle bus mastering of Root PCIe Bridge via emulated PCI_COMMAND on emulated bridge. Link: https://lore.kernel.org/r/[email protected] Fixes: 8a3ebd8de328 ("PCI: aardvark: Implement emulated root PCI bridge config space") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: [email protected] # b2a56469d550 ("PCI: aardvark: Add FIXME comment for PCIE_CORE_CMD_STATUS_REG access")
2021-10-29PCI: aardvark: Read all 16-bits from PCIE_MSI_PAYLOAD_REGMarek Behún1-1/+6
The PCIE_MSI_PAYLOAD_REG contains 16-bit MSI number, not only lower 8 bits. Fix reading content of this register and add a comment describing the access to this register. Link: https://lore.kernel.org/r/[email protected] Fixes: 8c39d710363c ("PCI: aardvark: Add Aardvark PCI host controller driver") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: [email protected]
2021-10-29PCI: aardvark: Fix return value of MSI domain .alloc() methodMarek Behún1-1/+1
MSI domain callback .alloc() (implemented by advk_msi_irq_domain_alloc() function) should return zero on success, since non-zero value indicates failure. When the driver was converted to generic MSI API in commit f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support"), it was converted so that it returns hwirq number. Fix this. Link: https://lore.kernel.org/r/[email protected] Fixes: f21a8b1b6837 ("PCI: aardvark: Move to MSI handling using generic MSI support") Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: [email protected]
2021-10-27PCI: Prefer 'unsigned int' over bare 'unsigned'Krzysztof Wilczyński1-2/+2
The bare "unsigned" type implicitly means "unsigned int", but the preferred coding style is to use the complete type name. Update the bare use of "unsigned" to the preferred "unsigned int". No change to functionality intended. See a1ce18e4f941 ("checkpatch: warn on bare unsigned or signed declarations without int"). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-10-21PCI: mt7621: Add MediaTek MT7621 PCIe host controller driverSergio Paracuellos3-0/+610
Add driver for the PCIe controller of the MT7621 SoC. [bhelgaas: rename from pci-mt7621.c to pcie-mt7621.c; also rename Kconfig symbol from PCI_MT7621 to PCIE_MT7621] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]>
2021-10-15PCI: uniphier: Serialize INTx masking/unmasking and fix the bit operationKunihiko Hayashi1-16/+10
The condition register PCI_RCV_INTX is used in irq_mask() and irq_unmask() callbacks. Accesses to register can occur at the same time without a lock. Add a lock into each callback to prevent the issue. And INTX mask and unmask fields in PCL_RCV_INTX register should only be set/reset for each bit. Clearing by PCL_RCV_INTX_ALL_MASK should be removed. INTX status fields in PCL_RCV_INTX register only indicates each INTX interrupt status, so the handler can't clear by writing 1 to the field. The status is expected to be cleared by the interrupt origin. The ack function has no meaning, so should remove it. Suggested-by: Pali Rohár <[email protected]> Link: https://lore.kernel.org/r/[email protected] Fixes: 7e6d5cd88a6f ("PCI: uniphier: Add UniPhier PCIe host controller support") Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Pali Rohár <[email protected]> Acked-by: Marc Zyngier <[email protected]>
2021-10-15PCI: qcom: Add sc8180x compatibleBjorn Andersson1-0/+1
The SC8180x platform comes with 4 PCIe controllers, typically used for things such as NVME storage or connecting a SDX55 5G modem. Add a compatible for this, that just reuses the 1.9.0 ops. Link: https://lore.kernel.org/linux-arm-msm/[email protected]/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]> [[email protected]: updated match data structure] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2021-10-14PCI: qcom: Switch pcie_1_pipe_clk_src after PHY init in SC7280Prasad Malisetty1-0/+29
On the SC7280, the clock source for gcc_pcie_1_pipe_clk_src must be the TCXO while gdsc is enabled. After PHY init successful clock source should switch to pipe clock for gcc_pcie_1_pipe_clk_src. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Prasad Malisetty <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Stephen Boyd <[email protected]>
2021-10-14PCI: qcom: Replace ops with struct pcie_cfg in pcie match dataPrasad Malisetty1-11/+55
Add struct qcom_pcie_cfg as match data for all platforms. Assign appropriate platform ops into struct qcom_pcie_cfg and read using of_device_get_match_data() in qcom_pcie_probe(). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Prasad Malisetty <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Stephen Boyd <[email protected]>
2021-10-13PCI: vmd: depend on !UMLJohannes Berg1-1/+1
With UML having enabled (simulated) PCI on UML, VMD breaks allyesconfig/allmodconfig compilation because it assumes it's running on X86_64 bare metal, and has hardcoded API use of ARCH=x86. Make it depend on !UML to fix this. Link: https://lore.kernel.org/r/20210811162530.affe26231bc3.I131b3c1e67e3d2ead6e98addd256c835fbef9a3e@changeid Signed-off-by: Johannes Berg <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Jon Derrick <[email protected]> Acked-by: Randy Dunlap <[email protected]> # build-tested
2021-10-12PCI: hv: Remove unnecessary use of %hxKrzysztof Wilczyński1-2/+2
"dom_req" is a u16 but varargs automatically promotes it to int, so there's no point in using the %h modifier. Drop it. See cbacb5ab0aa0 ("docs: printk-formats: Stop encouraging use of unnecessary %h[xudi] and %hh[xudi]") and 70eb2275ff8e ("checkpatch: add warning for unnecessary use of %h[xudi] and %hh[xudi]"). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Wilczyński <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2021-10-12PCI: vmd: Do not disable MSI-X remapping if interrupt remapping is enabled ↵Adrian Huang1-1/+3
by IOMMU When enabling VMD in BIOS setup (Ice Lake Processor: Whitley platform), the host OS cannot boot successfully with the following error message: nvme nvme0: I/O 12 QID 0 timeout, completion polled nvme nvme0: Shutdown timeout set to 6 seconds DMAR: DRHD: handling fault status reg 2 DMAR: [INTR-REMAP] Request device [0x00:0x00.5] fault index 0xa00 [fault reason 0x25] Blocked a compatibility format interrupt request The request device is the VMD controller: # lspci -s 0000:00.5 -nn 0000:00:00.5 RAID bus controller [0104]: Intel Corporation Volume Management Device NVMe RAID Controller [8086:28c0] (rev 04) `git bisect` points to this offending commit ee81ee84f873 ("PCI: vmd: Disable MSI-X remapping when possible"), which disables VMD MSI remapping. The IOMMU hardware blocks the compatibility format interrupt request because Interrupt Remapping Enable Status (IRES) and Extended Interrupt Mode Enable (EIME) are enabled. Please refer to section "5.1.4 Interrupt-Remapping Hardware Operation" in Intel VT-d spec. To fix the issue, VMD driver still enables the interrupt remapping irrespective of VMD_FEAT_CAN_BYPASS_MSI_REMAP if the IOMMU subsystem enables the interrupt remapping. Test configuration is shown as follows: * Two VMD controllers 1. 8086:28c0 (Whitley's VMD) 2. 8086:201d (Purley's VMD: The issue does not appear in this controller. Just make sure if any side effect occurs.) * w/wo intremap=off Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=214219 Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Adrian Huang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Jon Derrick <[email protected]> Cc: Jon Derrick <[email protected]> Cc: Nirmal Patel <[email protected]> Cc: Joerg Roedel <[email protected]>
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