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2022-11-10PCI: microchip: Include <linux/irqdomain.h> explicitlyBjorn Helgaas1-0/+1
pcie-microchip-host.c uses irq_domain_add_linear() and related interfaces, so it needs <linux/irqdomain.h> but doesn't include it directly; it relies on the fact that <linux/of_irq.h> includes it. But pcie-microchip-host.c *doesn't* need <linux/of_irq.h> itself. Include <linux/irqdomain.h> directly to remove this implicit dependency so a future patch can drop <linux/of_irq.h>. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Conor Dooley <[email protected]>
2022-11-10PCI: altera-msi: Include <linux/irqdomain.h> explicitlyBjorn Helgaas1-0/+1
pcie-altera-msi.c uses irq_domain_add_linear() and related interfaces, so it needs <linux/irqdomain.h> but doesn't include it directly; it relies on the fact that <linux/of_irq.h> includes it. But pcie-altera-msi.c *doesn't* need <linux/of_irq.h> itself. Include <linux/irqdomain.h> directly to remove this implicit dependency so a future patch can drop <linux/of_irq.h>. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Helgaas <[email protected]>
2022-11-10PCI: dwc: Use dev_info for PCIe link down event loggingVidya Sagar1-1/+1
Some of the platforms (like Tegra194 and Tegra234) have open slots and not having an endpoint connected to the slot is not an error. So, changing the macro from dev_err to dev_info to log the event. Link: https://lore.kernel.org/r/[email protected] Tested-by: Jon Hunter <[email protected]> Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Jon Hunter <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
2022-11-10PCI: qcom: Fix error message for reset_control_assert()Manivannan Sadhasivam1-1/+1
Fix the error message to mention "assert" instead of "deassert". Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Vinod Koul <[email protected]>
2022-11-03PCI: hv: Fix the definition of vector in hv_compose_msi_msg()Dexuan Cui1-6/+16
The local variable 'vector' must be u32 rather than u8: see the struct hv_msi_desc3. 'vector_count' should be u16 rather than u8: see struct hv_msi_desc, hv_msi_desc2 and hv_msi_desc3. Fixes: a2bad844a67b ("PCI: hv: Fix interrupt mapping for multi-MSI") Signed-off-by: Dexuan Cui <[email protected]> Cc: Jeffrey Hugo <[email protected]> Cc: Carl Vanderlip <[email protected]> Reviewed-by: Jeffrey Hugo <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Wei Liu <[email protected]>
2022-10-27PCI: tegra: Switch to using devm_fwnode_gpiod_getDmitry Torokhov1-4/+5
[devm_]gpiod_get_from_of_node in drivers usage should be limited so that gpiolib can be cleaned up; let's switch to the generic device property API. It may even help with handling secondary fwnodes when gpiolib is taught to handle gpios described by swnodes. Link: https://lore.kernel.org/r/20220903-gpiod_get_from_of_node-remove-v1-1-b29adfb27a6c@gmail.com Signed-off-by: Dmitry Torokhov <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Linus Walleij <[email protected]>
2022-10-27PCI: designware-ep: Disable PTM capabilities for EP modeVidya Sagar1-1/+18
Dual mode DesignWare PCIe IP has PTM capability enabled (if supported) even in the EP mode. The PCIe compliance for the EP mode expects PTM capabilities (ROOT_CAPABLE, RES_CAPABLE, CLK_GRAN) be disabled. Hence disable PTM for the EP mode. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Jingoo Han <[email protected]>
2022-10-27PCI: dwc: Fix n_fts[] array overrunVidya Sagar1-1/+1
commit aeaa0bfe89654 ("PCI: dwc: Move N_FTS setup to common setup") incorrectly uses pci->link_gen in deriving the index to the n_fts[] array also introducing the issue of accessing beyond the boundaries of array for greater than Gen-2 speeds. This change fixes that issue. Link: https://lore.kernel.org/r/[email protected] Fixes: aeaa0bfe8965 ("PCI: dwc: Move N_FTS setup to common setup") Signed-off-by: Vidya Sagar <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Jingoo Han <[email protected]>
2022-10-17Revert "PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro"Jon Hunter1-3/+8
This reverts commit 8bb7ff12a91429eb76e093b517ae810b146448fe. Commit 8bb7ff12a914 ("PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro") updated the Tegra PCI driver to use the macro PCI_CONF1_EXT_ADDRESS() instead of a local function in the Tegra PCI driver. This broke PCI for some Tegra platforms because, when calculating the offset value, the mask applied to the lower 8-bits changed from 0xff to 0xfc. For now, fix this by reverting this commit. Fixes: 8bb7ff12a914 ("PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro") Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jon Hunter <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Thierry Reding <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]>
2022-10-17PCI: qcom-ep: Setup PHY to work in EP modeDmitry Baryshkov1-0/+5
Call phy_set_mode_ext() to notify the PHY driver that the PHY is being used in the EP mode. Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Jingoo Han <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-10-17PCI: qcom: Setup PHY to work in RC modeDmitry Baryshkov1-0/+5
Call phy_set_mode_ext() to notify the PHY driver that the PHY is being used in the RC mode. Reviewed-by: Jingoo Han <[email protected]> Reviewed-by: Johan Hovold <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2022-10-11Merge tag 'pci-v6.1-changes' of ↵Linus Torvalds13-186/+244
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull pci updates from Bjorn Helgaas: "Resource management: - Distribute spare resources to unconfigured hotplug bridges at boot-time (not just when hot-adding such a bridge), which makes hot-adding devices to docks work better. - Revert to a BAR assignment inherited from firmware only when the address is actually reachable via any upstream bridges, which fixes some cases where firmware doesn't configure all devices. - Add a sysfs interface to resize BARs so this can be done before assigning devices to a VM through VFIO. Power management: - Disable Precision Time Management for all devices on suspend to enable lower-power PM state. We previously did this just for Root Ports, which isn't enough because downstream devices can still generate PTM messages, which cause errors if it's disabled in the Root Port. - Save and restore the ASPM L1 PM Substates configuration for suspend/ resume. Previously this configuration was lost, so L1.x states likely stopped working after resume. - Check whether the L1 PM Substates Capability exists. If it didn't exist, we previously read junk and tried to configure L1 Substates based on that. - Fix the LTR_L1.2_THRESHOLD computation, which previously set a threshold for entering L1.2 that was too low in some cases. - Reduce the delay after transitions to or from D3cold by using usleep_range() rather than msleep(), which often slept for ~19ms instead of the 10ms normally required. The spec says 10ms is enough, but it's possible we could trip over devices that need a little more. Error handling: - Work around a BIOS bug that caused Intel Root Ports to advertise a Root Port Programmed I/O (RP PIO) log size of zero, which caused annoying warnings and prevented the kernel from dumping log registers for DPC errors. Qualcomm PCIe controller driver: - Add support for SC8280XP and SA8540P host controllers and SM8450 endpoint controller. - Disable Master AXI clock on endpoint controllers to save power when link is idle or in L1.x. - Expose link state transition counts via debugfs to help debug issues with low-power states. - Add auto-loading module support. Synopsys DesignWare PCIe controller driver: - Remove a dependency on ZONE_DMA32 by allocating the MSI target page differently. There's more work to do related to eDMA controllers, so it's not completely settled" * tag 'pci-v6.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (71 commits) PCI: qcom-ep: Check platform_get_resource_byname() return value PCI: qcom-ep: Add support for SM8450 SoC dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC dt-bindings: PCI: qcom-ep: Define clocks per platform PCI: qcom-ep: Make PERST separation optional dt-bindings: PCI: qcom-ep: Make PERST separation optional PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe traffic PCI: Expose PCIe Resizable BAR support via sysfs PCI/ASPM: Correct LTR_L1.2_THRESHOLD computation PCI/ASPM: Ignore L1 PM Substates if device lacks capability PCI/ASPM: Factor out L1 PM Substates configuration PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS PCI: qcom-ep: Expose link transition counts via debugfs PCI: qcom-ep: Disable IRQs during driver remove PCI/ASPM: Save L1 PM Substates Capability for suspend/resume PCI/ASPM: Refactor L1 PM Substates Control Register programming PCI: qcom-ep: Make use of the cached dev pointer PCI: qcom-ep: Rely on the clocks supplied by devicetree PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on() ...
2022-10-05Merge branch 'remotes/lorenzo/pci/misc'Bjorn Helgaas3-36/+13
- Add macros for PCI Configuration Mechanism #1 and use them in the ftpci100, mt7621, and tegra drivers (Pali Rohár) * remotes/lorenzo/pci/misc: PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macro PCI: mt7621: Use PCI_CONF1_EXT_ADDRESS() macro PCI: ftpci100: Use PCI_CONF1_ADDRESS() macro PCI: Add standard PCI Config Address macros
2022-10-05Merge branch 'pci/qcom'Bjorn Helgaas2-112/+180
- List platforms that use a single MSI host interrupt in qcom DT (Johan Hovold) - Add SC8280XP, SA8540P support to qcom DT binding and driver(Johan Hovold) - Make all optional clocks truly optional in the driver (Johan Hovold) - Rename per-IP structs to reflect the IP version (Johan Hovold) - Sort device ID match table by compatible string (Johan Hovold) - Add MODULE_DEVICE_TABLE to enable module autoloading (Dmitry Baryshkov) - Drop the unused .post_deinit() callback (Johan Hovold) - Rely on DT for clock information instead of hard-coding it in the driver (Manivannan Sadhasivam) - Disable IRQs when removing driver to avoid spurious IRQs later (Manivannan Sadhasivam) - Expose link transition counts via debugfs to help debug issues with low-power states (Manivannan Sadhasivam) - Gate Master AXI clock to the MHI bus while in L1 substates to save power (Manivannan Sadhasivam) - Disable Master AXI clock to save power when there is no traffic on PCIe (Manivannan Sadhasivam) - Make the "PERST separation" debug feature optional in the DT and the driver (Manivannan Sadhasivam) - Define clocks to be per-platform in DT to prepare for future SoCs (Manivannan Sadhasivam) - Add SM8450 SoC support (Manivannan Sadhasivam) - Check for platform_get_resource_byname() to avoid a NULL pointer dereference (Yang Yingliang) * pci/qcom: PCI: qcom-ep: Check platform_get_resource_byname() return value PCI: qcom-ep: Add support for SM8450 SoC dt-bindings: PCI: qcom-ep: Add support for SM8450 SoC dt-bindings: PCI: qcom-ep: Define clocks per platform PCI: qcom-ep: Make PERST separation optional dt-bindings: PCI: qcom-ep: Make PERST separation optional PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe traffic PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SS PCI: qcom-ep: Expose link transition counts via debugfs PCI: qcom-ep: Disable IRQs during driver remove PCI: qcom-ep: Make use of the cached dev pointer PCI: qcom-ep: Rely on the clocks supplied by devicetree PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structure PCI: qcom: Rename host-init error label PCI: qcom: Drop unused post_deinit callback PCI: qcom-ep: Add MODULE_DEVICE_TABLE PCI: qcom: Sort device-id table PCI: qcom: Clean up IP configurations PCI: qcom: Make all optional clocks optional PCI: qcom: Add support for SA8540P PCI: qcom: Add support for SC8280XP dt-bindings: PCI: qcom: Add SA8540P to binding dt-bindings: PCI: qcom: Add SC8280XP to binding dt-bindings: PCI: qcom: Enumerate platforms with single msi interrupt
2022-10-05Merge branch 'remotes/lorenzo/pci/mvebu'Bjorn Helgaas1-6/+6
- Fix endianness of emulated bridge iolimitupper, iobaseupper, memlimit and membase members (Pali Rohár) * remotes/lorenzo/pci/mvebu: PCI: mvebu: Fix endianness when accessing PCI emul bridge members
2022-10-05Merge branch 'remotes/lorenzo/pci/mediatek'Bjorn Helgaas1-1/+1
- Rename the pcie-mediatek-gen3 driver from 'mtk-pcie' to 'mtk-pcie-gen3' so it can coexist with the pcie-mediatek driver, which also uses 'mtk-pcie' (Felix Fietkau) * remotes/lorenzo/pci/mediatek: PCI: mediatek-gen3: Change driver name to mtk-pcie-gen3
2022-10-05Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas4-29/+37
- Use dmam_alloc_coherent() instead of dma_map_page() to allocate the MSI target page, which means dwc drivers will work even when ZONE_DMA32 is disabled (Will McVicker) - If we can't allocate an MSI target page with a 32-bit address, try allocating one with a 64-bit address (Will McVicker) - Switch from of_gpio_named_count() to generic gpiod_count() (Andy Shevchenko) - Add support for i.MX8MP PCIe (Richard Zhu) - Fix the Freescale i.MX8 PHY driver, which had interchanged the phy_init() and phy_power_on() interfaces (Richard Zhu) * remotes/lorenzo/pci/dwc: phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on() PCI: imx6: Add i.MX8MP PCIe support PCI: dwc: Replace of_gpio_named_count() by gpiod_count() PCI: dwc: Drop dependency on ZONE_DMA32
2022-10-05Merge branch 'remotes/lorenzo/pci/bridge-emul'Bjorn Helgaas2-0/+2
- In an emulated PCI bridge, set Capability offsets so they match the hardware offsets shown by U-Boot (Pali Rohár) * remotes/lorenzo/pci/bridge-emul: PCI: pci-bridge-emul: Set position of PCI capabilities to real HW value
2022-10-05Merge branch 'remotes/lorenzo/pci/apple'Bjorn Helgaas1-2/+2
- Switch from gpiod_get_from_of_node() to generic devm GPIO API (Dmitry Torokhov) * remotes/lorenzo/pci/apple: PCI: apple: Do not leak reset GPIO on unbind/unload/error
2022-10-05PCI: qcom-ep: Check platform_get_resource_byname() return valueYang Yingliang1-0/+5
If platform_get_resource_byname() fails, 'mmio_res' will be set to NULL pointer, which causes a NULL pointer dereference when it is used in qcom_pcie_perst_deassert(). Check the return value to prevent it. Link: https://lore.kernel.org/r/[email protected] Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver") Signed-off-by: Yang Yingliang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Andrew Halaney <[email protected]>
2022-10-05PCI: qcom-ep: Add support for SM8450 SoCManivannan Sadhasivam1-0/+1
Add support for SM8450 SoC to the Qualcomm PCIe Endpoint Controller driver. The driver uses the same config as the existing SDX55 chipset, so additional settings are not required. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-10-05PCI: qcom-ep: Make PERST separation optionalManivannan Sadhasivam1-4/+6
PERST separation is an optional debug feature used to collect the crash dump from the PCIe endpoint devices by the PCIe host when the endpoint crashes. This feature keeps the PCIe link up by separating the PCIe IP block from the SoC reset logic. Make the property optional in the driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-10-05PCI: qcom-ep: Disable Master AXI Clock when there is no PCIe trafficManivannan Sadhasivam1-1/+8
The Master AXI clock can be disabled when it is not used i.e., when there is no traffic on the PCIe bus. This helps to save power during idle state. [bhelgaas: tidy and wrap comment] Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2022-10-05PCI: qcom-ep: Gate Master AXI clock to MHI bus during L1SSManivannan Sadhasivam1-0/+9
During L1SS, gate the Master clock supplied to the MHI bus to save power. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-10-05PCI: qcom-ep: Expose link transition counts via debugfsManivannan Sadhasivam1-0/+60
Qualcomm PCIe controllers have debug registers in the MMIO region that count PCIe link transitions. Expose them over debugfs to userspace to help debug the low power issues. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-10-05PCI: qcom-ep: Disable IRQs during driver removeManivannan Sadhasivam1-6/+9
Disable the Global and PERST IRQs during driver remove to avoid getting spurious IRQs after resource deallocation. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-10-03PCI: qcom-ep: Make use of the cached dev pointerManivannan Sadhasivam1-2/+2
In the qcom_pcie_ep_get_resources() function, dev pointer is already cached in a local variable. So let's make use of it instead of getting the dev pointer again from pdev struct. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-10-03PCI: qcom-ep: Rely on the clocks supplied by devicetreeManivannan Sadhasivam1-20/+13
Generally, device drivers should just rely on the platform data like devicetree to supply the clocks required for the functioning of the peripheral. There is no need to hardcode the clk info in the driver. So get rid of the static clk info and obtain the platform supplied clks. The total number of clocks supplied is obtained using the devm_clk_bulk_get_all() API and used for the rest of the clk_bulk_ APIs. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-10-03PCI: qcom-ep: Add kernel-doc for qcom_pcie_ep structureManivannan Sadhasivam1-0/+17
Add kernel-doc for qcom_pcie_ep structure. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-10-03phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on()Richard Zhu1-3/+3
Refer to phy_core driver, phy_init() must be called before phy_power_on(). Fix the wrong order of phy_init() and phy_power_on() here. Link: https://lore.kernel.org/r/[email protected] Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Tested-by: Alexander Stein <[email protected]> Signed-off-by: Richard Zhu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Vinod Koul <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]>
2022-10-03PCI: imx6: Add i.MX8MP PCIe supportRichard Zhu1-2/+25
Add i.MX8MP PCIe support. To avoid codes duplication when find the syscon regmap, add the iomux gpr syscon compatible into drvdata. Link: https://lore.kernel.org/r/[email protected] Tested-by: Marek Vasut <[email protected]> Tested-by: Richard Leitner <[email protected]> Tested-by: Alexander Stein <[email protected]> Signed-off-by: Richard Zhu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
2022-10-03PCI: dwc: Replace of_gpio_named_count() by gpiod_count()Andy Shevchenko1-2/+2
As a preparation to unexport of_gpio_named_count(), convert the driver to use gpiod_count() instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Rob Herring <[email protected]>
2022-09-29PCI: tegra: Use PCI_CONF1_EXT_ADDRESS() macroPali Rohár1-8/+3
Simplify pci-tegra.c driver code and use new PCI_CONF1_EXT_ADDRESS() macro for accessing PCI config space. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Thierry Reding <[email protected]>
2022-09-29PCI: qcom: Rename host-init error labelJohan Hovold1-2/+2
Use a more descriptive name for the reset host-init error label for consistency. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-09-29PCI: qcom: Drop unused post_deinit callbackJohan Hovold1-3/+0
Drop the unused and confusingly named post_deinit callback that was added for the now removed pipe clock handling. If ever needed we can add back a callback named pre_deinit (or perhaps rather pre_phy_power_off) instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-09-27PCI: mt7621: Use PCI_CONF1_EXT_ADDRESS() macroPali Rohár1-11/+6
Simplify pcie-mt7621.c driver code and use new PCI_CONF1_EXT_ADDRESS() macro for accessing PCIe config space. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Sergio Paracuellos <[email protected]>
2022-09-27PCI: ftpci100: Use PCI_CONF1_ADDRESS() macroPali Rohár1-17/+4
Simplify pci-ftpci100.c driver code and use new PCI_CONF1_ADDRESS() macro for accessing PCI config space. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-09-16PCI: aardvark: Add support for PCI Bridge Subsystem Vendor ID on emulated bridgePali Rohár1-0/+3
Register with Subsystem Device/Vendor ID is at offset 0x2c. Export it via the emulated bridge to enable support for the Subsystem Device/Vendor ID - by reading it in the PCI controller config space and storing it in the emulated bridge control structures, so that it is exposed in the respective PCI capability. After this change Subsystem ID is visible in lspci output at line: Capabilities: [40] Subsystem Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-09-14PCI: apple: Do not leak reset GPIO on unbind/unload/errorDmitry Torokhov1-2/+2
The driver allocates reset GPIO in apple_pcie_setup_port() but neither releases the resource, nor uses devm API to have it released automatically. Let's fix this by switching to devm API. While at it let's use generic devm_fwnode_gpiod_get() instead of OF-specific gpiod_get_from_of_node() - this will allow us top stop exporting the latter down the road. Link: https://lore.kernel.org/r/[email protected] Fixes: 1e33888fbe44 ("PCI: apple: Add initial hardware bring-up") Signed-off-by: Dmitry Torokhov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Hector Martin <[email protected]> Acked-by: Marc Zyngier <[email protected]>
2022-08-30PCI: qcom-ep: Add MODULE_DEVICE_TABLEDmitry Baryshkov1-0/+1
Add MODULE_DEVICE_TABLE to enable module autoloading for respective device. Link: https://lore.kernel.org/r/[email protected] Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver") Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-08-29PCI: dwc: Drop dependency on ZONE_DMA32Will McVicker2-22/+7
Re-work the msi_msg DMA allocation logic to use dmam_alloc_coherent() which uses the coherent DMA mask to try to return an allocation within the DMA mask limits. With that, we now can drop the msi_page parameter in struct dw_pcie_rp. This allows kernel configurations that disable ZONE_DMA32 to continue supporting a 32-bit DMA mask. Without this patch, the PCIe host device will fail to probe when ZONE_DMA32 is disabled. Link: https://lore.kernel.org/r/[email protected] Fixes: 35797e672ff0 ("PCI: dwc: Fix MSI msi_msg DMA mapping") Reported-by: Isaac J. Manjarres <[email protected]> Signed-off-by: Will McVicker <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Jingoo Han <[email protected]>
2022-08-25PCI: pci-bridge-emul: Set position of PCI capabilities to real HW valuePali Rohár2-0/+2
mvebu and aardvark HW have PCIe capabilities on different offset in PCI config space. Extend pci-bridge-emul.c code to allow setting custom driver custom value where PCIe capabilities starts. With this change PCIe capabilities of both drivers are reported at the same location as where they are reported by U-Boot - in their real HW offset. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-08-23PCI: mediatek-gen3: Change driver name to mtk-pcie-gen3Felix Fietkau1-1/+1
driver_register() will refuse to register another driver with the same name. This change allows pcie-mediatek-gen3 to coexist with pcie-mediatek built into the kernel. Link: https://lore.kernel.org/r/[email protected] Fixes: d3bf75b579b9 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192") Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Jianjun Wang <[email protected]>
2022-08-23PCI: mvebu: Fix endianness when accessing PCI emul bridge membersPali Rohár1-6/+6
PCI emul bridge members iolimitupper, iobaseupper, memlimit and membase are of type __le16, so correctly access these members using le16_to_cpu() macros. Link: https://lore.kernel.org/r/[email protected] Fixes: e7a01876729c ("PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers") Reported-by: kernel test robot <[email protected]> Signed-off-by: Pali Rohár <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2022-08-23PCI: qcom: Sort device-id tableJohan Hovold1-7/+7
Sort the device-id table entries alphabetically by compatible string to make it easier to find entries and add new ones. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Brian Masney <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2022-08-23PCI: qcom: Clean up IP configurationsJohan Hovold1-60/+29
The various IP versions have different configurations that are encoded in separate sets of operation callbacks. Currently, there is no need for also maintaining corresponding sets of data parameters, but it is conceivable that these may again be found useful (e.g. to implement minor variations of the operation callbacks). Rename the default configuration structures after the IP version they apply to so that they can more easily be reused by different SoCs. Note that SoC specific configurations can be added later if need arises (e.g. cfg_sc8280xp). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Brian Masney <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2022-08-23PCI: qcom: Make all optional clocks optionalJohan Hovold1-24/+4
The kernel is not a devicetree validator and does not need to re-encode information which is already available in the devicetree. This is specifically true for the optional PCIe clocks, some of which are really interconnect clocks. Treat also the 2.7.0 optional clocks as truly optional instead of maintaining a list of clocks per compatible (including two compatible strings for the two identical controllers on sm8450) just to validate the devicetree. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Brian Masney <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2022-08-23PCI: qcom: Add support for SA8540PJohan Hovold1-0/+6
The SA8540P platform has five PCIe controllers: two 4-lane, two 2-lane and one 1-lane. Add a new "qcom,pcie-sa8540p" compatible string and reuse the 1.9.0 ops. Note that like for SC8280XP, the SA8540P controllers need two or three interconnect clocks to be enabled. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Brian Masney <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2022-08-23PCI: qcom: Add support for SC8280XPJohan Hovold1-2/+20
The SC8280XP platform has seven PCIe controllers: two used with USB4, two 4-lane, two 2-lane and one 1-lane. Add a new "qcom,pcie-sc8280xp" compatible string and reuse the 1.9.0 ops. Note that the SC8280XP controllers need two or three interconnect clocks to be enabled. Model these as optional clocks to avoid encoding devicetree data in the PCIe driver. Note that the same could be done for the SM8450 interconnect clocks and possibly also for the TBU clocks. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Johan Hovold <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2022-08-15arm64: bcmbca: Make BCM4908 drivers depend on ARCH_BCMBCAWilliam Zhang1-1/+1
With Broadcom Broadband arch ARCH_BCMBCA supported in the kernel, this patch series migrate the ARCH_BCM4908 symbol to ARCH_BCMBCA. Hence replace ARCH_BCM4908 with ARCH_BCMBCA in subsystem Kconfig files. Signed-off-by: William Zhang <[email protected]> Acked-by: Guenter Roeck <[email protected]> (for watchdog) Acked-by: Bjorn Helgaas <[email protected]> (for drivers/pci) Acked-by: Wolfram Sang <[email protected]> (for i2c) Acked-by: Philipp Zabel <[email protected]> (for reset) Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Florian Fainelli <[email protected]>
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