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Extend devm_of_pci_get_host_bridge_resources() and
pci_parse_request_of_pci_ranges() helpers to also parse the inbound
addresses from DT 'dma-ranges' and populate a resource list with the
translated addresses. This will help ensure 'dma-ranges' is always
parsed in a consistent way.
Tested-by: Srinath Mannam <[email protected]>
Tested-by: Thomas Petazzoni <[email protected]> # for AArdvark
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Srinath Mannam <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Toan Le <[email protected]>
Cc: Ley Foon Tan <[email protected]>
Cc: Tom Joseph <[email protected]>
Cc: Ray Jui <[email protected]>
Cc: Scott Branden <[email protected]>
Cc: [email protected]
Cc: Ryder Lee <[email protected]>
Cc: Karthikeyan Mitran <[email protected]>
Cc: Hou Zhiqiang <[email protected]>
Cc: Simon Horman <[email protected]>
Cc: Shawn Lin <[email protected]>
Cc: Heiko Stuebner <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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Convert altera host bridge to use the common
pci_parse_request_of_pci_ranges().
There's no need to assign the resources to a temporary list first. Just
use bridge->windows directly and remove all the temporary list handling.
If an I/O range is present, then it will now be mapped. It's expected
that h/w which doesn't support I/O range will not define one.
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Cc: Ley Foon Tan <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: [email protected]
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Stratix 10 PCIe controller does not support Type 1 to Type 0 conversion
as previous version (V1) does so the PCIe controller configuration
mechanism needs to send Type 0 config TLP if the target bus number
matches with the secondary bus number.
Implement a function to form a TLP header that depends on the PCIe
controller version, so that the header can be formed according to
specific host controller HW internals, fixing the type conversion issue.
Signed-off-by: Ley Foon Tan <[email protected]>
[[email protected]: commit log]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Altera PCIe Rootport IP is a soft IP and is only available after
an FPGA image (whose design contains it) is programmed.
Make driver modulable to support use cases when FPGA image is
programmed after the kernel has booted, so that the driver
can be loaded upon request.
Signed-off-by: Ley Foon Tan <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Add PCIe Root Port support for Stratix 10 device.
Main differences compared to the PCIe Root Port IP on Cyclone V
and Arria 10 devices:
- HIP interface to access Root Port configuration register
- TLP programming flow:
- One REG0 register
- Don't need to check alignment
Signed-off-by: Ley Foon Tan <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Native PCI drivers for root complex devices were originally all in
drivers/pci/host/. Some of these devices can also be operated in endpoint
mode. Drivers for endpoint mode didn't seem to fit in the "host"
directory, so we put both the root complex and endpoint drivers in
per-device directories, e.g., drivers/pci/dwc/, drivers/pci/cadence/, etc.
These per-device directories contain trivial Kconfig and Makefiles and
clutter drivers/pci/. Make a new drivers/pci/controllers/ directory and
collect all the device-specific drivers there.
No functional change intended.
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Shawn Lin <[email protected]>
[bhelgaas: changelog]
Signed-off-by: Bjorn Helgaas <[email protected]>
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