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2020-11-04PCI: dwc: Restore ATU memory resource setup to use last entryRob Herring1-2/+6
Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources"), the DWC driver was setting up the last memory resource rather than the first memory resource. This doesn't matter for most platforms which only have 1 memory resource, but it broke Tegra194 which has a 2nd (prefetchable) memory region that requires an ATU entry. The first region on Tegra194 relies on the default 1:1 pass-thru of outbound transactions and doesn't need an ATU entry. Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources") Link: https://lore.kernel.org/r/[email protected] Reported-by: Vidya Sagar <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]> Acked-by: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]>
2020-10-21Merge branch 'remotes/lorenzo/pci/tegra'Bjorn Helgaas1-15/+5
- Drop return value checking for debugfs_create() calls (Greg Kroah-Hartman) - Convert debugfs "ports" file to use DEFINE_SEQ_ATTRIBUTE() (Liu Shixin) * remotes/lorenzo/pci/tegra: PCI: tegra: Convert to use DEFINE_SEQ_ATTRIBUTE macro PCI: tegra: No need to check return value of debugfs_create() functions
2020-10-21Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas1-0/+13
- Make sure PCIe is reset before init to work around QSDK U-Boot issue (Ansuel Smith) - Set iproc affinity mask on MSI interrupts (Mark Tomlinson) * remotes/lorenzo/pci/qcom: PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0
2020-10-21Merge branch 'remotes/lorenzo/pci/meson'Bjorn Helgaas2-2/+9
- Add pci-meson module support and enable by default on ARCH_MESON (Kevin Hilman) * remotes/lorenzo/pci/meson: PCI: meson: Build as module by default
2020-10-21Merge branch 'remotes/lorenzo/pci/kirin'Bjorn Helgaas1-1/+5
- Return -EPROBE_DEFER in case the gpio isn't ready (Bean Huo) * remotes/lorenzo/pci/kirin: PCI: kirin: Return -EPROBE_DEFER in case the gpio isn't ready
2020-10-21Merge branch 'remotes/lorenzo/pci/imx6'Bjorn Helgaas1-23/+18
- Use "fallthrough" pseudo-keyword (Gustavo A. R. Silva) - Drop redundant error messages after devm_clk_get() (Anson Huang) * remotes/lorenzo/pci/imx6: PCI: imx6: Do not output error message when devm_clk_get() failed with -EPROBE_DEFER PCI: imx6: Use fallthrough pseudo-keyword
2020-10-20PCI: dwc: Add link up check in dw_child_pcie_ops.map_bus()Hou Zhiqiang1-0/+11
NXP Layerscape (ls1028a, ls2088a), dra7xxx and imx6 platforms are either programmed or statically configured to forward the error triggered by a link-down state (eg no connected endpoint device) on the system bus for PCI configuration transactions; these errors are reported as an SError at system level, which is fatal. Enumerating a PCI tree when the PCIe link is down is not sensible either, so even if the link-up check is racy (link can go down after map_bus() is called) add a link-up check in map_bus() to prevent issuing configuration transactions when the link is down. SError report: SError Interrupt on CPU2, code 0xbf000002 -- SError CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67 Hardware name: LS1046A RDB Board (DT) pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--) pc : pci_generic_config_read+0x3c/0xe0 lr : pci_generic_config_read+0x24/0xe0 sp : ffff80001003b7b0 x29: ffff80001003b7b0 x28: ffff80001003ba74 x27: ffff000971d96800 x26: ffff00096e77e0a8 x25: ffff80001003b874 x24: ffff80001003b924 x23: 0000000000000004 x22: 0000000000000000 x21: 0000000000000000 x20: ffff80001003b874 x19: 0000000000000004 x18: ffffffffffffffff x17: 00000000000000c0 x16: fffffe0025981840 x15: ffffb94c75b69948 x14: 62203a383634203a x13: 666e6f635f726568 x12: 202c31203d207265 x11: 626d756e3e2d7375 x10: 656877202c307830 x9 : 203d206e66766564 x8 : 0000000000000908 x7 : 0000000000000908 x6 : ffff800010900000 x5 : ffff00096e77e080 x4 : 0000000000000000 x3 : 0000000000000003 x2 : 84fa3440ff7e7000 x1 : 0000000000000000 x0 : ffff800010034000 Kernel panic - not syncing: Asynchronous SError Interrupt CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67 Hardware name: LS1046A RDB Board (DT) Call trace: dump_backtrace+0x0/0x1c0 show_stack+0x18/0x28 dump_stack+0xd8/0x134 panic+0x180/0x398 add_taint+0x0/0xb0 arm64_serror_panic+0x78/0x88 do_serror+0x68/0x180 el1_error+0x84/0x100 pci_generic_config_read+0x3c/0xe0 dw_pcie_rd_other_conf+0x78/0x110 pci_bus_read_config_dword+0x88/0xe8 pci_bus_generic_read_dev_vendor_id+0x30/0x1b0 pci_bus_read_dev_vendor_id+0x4c/0x78 pci_scan_single_device+0x80/0x100 Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Hou Zhiqiang <[email protected]> [[email protected]: rewrote the commit log, remove Fixes tag] Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-10-13PCI: dwc: Fix MSI page leakage in suspend/resumeJisheng Zhang3-17/+36
Currently, dw_pcie_msi_init() allocates and maps page for msi, then program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex may lose power during suspend-to-RAM, so when we resume, we want to redo the latter but not the former. If designware based driver (for example, pcie-tegra194.c) calls dw_pcie_msi_init() in resume path, the msi page will be leaked. As pointed out by Rob and Ard, there's no need to allocate a page for the MSI address, we could use an address in the driver data. To avoid map the MSI msg again during resume, we move the map MSI msg from dw_pcie_msi_init() to dw_pcie_host_init(). Suggested-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jisheng Zhang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-10-13PCI: dwc: Skip PCIE_MSI_INTR0* programming if MSI is disabledJisheng Zhang1-1/+1
If MSI is disabled, there's no need to program PCIE_MSI_INTR0_MASK and PCIE_MSI_INTR0_ENABLE registers. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jisheng Zhang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
2020-10-13PCI: keystone: Remove iATU register mappingKunihiko Hayashi1-16/+4
After applying "PCI: dwc: Add common iATU register support", there is no need to set own iATU in the Keystone driver itself. Suggested-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]>
2020-10-13PCI: dwc: Add common iATU register supportKunihiko Hayashi1-0/+5
This gets iATU register area from reg property that has reg-names "atu". In Synopsys DWC version 4.80 or later, since iATU register area is separated from core register area, this area is necessary to get from DT independently. Suggested-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]>
2020-10-05PCI: meson: Build as module by defaultKevin Hilman2-2/+9
Enable pci-meson to build as a module whenever ARCH_MESON is enabled. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Kevin Hilman <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Cc: Yue Wang <[email protected]>
2020-09-28PCI: kirin: Return -EPROBE_DEFER in case the gpio isn't readyBean Huo1-1/+5
PCI host bridge driver can be probed before the gpiochip it requires, so, of_get_named_gpio() can return -EPROBE_DEFER. Current code lets the kirin_pcie_probe() directly return -ENODEV, which results in the PCI host controller driver probe failure; with this error code the PCI host controller driver will not be probed again when the gpiochip driver is loaded. Fix the above issue by letting kirin_pcie_probe() return -EPROBE_DEFER in such a case. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bean Huo <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-09-28PCI: dwc: Fix 'cast truncates bits from constant value'Gustavo Pimentel1-1/+1
Fixes warning given by executing "make C=2 drivers/pci/" Sparse output: CHECK drivers/pci/controller/dwc/pcie-designware.c drivers/pci/controller/dwc/pcie-designware.c:432:52: warning: cast truncates bits from constant value (ffffffff7fffffff becomes 7fffffff) Link: https://lore.kernel.org/r/7ea7f7d342f97c758949a17b870012f52ce5b3f5.1600767645.git.gustavo.pimentel@synopsys.com Reported-by: Bjorn Helgaas <[email protected]> Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Joao Pinto <[email protected]>
2020-09-21PCI: layerscape: Add EP mode support for ls1088a and ls2088aXiaowei Bao1-19/+53
Add PCIe EP mode support for ls1088a and ls2088a, there are some difference between LS1 and LS2 platform, so refactor the code of the EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-09-21PCI: layerscape: Modify the MSIX to the doorbell modeXiaowei Bao1-1/+2
dw_pcie_ep_raise_msix_irq was never called in the exisitng driver before, because the ls1046a platform don't support the MSIX feature and msix_capable was always set to false. Now that add the ls1088a platform with MSIX support, use the doorbell method to support the MSIX feature. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2020-09-21PCI: layerscape: Modify the way of getting capability with different PEXXiaowei Bao1-8/+23
The different PCIe controller in one board may be have different capability of MSI or MSIX, so change the way of getting the MSI capability, make it more flexible. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-09-21PCI: layerscape: Fix some format issue of the codeXiaowei Bao1-2/+2
Fix some format issue of the code in EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2020-09-21PCI: designware-ep: Modify MSI and MSIX CAP way of findingXiaowei Bao2-21/+118
Each PF of EP device should have its own MSI or MSIX capabitily struct, so create a dw_pcie_ep_func struct and move the msi_cap and msix_cap to this struct from dw_pcie_ep, and manage the PFs via a list. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-09-21PCI: designware-ep: Move the function of getting MSI capability forwardXiaowei Bao1-4/+4
Move the function of getting MSI capability to the front of init function, because the init function of the EP platform driver will use the return value by the function of getting MSI capability. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2020-09-21PCI: designware-ep: Add the doorbell mode of MSI-X in EP modeXiaowei Bao2-0/+31
Add the doorbell mode of MSI-X in DWC EP driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2020-09-21PCI: designware-ep: Add multiple PFs support for DWCXiaowei Bao3-59/+143
Add multiple PFs support for DWC, due to different PF have different config space, we use func_conf_select callback function to access the different PF's config space, the different chip company need to implement this callback function when use the DWC IP core and intend to support multiple PFs feature. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Hou Zhiqiang <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Gustavo Pimentel <[email protected]>
2020-09-10PCI: dwc: Use DBI accessorsRob Herring2-10/+8
Convert the remaining cases of register accesses using dbi_base rather than dw_pcie_(read|write)[bwl]_dbi accessors. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Pratyush Anand <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected]
2020-09-10PCI: dwc: Move N_FTS setup to common setupRob Herring5-85/+35
The Designware controller has common registers to set number of fast training sequence ordered sets. The Artpec6, Intel, and Tegra driver initialize these register fields. Let's move the initialization to the common setup code and drivers just have to provide the value. There's a slight change in that the common clock mode N_FTS field is now initialized. Previously only the Intel driver set this. It's not clear from the code if common clock mode is used in the Artpec6 or Tegra driver. It depends on the DWC configuration. Given the field is not initialized while the others are, it seems unlikely common clock mode is used. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jesper Nilsson <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected]
2020-09-10PCI: dwc/intel-gw: Drop unused max_widthRob Herring1-4/+0
'max_width' is read, but never used, so let's remove it. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Dilip Kota <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-10PCI: dwc/intel-gw: Move getting PCI_CAP_ID_EXP offset to intel_pcie_link_setup()Rob Herring1-14/+1
The PCI_CAP_ID_EXP offset is only needed by intel_pcie_link_setup(), so let's retrieve it there and avoid storing the offset. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Dilip Kota <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-10PCI: dwc/intel-gw: Drop unnecessary checking of DT 'device_type' propertyRob Herring1-6/+0
A driver doesn't need to check for DT 'device_type' property, so let's remove the check. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Dilip Kota <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-10PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup codeRob Herring2-4/+1
The Intel driver is the only one to set PORT_LINK_DLL_LINK_EN. The default value is set and it seems pretty certain that enabling link initialization is always required. Maybe it could just be dropped from the Intel driver, but lets move setting it into the common code to be sure. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Dilip Kota <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-10PCI: dwc: Centralize link gen settingRob Herring11-151/+40
keystone would force gen2 if no DT property. Now it relies on the PCI_EXP_LNKCAP value. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Richard Zhu <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Stanimir Varbanov <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Pratyush Anand <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2020-09-08PCI: dwc: Make ATU accessors privateRob Herring2-18/+6
The ATU registers are only accessed in pcie-designware.c and can be private to it. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-08PCI: dwc: Remove read_dbi2 codeRob Herring3-36/+0
The DBI2 appears to be write-only and there's no read accesses in the code anyways, so let's remove all the read_dbi2 related code. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]>
2020-09-08PCI: dwc/tegra: Use common Designware port logic register definitionsRob Herring2-34/+28
The Tegra driver has its own defines for common Designware Port Logic registers. Convert it to use the standard register definitions. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected]
2020-09-08PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offsetRob Herring3-12/+7
While the Designware controller appears to hard code the PCI_CAP_ID_EXP capability register at 0x70, there's no need to hard code this in the driver as it is discoverable. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Pratyush Anand <[email protected]> Cc: [email protected]
2020-09-08PCI: dwc/qcom: Use common PCI register definitionsRob Herring1-10/+8
The QCom driver has its own defines for common PCI config space registers. It also hard codes the capability register offsets which are discoverable. Convert it to use the standard register definitions. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Stanimir Varbanov <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: [email protected]
2020-09-08PCI: dwc/imx6: Use common PCI register definitionsRob Herring1-23/+14
The i.MX6 driver has its own defines for common PCI config space registers. It also hard codes the capability register offsets which are discoverable. Convert it to use the standard register definitions. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Richard Zhu <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: NXP Linux Team <[email protected]>
2020-09-08PCI: dwc/meson: Rework PCI config and DW port logic register accessesRob Herring1-51/+25
The meson 'elbi' registers are just the Designware 'dbi' space and all the registers accessed are either standard PCI config space or DWC port logic registers. Convert the accesses to use the common defines and register accessors. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Yue Wang <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Kevin Hilman <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: [email protected]
2020-09-08PCI: dwc/meson: Drop unnecessary RC config space initializationRob Herring1-20/+0
The common Designware init already initializes the RC PCI_COMMAND, BAR0 and BAR1 registers. The only difference here is the common code sets SERR. If clearing SERR is what's desired, then the Meson driver should do that instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Yue Wang <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Kevin Hilman <[email protected]> Cc: [email protected]
2020-09-08PCI: dwc/meson: Drop the duplicate number of lanes setupRob Herring1-28/+1
The meson lanes initialization is the same DWC port logic registers as in dw_pcie_setup(). We just need to initialize 'num_lanes' to 1 to do the same init. dw_pcie_setup_rc() sets the PORT_LOGIC_SPEED_CHANGE bit, so setting it can be dropped. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Yue Wang <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Kevin Hilman <[email protected]> Cc: Neil Armstrong <[email protected]> Cc: Jerome Brunet <[email protected]> Cc: Martin Blumenstingl <[email protected]> Cc: [email protected]
2020-09-08PCI: dwc: Ensure FAST_LINK_MODE is clearedRob Herring2-1/+5
"Fast Link Mode" is a simulation environment speed up setting which should never be set and the default is not set. However some Amlogic platforms have it set (by firmware presumably). See commit 87dccf09323f ("PCI: amlogic: meson: Don't use FAST_LINK_MODE to set up link") for more information. Let's clear it in core DWC code so we can drop some vendor specific code. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-08PCI: dwc: Add a 'num_lanes' field to struct dw_pcieRob Herring2-8/+7
Add a 'num_lanes' field to allow drivers to provide a the number of lanes if not in DT or using a custom DT property. A driver can provide a non-zero value which is used if the DT doesn't have a 'num-lanes' property. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-08PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROLRob Herring1-2/+0
PCIE_LINK_WIDTH_SPEED_CONTROL is already defined in pcie-designware.h, so remove it from the i.MX6 driver. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Richard Zhu <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: NXP Linux Team <[email protected]>
2020-09-08PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()Rob Herring9-34/+11
Move the IS_ENABLED(CONFIG_PCI_MSI) check into dw_pcie_msi_init() instead of duplicating it in all the drivers. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Richard Zhu <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: Yue Wang <[email protected]> Cc: Kevin Hilman <[email protected]> Cc: Jesper Nilsson <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Xiaowei Song <[email protected]> Cc: Binghui Wang <[email protected]> Cc: Stanimir Varbanov <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Kunihiko Hayashi <[email protected]> Cc: Masahiro Yamada <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2020-09-08PCI: dwc/keystone: Drop duplicated 'num-viewport'Rob Herring1-10/+1
The DWC core driver already parses and stores the 'num-viewport' DT property, so there is no need for the Keystone driver to store it. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-08PCI: dwc: Simplify config space handlingRob Herring3-55/+20
The config space is divided in half for type 0 and type 1 accesses, but this is pointless as there's only one iATU window which is reconfigured on each access. The only platform doing something custom is TI Keystone (surprise!). It does its own mapping of the config space to avoid spliting the config space and never actually uses va_cfg1_base as it has its own config space accessors. With the splitting removed, Keystone can use the default mapping of config space. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]>
2020-09-08PCI: dwc: Remove storing of PCI resourcesRob Herring4-29/+19
The PCI bridge resources are stored in pci_host_bridge.windows, so there's no need to store them in a DWC specific struct. There's also no need to parse the resources and store them a 2nd time as they are mainly used for one time setup of iATU windows. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Jonathan Chocron <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]>
2020-09-08PCI: dwc: Remove root_bus pointerRob Herring3-5/+4
The pci_host_bridge struct already has a pointer to its pci_bus, so let's convert the one user to use the bridge struct and remove the private 'root_bus' pointer. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected]
2020-09-08PCI: dwc: Convert to use pci_host_probe()Rob Herring2-19/+3
Now that there are no more .scan_bus() callbacks, we can remove it and just use pci_host_probe(). Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-08PCI: dwc: keystone: Convert .scan_bus() callback to use add_busRob Herring1-3/+9
TI keystone is the only Designware driver using .scan_bus(). This function pointer is the only thing preventing the Designware driver from using pci_host_probe(). Let's use the pci_ops.add_bus hook instead. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-08PCI: dwc: Use generic config accessorsRob Herring1-82/+37
Now that all the platforms with custom config access handling define their own pci_ops, let's split the default config accessors to use different pci_ops for root and child buses. With this, we can use the generic config accessors. The child bus accesses mainly require a .map_bus() hook to reconfigure the iATU on each config space access. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-09-08PCI: dwc: Remove dwc specific config accessor opsRob Herring2-20/+0
Now that all the drivers needing custom config accessors have been converted to define their own pci_ops, we can remove the DWC specific function callbacks {rd,wr}_{own,other}_conf. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
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