| Age | Commit message (Collapse) | Author | Files | Lines |
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Set the mode register to host(RC) mode so that the host controller
mode is set-up consistently across SoCs.
Signed-off-by: Kunihiko Hayashi <[email protected]>
[[email protected]: updated log]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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Remove <linux/pci.h> and <linux/msi.h> from being included directly as part
of the include/linux/of_pci.h, and remove superfluous declaration of struct
of_phandle_args.
Move users of include <linux/of_pci.h> to include <linux/pci.h> and
<linux/msi.h> directly rather than rely on both being included transitively
through <linux/of_pci.h>.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Wilczynski <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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Extend devm_of_pci_get_host_bridge_resources() and
pci_parse_request_of_pci_ranges() helpers to also parse the inbound
addresses from DT 'dma-ranges' and populate a resource list with the
translated addresses. This will help ensure 'dma-ranges' is always
parsed in a consistent way.
Tested-by: Srinath Mannam <[email protected]>
Tested-by: Thomas Petazzoni <[email protected]> # for AArdvark
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Srinath Mannam <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: Will Deacon <[email protected]>
Cc: Linus Walleij <[email protected]>
Cc: Toan Le <[email protected]>
Cc: Ley Foon Tan <[email protected]>
Cc: Tom Joseph <[email protected]>
Cc: Ray Jui <[email protected]>
Cc: Scott Branden <[email protected]>
Cc: [email protected]
Cc: Ryder Lee <[email protected]>
Cc: Karthikeyan Mitran <[email protected]>
Cc: Hou Zhiqiang <[email protected]>
Cc: Simon Horman <[email protected]>
Cc: Shawn Lin <[email protected]>
Cc: Heiko Stuebner <[email protected]>
Cc: Michal Simek <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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Add support for the LS1028a PCIe controller.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Acked-by: Minghuan Lian <[email protected]>
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Convert the Designware host bridge to use the common
pci_parse_request_of_pci_ranges().
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Andrew Murray <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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Corrects the programming to provide REFCLK to the downstream device
when there is no CLKREQ sideband signal routing present from root port
to the endpont.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Thierry Reding <[email protected]>
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find_next_bit() takes a parameter of size long, and performs arithmetic
that assumes that the argument is of size long.
Therefore we cannot pass a u32, since this will cause find_next_bit()
to read outside the stack buffer and will produce the following print:
BUG: KASAN: stack-out-of-bounds in find_next_bit+0x38/0xb0
Fixes: 1b497e6493c4 ("PCI: dwc: Fix uninitialized variable in dw_handle_msi_irq()")
Tested-by: Bjorn Andersson <[email protected]>
Signed-off-by: Niklas Cassel <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
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Add support for the Amlogic G12A SoC using a separate shared PHY.
This adds support for fetching a PHY phandle and call the PHY init,
reset and power on/off calls instead of writing in the PHY register or
toggling the PHY reset line.
The MIPI clock and the PHY memory resource are only required for the
Amlogic AXG SoC PCIe PHY setup, thus these elements are ignored for
the Amlogic G12A having a separate shared PHY.
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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Fix the clock names used in the probe function according
to the bindings.
Fixes: 9c0ef6d34fdb ("PCI: amlogic: Add the Amlogic Meson PCIe controller driver")
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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Normally asserting reset signal on gpio would be achieved with:
gpiod_set_value_cansleep(reset_gpio, 1);
Meson PCI driver set reset value to '0' instead of '1' as it takes into
account the PERST# signal polarity. The polarity should be taken care
in the device tree instead.
This fixes the reset assertion meaning and moves out the polarity
configuration in DT (please note that there is no DT currently using
this driver).
Signed-off-by: Remi Pommarel <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
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Code that iterates over all standard PCI BARs typically uses
PCI_STD_RESOURCE_END. However, that requires the unusual test
"i <= PCI_STD_RESOURCE_END" rather than something the typical
"i < PCI_STD_NUM_BARS".
Add a definition for PCI_STD_NUM_BARS and change loops to use the more
idiomatic C style to help avoid fencepost errors.
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Denis Efremov <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Sebastian Ott <[email protected]> # arch/s390/
Acked-by: Bartlomiej Zolnierkiewicz <[email protected]> # video/fbdev/
Acked-by: Gustavo Pimentel <[email protected]> # pci/controller/dwc/
Acked-by: Jack Wang <[email protected]> # scsi/pm8001/
Acked-by: Martin K. Petersen <[email protected]> # scsi/pm8001/
Acked-by: Ulf Hansson <[email protected]> # memstick/
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- Fix Tegra OF node reference leak (Nishka Dasgupta)
- Add #defines for PCIe Data Link Feature and Physical Layer 16.0 GT/s
features (Vidya Sagar)
- Disable MSI for Tegra Root Ports since they don't support using MSI for
all Root Port events (Vidya Sagar)
- Group DesignWare write-protected register writes together (Vidya Sagar)
- Move DesignWare capability search interfaces so they can be used by
both host and endpoint drivers (Vidya Sagar)
- Add DesignWare extended capability search interfaces (Vidya Sagar)
- Export dw_pcie_wait_for_link() so drivers can be modules (Vidya Sagar)
- Add "snps,enable-cdm-check" DT binding for Configuration Dependent
Module (CDM) register checking (Vidya Sagar)
- Add DesignWare support for "snps,enable-cdm-check" CDM checking (Vidya
Sagar)
- Add "supports-clkreq" DT binding for host drivers to decide whether to
advertise low power features (Vidya Sagar)
- Add DT binding for Tegra194 (Vidya Sagar)
- Add DT binding for Tegra194 P2U (PIPE to UPHY) block (Vidya Sagar)
- Add support for Tegra194 P2U (PIPE to UPHY) (Vidya Sagar)
- Add support for Tegra194 host controller (Vidya Sagar)
- Add Tegra support for sideband PERST# and CLKREQ# for C5 (Vidya Sagar)
- Add Tegra support for slot regulators for p2972-0000 platform (Vidya
Sagar)
* lorenzo/pci/tegra:
arm64: tegra: Add PCIe slot supply information in p2972-0000 platform
arm64: tegra: Add configuration for PCIe C5 sideband signals
PCI: tegra: Add support to enable slot regulators
PCI: tegra: Add support to configure sideband pins
dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries
dt-bindings: PCI: tegra: Add sideband pins configuration entries
PCI: tegra: Add Tegra194 PCIe support
phy: tegra: Add PCIe PIPE2UPHY support
dt-bindings: PHY: P2U: Add Tegra194 P2U block
dt-bindings: PCI: tegra: Add device tree support for Tegra194
dt-bindings: Add PCIe supports-clkreq property
PCI: dwc: Add support to enable CDM register check
dt-bindings: PCI: designware: Add binding for CDM register check
PCI: dwc: Export dw_pcie_wait_for_link() API
PCI: dwc: Add extended configuration space capability search API
PCI: dwc: Move config space capability search API
PCI: dwc: Group DBI registers writes requiring unlocking
PCI: Disable MSI for Tegra root ports
PCI: Add #defines for some of PCIe spec r4.0 features
PCI: tegra: Fix OF node reference leak
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- Propagate regulator_get_optional() errors so callers can distinguish
real errors from optional regulators that are absent (Thierry Reding)
- Propagate devm_of_phy_get() errors so callers can distinguish
real errors from optional PHYs that are absent (Thierry Reding)
- Add Andrew Murray as PCI native driver reviewer (Lorenzo Pieralisi)
* remotes/lorenzo/pci/misc:
MAINTAINERS: Add PCI native host/endpoint controllers designated reviewer
PCI: iproc: Propagate errors for optional PHYs
PCI: histb: Propagate errors for optional regulators
PCI: armada8x: Propagate errors for optional PHYs
PCI: imx6: Propagate errors for optional regulators
PCI: exynos: Propagate errors for optional PHYs
PCI: rockchip: Propagate errors for optional regulators
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- Mark Layerscape endpoint BARs 2 and 4 as 64-bit (Xiaowei Bao)
- Add CONFIG_PCI_LAYERSCAPE_EP so EP/RC can be built separately (Xiaowei
Bao)
* remotes/lorenzo/pci/layerscape:
PCI: layerscape: Add CONFIG_PCI_LAYERSCAPE_EP to build EP/RC separately
PCI: layerscape: Add the bar_fixed_64bit property to the endpoint driver
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- Reduce i.MX 6Quad DBI register length to avoid aborts from accessing
invalid registers (Stefan Agner)
* remotes/lorenzo/pci/imx:
PCI: imx6: Limit DBI register length
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- Make kirin_dw_pcie_ops constant (Nishka Dasgupta)
- Make DesignWare "num-lanes" property optional and remove from relevant
DTs (Hou Zhiqiang)
* remotes/lorenzo/pci/dwc:
arm64: dts: fsl: Remove num-lanes property from PCIe nodes
ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes
PCI: dwc: Return directly when num-lanes is not found
dt-bindings: PCI: designware: Remove the num-lanes from Required properties
PCI: kirin: Make structure kirin_dw_pcie_ops constant
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Add support to get regulator information of 3.3V and 12V supplies of a PCIe
slot from the respective controller's device-tree node and enable those
supplies. This is required in platforms like p2972-0000 where the supplies
to x16 slot owned by C5 controller need to be enabled before attempting to
enumerate the devices.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Acked-by: Thierry Reding <[email protected]>
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Add support to configure sideband signal pins when the information is
present in the respective controller device-tree node.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
[bhelgaas: fold in YueHaibing's fix for build error without CONFIG_PINCTRL;
https://lore.kernel.org/r/[email protected]]
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Acked-by: Thierry Reding <[email protected]>
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Some PCIe controllers can be set to either Host or EP according to some
early boot FW. To make sure there is no discrepancy (e.g. FW configured
the port to EP mode while the DT specifies it as a host bridge or vice
versa), a check has been added for each mode.
Signed-off-by: Jonathan Chocron <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
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This driver is DT based and utilizes the DesignWare APIs.
It allows using a smaller ECAM range for a larger bus range -
usually an entire bus uses 1MB of address space, but the driver
can use it for a larger number of buses. This is achieved by using a HW
mechanism which allows changing the BUS part of the "final" outgoing
config transaction. There are 2 HW regs, one which is basically a
bitmask determining which bits to take from the AXI transaction itself
and another which holds the complementary part programmed by the
driver.
All link initializations are handled by the boot FW.
Signed-off-by: Jonathan Chocron <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Gustavo Pimentel <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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Add support for Synopsys DesignWare core IP based PCIe host controller
present in the Tegra194 SoC.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Thierry Reding <[email protected]>
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regulator_get_optional() can fail for a number of reasons besides probe
deferral. It can for example return -ENOMEM if it runs out of memory as
it tries to allocate data structures. Propagating only -EPROBE_DEFER is
problematic because it results in these legitimately fatal errors being
treated as "regulator not specified in DT".
What we really want is to ignore the optional regulators only if they
have not been specified in DT. regulator_get_optional() returns -ENODEV
in this case, so that's the special case that we need to handle. So we
propagate all errors, except -ENODEV, so that real failures will still
cause the driver to fail probe.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Cc: Shawn Guo <[email protected]>
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devm_of_phy_get_by_index() can fail for a number of reasons besides
probe deferral. It can for example return -ENOMEM if it runs out of
memory as it tries to allocate devres structures. Propagating only
-EPROBE_DEFER is problematic because it results in these legitimately
fatal errors being treated as "PHY not specified in DT".
What we really want is to ignore the optional PHYs only if they have not
been specified in DT. devm_of_phy_get_by_index() returns -ENODEV in this
case, so that's the special case that we need to handle. So we propagate
all errors, except -ENODEV, so that real failures will still cause the
driver to fail probe.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
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regulator_get_optional() can fail for a number of reasons besides probe
deferral. It can for example return -ENOMEM if it runs out of memory as
it tries to allocate data structures. Propagating only -EPROBE_DEFER is
problematic because it results in these legitimately fatal errors being
treated as "regulator not specified in DT".
What we really want is to ignore the optional regulators only if they
have not been specified in DT. regulator_get_optional() returns -ENODEV
in this case, so that's the special case that we need to handle. So we
propagate all errors, except -ENODEV, so that real failures will still
cause the driver to fail probe.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: [email protected]
Cc: [email protected]
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devm_of_phy_get() can fail for a number of reasons besides probe
deferral. It can for example return -ENOMEM if it runs out of memory as
it tries to allocate devres structures. Propagating only -EPROBE_DEFER
is problematic because it results in these legitimately fatal errors
being treated as "PHY not specified in DT".
What we really want is to ignore the optional PHYs only if they have not
been specified in DT. devm_of_phy_get() returns -ENODEV in this case, so
that's the special case that we need to handle. So we propagate all
errors, except -ENODEV, so that real failures will still cause the
driver to fail probe.
Signed-off-by: Thierry Reding <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Kukjin Kim <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
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The num-lanes is optional since it is not needed on some platforms
that bring up the link in firmware.
The link programming is based on the num-lanes properties (which is
optional); if it is not present code must return instead of fiddling
with the lanes value to print an error message.
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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Static variable kirin_dw_pcie_ops, of type dw_pcie_ops, is used only
once, when it is assigned to the constant field ops of variable pci
(having type dw_pcie) so kirin_dw_pcie_ops is never modified.
Make it constant to protect it from unintended modification.
Issue found with Coccinelle.
Signed-off-by: Nishka Dasgupta <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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Define the length of the DBI registers and limit config space to its
length. This makes sure that the kernel does not access registers
beyond that point, avoiding the following abort on a i.MX 6Quad:
# cat /sys/devices/soc0/soc/1ffc000.pcie/pci0000\:00/0000\:00\:00.0/config
[ 100.021433] Unhandled fault: imprecise external abort (0x1406) at 0xb6ea7000
...
[ 100.056423] PC is at dw_pcie_read+0x50/0x84
[ 100.060790] LR is at dw_pcie_rd_own_conf+0x44/0x48
...
Signed-off-by: Stefan Agner <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Lucas Stach <[email protected]>
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Add CONFIG_PCI_LAYERSCAPE_EP so that endpoint and host controller
drivers can be built separately.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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The layerscape PCIe controller have 4 BARs.
BAR0 and BAR1 are 32bit, BAR2 and BAR4 are 64bit and that's a
fixed hardware configuration.
Set the bar_fixed_64bit variable accordingly.
Signed-off-by: Xiaowei Bao <[email protected]>
[[email protected]: commit log]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Kishon Vijay Abraham I <[email protected]>
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Add support to enable CDM (Configuration Dependent Module) register
check for any data corruption based on the DT property
'snps,enable-cdm-check'.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
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Export the dw_pcie_wait_for_link() function to be able to build drivers
using it as loadable modules.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Add extended configuration space capability search API using struct
dw_pcie* pointer.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
Acked-by: Thierry Reding <[email protected]>
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Move PCIe config space capability search API to common DesignWare file
as this can be used by both host and EP mode drivers.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
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Some of DesignWare core's DBI registers (a.k.a configuration space
registers) are write-protected with a lock without enabling which they
are read-only by default.
These write-protected registers are implementation specific. Tegra194's
BAR-0 register which is at offset 0x10 in the configuration space is an
example. Current implementation in dw_pcie_setup_rc() API attempts to
unlock those write-protected registers whenever they are updated and
lock them back again for writing.
Group all write-protected registers writes so that locking and unlocking
is performed once to avoid bloating the code with multiple unlock/lock
sequences for all those write-protected registers.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
Acked-by: Jingoo Han <[email protected]>
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- Fix typos and whitespace errors (Bjorn Helgaas)
* pci/trivial:
PCI: Fix typos and whitespace errors
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- Move qcom driver to bulk clock API (Bjorn Andersson)
- Add Qualcomm QCS404 PCIe controller support (Bjorn Andersson)
- Ensure Qualcomm PERST is asserted for at least 100ms (Niklas Cassel)
* remotes/lorenzo/pci/qcom:
PCI: qcom: Ensure that PERST is asserted for at least 100 ms
PCI: qcom: Add QCS404 PCIe controller support
dt-bindings: PCI: qcom: Add QCS404 to the binding
PCI: qcom: Use clk bulk API for 2.4.0 controllers
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- Add dwc API support to de-initialize host (Vidya Sagar)
- Clean up dwc DBI,ATU read and write APIs (Vidya Sagar)
- Export dwc APIs to support .remove() so drivers can be modular (Vidya
Sagar)
- Simplify imx6 Kconfig dependencies (Leonard Crestez)
- Fix dra7xx build error when !CONFIG_GPIOLIB (YueHaibing)
* remotes/lorenzo/pci/dwc:
PCI: dwc: pci-dra7xx: Fix compilation when !CONFIG_GPIOLIB
PCI: imx6: Simplify Kconfig depends on
PCI: dwc: Export APIs to support .remove() implementation
PCI: dwc: Cleanup DBI,ATU read and write APIs
PCI: dwc: Add API support to de-initialize host
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If CONFIG_GPIOLIB is not selected the compilation results in the
following build errors:
drivers/pci/controller/dwc/pci-dra7xx.c:
In function dra7xx_pcie_probe:
drivers/pci/controller/dwc/pci-dra7xx.c:777:10:
error: implicit declaration of function devm_gpiod_get_optional;
did you mean devm_regulator_get_optional? [-Werror=implicit-function-declaration]
reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
drivers/pci/controller/dwc/pci-dra7xx.c:778:45: error: ‘GPIOD_OUT_HIGH’
undeclared (first use in this function); did you mean ‘GPIOF_INIT_HIGH’?
reset = devm_gpiod_get_optional(dev, NULL, GPIOD_OUT_HIGH);
^~~~~~~~~~~~~~
GPIOF_INIT_HIGH
Fix them by including the appropriate header file.
Reported-by: Hulk Robot <[email protected]>
Signed-off-by: YueHaibing <[email protected]>
[[email protected]: commit log]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Kishon Vijay Abraham I <[email protected]>
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Fix typos in drivers/pci. Comment and whitespace changes only.
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Rafael J. Wysocki <[email protected]>
Reviewed-by: Randy Dunlap <[email protected]>
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The imx6 driver can be used on imx6sx without enabling support for
imx6q or imx7d but the "depends on" condition doesn't allow that.
Instead of making the condition even longer just make it depend on
"ARCH_MXC || COMPILE_TEST" instead.
Signed-off-by: Leonard Crestez <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Lucas Stach <[email protected]>
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Export all configuration space access APIs and also other APIs to
support host controller drivers of dwc core based implementations while
adding support for .remove() hook to build their respective drivers as
modules.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
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Cleanup DBI read and write APIs by removing leading "__" (underscore)
from their names as there is no reason to have leading underscores
in the first place in the function definition.
Remove dbi/dbi2 base address parameters as the same behaviour can be
obtained through read and write APIs. Since dw_pcie_{readl/writel}_dbi()
APIs can't be used for ATU read/write as ATU base address could be
different from DBI base address, implement ATU read/write APIs using ATU
base address without using dw_pcie_{readl/writel}_dbi() APIs.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Jingoo Han <[email protected]>
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Add an API to group all the tasks to be done to de-initialize host which
can then be called by any dwc core based driver implementations
while adding .remove() support in their respective drivers.
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
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Bring PHY support for the Armada8k driver.
The Armada8k IP only supports x1, x2 or x4 link widths. Iterate over
the DT 'phys' entries and configure them one by one. Use
phy_set_mode_ext() to make use of the submode parameter (initially
introduced for Ethernet modes). For PCI configuration, let the submode
be the width (1, 2, 4, etc) so that the PHY driver knows how many
lanes are bundled. Do not error out in case of error for compatibility
reasons.
Signed-off-by: Miquel Raynal <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Thomas Petazzoni <[email protected]>
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Currently, there is only a 1 ms sleep after asserting PERST.
Reading the datasheets for different endpoints, some require PERST to be
asserted for 10 ms in order for the endpoint to perform a reset, others
require it to be asserted for 50 ms.
Several SoCs using this driver uses PCIe Mini Card, where we don't know
what endpoint will be plugged in.
The PCI Express Card Electromechanical Specification r2.0, section
2.2, "PERST# Signal" specifies:
"On power up, the deassertion of PERST# is delayed 100 ms (TPVPERL) from
the power rails achieving specified operating limits."
Add a sleep of 100 ms before deasserting PERST, in order to ensure that
we are compliant with the spec.
Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
Signed-off-by: Niklas Cassel <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Stanimir Varbanov <[email protected]>
Cc: [email protected] # 4.5+
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The QCS404 platform contains a PCIe version 2.4.0 controller and a
Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the
IPQ4019, but this support touches clocks and resets related to the PHY
as well and there's no upstream driver for the PHY.
On QCS404 we must initialize the PHY, so a separate PHY driver is
implemented to take care of this and the controller driver is updated to
not require the PHY related resources. This is done by relying on the
fact that operations in both the clock and reset framework are NOPs when
passed NULL, so we can isolate this change to only the
qcom_pcie_get_resources_2_4_0() function.
For QCS404 we also need to enable the AHB (iface) clock, in order to
access the register space of the controller, but as this is not part of
the IPQ4019 DT binding this is only added for new users of the 2.4.0
controller.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Niklas Cassel <[email protected]>
Reviewed-by: Vinod Koul <[email protected]>
Acked-by: Stanimir Varbanov <[email protected]>
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Before introducing the QCS404 platform, which uses the same PCIe
controller as IPQ4019, migrate this to use the bulk clock API, in order
to make the error paths slighly cleaner.
Signed-off-by: Bjorn Andersson <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Niklas Cassel <[email protected]>
Reviewed-by: Vinod Koul <[email protected]>
Acked-by: Stanimir Varbanov <[email protected]>
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- Exit pcitest with error code when test fails (Jean-Jacques Hiblot)
- Fix leaked of_node references in dra7xx, uniphier, layerscape,
rockchip, aardvark, iproc, mediatek, rpadlpar (Wen Yang)
- Fix pcitest "help" option parsing (Kishon Vijay Abraham I)
- Fix Makefile bug that inadvertently removes pcitest.sh (Kishon Vijay
Abraham I)
- Check for alloc_workqueue() failure in endpoint test driver (Kangjie
Lu)
* remotes/lorenzo/pci/misc:
PCI: endpoint: Fix a potential NULL pointer dereference
tools: PCI: Handle pcitest.sh independently from pcitest
tools: PCI: Add 'h' in optstring of getopt()
PCI: mediatek: Fix a leaked reference by adding missing of_node_put()
PCI: iproc: Fix a leaked reference by adding missing of_node_put()
PCI: aardvark: Fix a leaked reference by adding missing of_node_put()
PCI: rockchip: Fix a leaked reference by adding missing of_node_put()
PCI: dwc: layerscape: Fix a leaked reference by adding missing of_node_put()
PCI: uniphier: Fix a leaked reference by adding missing of_node_put()
PCI: dwc: pci-dra7xx: Fix a leaked reference by adding missing of_node_put()
tools: PCI: Exit with error code when test fails
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- Move IRQ register address computation inside macros (Kishon Vijay
Abraham I)
- Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I)
- Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham
I)
- Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon
Vijay Abraham I)
- Add dwc support for platforms with custom MSI controllers (Kishon Vijay
Abraham I)
- Add keystone-specific MSI controller (Kishon Vijay Abraham I)
- Remove dwc host_ops previously used for keystone-specific MSI (Kishon
Vijay Abraham I)
- Skip dwc default MSI init if platform has custom MSI controller (Kishon
Vijay Abraham I)
- Implement .start_link() and .stop_link() for keystone endpoint support
(Kishon Vijay Abraham I)
- Add keystone "reg-names" DT binding (Kishon Vijay Abraham I)
- Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon
Vijay Abraham I)
- Get keystone register resources from DT by name, not index (Kishon
Vijay Abraham I)
- Get DT resources in .probe() to prepare for endpoint support (Kishon
Vijay Abraham I)
- Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration
(Kishon Vijay Abraham I)
- Explicitly set keystone to host mode (Kishon Vijay Abraham I)
- Document DT "atu" reg-names requirement for DesignWare core >= 4.80
(Kishon Vijay Abraham I)
- Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon
Vijay Abraham I)
- Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon
Vijay Abraham I)
- Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham
I)
- Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham
I)
- Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I)
- Reset keystone PHYs before enabling them (Kishon Vijay Abraham I)
- Make of_pci_get_max_link_speed() available to endpoint drivers as well
as host drivers (Kishon Vijay Abraham I)
- Add keystone support for DT "max-link-speed" property (Kishon Vijay
Abraham I)
- Add endpoint library support for BAR buffer alignment (Kishon Vijay
Abraham I)
- Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I)
- Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay
Abraham I)
- Add dwc hooks for dbi/dbi2 that share the same address space (Kishon
Vijay Abraham I)
- Add keystone support for TI AM654x in endpoint mode (Kishon Vijay
Abraham I)
- Configure designware endpoints to advertise smallest resizable BAR
(1MB) (Kishon Vijay Abraham I)
- Align designware endpoint ATU windows for raising MSIs (Kishon Vijay
Abraham I)
- Add endpoint test support for TI AM654x (Kishon Vijay Abraham I)
- Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I)
* remotes/lorenzo/pci/keystone:
misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test
misc: pci_endpoint_test: Add support to test PCI EP in AM654x
PCI: designware-ep: Use aligned ATU window for raising MSI interrupts
PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size
PCI: keystone: Add support for PCIe EP in AM654x Platforms
dt-bindings: PCI: Add PCI EP DT binding documentation for AM654
PCI: dwc: Add callbacks for accessing dbi2 address space
PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset
PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops
PCI: endpoint: Add support to specify alignment for buffers allocated to BARs
PCI: keystone: Add support to set the max link speed from DT
PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers
PCI: keystone: Invoke phy_reset() API before enabling PHY
PCI: keystone: Add support for PCIe RC in AM654x Platforms
dt-bindings: PCI: Add PCI RC DT binding documentation for AM654
PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64
PCI: dwc: Fix ATU identification for designware version >= 4.80
PCI: dwc: Enable iATU unroll for endpoint too
dt-bindings: PCI: Document "atu" reg-names
PCI: keystone: Explicitly set the PCIe mode
dt-bindings: PCI: Add dt-binding to configure PCIe mode
PCI: keystone: Move resources initialization to prepare for EP support
PCI: keystone: Use platform_get_resource_byname() to get memory resources
PCI: keystone: Perform host initialization in a single function
dt-bindings: PCI: keystone: Add "reg-names" binding information
PCI: keystone: Cleanup error_irq configuration
PCI: keystone: Add start_link()/stop_link() dw_pcie_ops
PCI: dwc: Remove default MSI initialization for platform specific MSI chips
PCI: dwc: Remove Keystone specific dw_pcie_host_ops
PCI: keystone: Use Keystone specific msi_irq_chip
PCI: dwc: Add support to use non default msi_irq_chip
PCI: keystone: Cleanup ks_pcie_msi_irq_handler()
PCI: keystone: Use hwirq to get the MSI IRQ number offset
PCI: keystone: Add separate functions for configuring MSI and legacy interrupt
PCI: keystone: Cleanup interrupt related macros
# Conflicts:
# drivers/pci/controller/dwc/pcie-designware.h
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