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Many calls to dw_pcie_host_init() are in a wrapper function with
nothing else now. Let's remove the pointless extra layer.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Minghuan Lian <[email protected]>
Cc: Mingkai Hu <[email protected]>
Cc: Roy Zang <[email protected]>
Cc: Yue Wang <[email protected]>
Cc: Kevin Hilman <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Martin Blumenstingl <[email protected]>
Cc: Jonathan Chocron <[email protected]>
Cc: Jesper Nilsson <[email protected]>
Cc: Xiaowei Song <[email protected]>
Cc: Binghui Wang <[email protected]>
Cc: Kunihiko Hayashi <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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All RC complex drivers must call dw_pcie_setup_rc(). The ordering of the
call shouldn't be too important other than being after any RC resets.
There's a few calls of dw_pcie_setup_rc() left as drivers implementing
suspend/resume need it.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Jingoo Han <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Kukjin Kim <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Minghuan Lian <[email protected]>
Cc: Mingkai Hu <[email protected]>
Cc: Roy Zang <[email protected]>
Cc: Yue Wang <[email protected]>
Cc: Kevin Hilman <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Martin Blumenstingl <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: Jesper Nilsson <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Xiaowei Song <[email protected]>
Cc: Binghui Wang <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Stanimir Varbanov <[email protected]>
Cc: Pratyush Anand <[email protected]>
Cc: Kunihiko Hayashi <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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The host drivers which call dw_pcie_msi_init() are all the ones using
the built-in MSI controller, so let's move it into the common DWC code.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Jingoo Han <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Kukjin Kim <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: Yue Wang <[email protected]>
Cc: Kevin Hilman <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Martin Blumenstingl <[email protected]>
Cc: Jesper Nilsson <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Xiaowei Song <[email protected]>
Cc: Binghui Wang <[email protected]>
Cc: Stanimir Varbanov <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Pratyush Anand <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: Kunihiko Hayashi <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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All the DWC drivers do link setup and checks at roughly the same time.
Let's use the existing .start_link() hook (currently only used in EP
mode) and move the link handling to the core code.
The behavior for a link down was inconsistent as some drivers would fail
probe in that case while others succeed. Let's standardize this to
succeed as there are usecases where devices (and the link) appear later
even without hotplug. For example, a reconfigured FPGA device.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Jingoo Han <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Kukjin Kim <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Yue Wang <[email protected]>
Cc: Kevin Hilman <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Martin Blumenstingl <[email protected]>
Cc: Thomas Petazzoni <[email protected]>
Cc: Jesper Nilsson <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Xiaowei Song <[email protected]>
Cc: Binghui Wang <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Stanimir Varbanov <[email protected]>
Cc: Pratyush Anand <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: Kunihiko Hayashi <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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There are 3 possible MSI implementations for the DWC host. The first is
using the built-in DWC MSI controller. The 2nd is a custom MSI
controller as part of the PCI host (keystone only). The 3rd is an
external MSI controller (typically GICv3 ITS). Currently, the last 2
are distinguished with a .msi_host_init() hook with the 3rd option using
an empty function. However we can detect the 3rd case with the presence
of 'msi-parent' or 'msi-map' properties, so let's do that instead and
remove the empty functions.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Jingoo Han <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Minghuan Lian <[email protected]>
Cc: Mingkai Hu <[email protected]>
Cc: Roy Zang <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: [email protected]
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Platforms using the built-in DWC MSI controller all have a dedicated
interrupt with "msi" name or at index 0, so let's move setting up the
interrupt to the common DWC code.
spear13xx and dra7xx are the 2 oddballs with muxed interrupts, so
we need to prevent configuring the MSI interrupt by setting msi_irq
to negative.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Jingoo Han <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Kukjin Kim <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: Yue Wang <[email protected]>
Cc: Kevin Hilman <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Jerome Brunet <[email protected]>
Cc: Martin Blumenstingl <[email protected]>
Cc: Jesper Nilsson <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Xiaowei Song <[email protected]>
Cc: Binghui Wang <[email protected]>
Cc: Stanimir Varbanov <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Pratyush Anand <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: Kunihiko Hayashi <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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There's no reason for the .set_num_vectors() host op. Drivers needing a
non-default value can just initialize pcie_port.num_vectors directly.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: [email protected]
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The dra7xx MSI irq_chip implementation is identical to the default DWC one.
The only difference is the interrupt handler as the MSI interrupt is muxed
with other interrupts, but that doesn't affect the irq_chip part of it.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: [email protected]
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The Layerscape driver clears the ATU registers which may have been
configured by the bootloader. Any driver could have the same issue
and doing it for all drivers doesn't hurt, so let's move it into the
common DWC code.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Jingoo Han <[email protected]>
Cc: Minghuan Lian <[email protected]>
Cc: Mingkai Hu <[email protected]>
Cc: Roy Zang <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: [email protected]
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Remove some of the pointless levels of functions that just wrap or group
a series of other functions.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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Most DWC drivers use the common register resource names "dbi", "dbi2", and
"addr_space", so let's move their setup into the DWC common code.
This means 'dbi_base' in particular is setup later, but it looks like no
drivers touch DBI registers before dw_pcie_host_init or dw_pcie_ep_init.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Jingoo Han <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Minghuan Lian <[email protected]>
Cc: Mingkai Hu <[email protected]>
Cc: Roy Zang <[email protected]>
Cc: Jonathan Chocron <[email protected]>
Cc: Jesper Nilsson <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Xiaowei Song <[email protected]>
Cc: Binghui Wang <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Stanimir Varbanov <[email protected]>
Cc: Pratyush Anand <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: Kunihiko Hayashi <[email protected]>
Cc: Masahiro Yamada <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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The ATU offset should be a register range in DT called 'atu', not driver
match data. Any future platforms with a different ATU offset should add
it to their DT.
This is also in preparation to do DBI resource setup in the core DWC
code, so let's move setting atu_base later in intel_pcie_rc_setup().
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Marek Szyprowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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Currently the Keystone driver can only be compile-tested on ARM, but
this restriction seems unnecessary. Get rid of it to increase test
coverage.
Build-tested with allyesconfig on x86, ppc, mips and riscv.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alex Dewar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Rob Herring <[email protected]>
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Add support to program the ATU to enable translations for >4GB sizes of
the prefetchable memory apertures.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Thierry Reding <[email protected]>
Tested-by: Jon Hunter <[email protected]>
Signed-off-by: Vidya Sagar <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Acked-by: Jingoo <[email protected]>
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The current ATU setup only supports a single memory resource which
isn't sufficient if there are also prefetchable memory regions. In order
to support multiple memory regions, we need to move away from fixed ATU
slots and rework the assignment. As there's always an ATU entry for
config space, let's assign index 0 to config space. Then we assign
memory resources to index 1 and up. Finally, if we have an I/O region
and slots remaining, we assign the I/O region last. If there aren't
remaining slots, we keep the same config and I/O space sharing.
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Vidya Sagar <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Vidya Sagar <[email protected]>
Acked-by: Jingoo Han <[email protected]>
Cc: Vidya Sagar <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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Prior to commit 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources"),
the DWC driver was setting up the last memory resource rather than the
first memory resource. This doesn't matter for most platforms which only
have 1 memory resource, but it broke Tegra194 which has a 2nd
(prefetchable) memory region that requires an ATU entry. The first region
on Tegra194 relies on the default 1:1 pass-thru of outbound transactions
and doesn't need an ATU entry.
Fixes: 0f71c60ffd26 ("PCI: dwc: Remove storing of PCI resources")
Link: https://lore.kernel.org/r/[email protected]
Reported-by: Vidya Sagar <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Acked-by: Lorenzo Pieralisi <[email protected]>
Acked-by: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
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- Drop return value checking for debugfs_create() calls (Greg
Kroah-Hartman)
- Convert debugfs "ports" file to use DEFINE_SEQ_ATTRIBUTE() (Liu Shixin)
* remotes/lorenzo/pci/tegra:
PCI: tegra: Convert to use DEFINE_SEQ_ATTRIBUTE macro
PCI: tegra: No need to check return value of debugfs_create() functions
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- Make sure PCIe is reset before init to work around QSDK U-Boot issue
(Ansuel Smith)
- Set iproc affinity mask on MSI interrupts (Mark Tomlinson)
* remotes/lorenzo/pci/qcom:
PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0
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- Add pci-meson module support and enable by default on ARCH_MESON (Kevin
Hilman)
* remotes/lorenzo/pci/meson:
PCI: meson: Build as module by default
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- Return -EPROBE_DEFER in case the gpio isn't ready (Bean Huo)
* remotes/lorenzo/pci/kirin:
PCI: kirin: Return -EPROBE_DEFER in case the gpio isn't ready
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- Use "fallthrough" pseudo-keyword (Gustavo A. R. Silva)
- Drop redundant error messages after devm_clk_get() (Anson Huang)
* remotes/lorenzo/pci/imx6:
PCI: imx6: Do not output error message when devm_clk_get() failed with -EPROBE_DEFER
PCI: imx6: Use fallthrough pseudo-keyword
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NXP Layerscape (ls1028a, ls2088a), dra7xxx and imx6 platforms are either
programmed or statically configured to forward the error triggered by a
link-down state (eg no connected endpoint device) on the system bus for
PCI configuration transactions; these errors are reported as an SError
at system level, which is fatal.
Enumerating a PCI tree when the PCIe link is down is not sensible
either, so even if the link-up check is racy (link can go down after
map_bus() is called) add a link-up check in map_bus() to prevent issuing
configuration transactions when the link is down.
SError report:
SError Interrupt on CPU2, code 0xbf000002 -- SError
CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67
Hardware name: LS1046A RDB Board (DT)
pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--)
pc : pci_generic_config_read+0x3c/0xe0
lr : pci_generic_config_read+0x24/0xe0
sp : ffff80001003b7b0
x29: ffff80001003b7b0 x28: ffff80001003ba74
x27: ffff000971d96800 x26: ffff00096e77e0a8
x25: ffff80001003b874 x24: ffff80001003b924
x23: 0000000000000004 x22: 0000000000000000
x21: 0000000000000000 x20: ffff80001003b874
x19: 0000000000000004 x18: ffffffffffffffff
x17: 00000000000000c0 x16: fffffe0025981840
x15: ffffb94c75b69948 x14: 62203a383634203a
x13: 666e6f635f726568 x12: 202c31203d207265
x11: 626d756e3e2d7375 x10: 656877202c307830
x9 : 203d206e66766564 x8 : 0000000000000908
x7 : 0000000000000908 x6 : ffff800010900000
x5 : ffff00096e77e080 x4 : 0000000000000000
x3 : 0000000000000003 x2 : 84fa3440ff7e7000
x1 : 0000000000000000 x0 : ffff800010034000
Kernel panic - not syncing: Asynchronous SError Interrupt
CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.9.0-rc5-next-20200914-00001-gf965d3ec86fa #67
Hardware name: LS1046A RDB Board (DT)
Call trace:
dump_backtrace+0x0/0x1c0
show_stack+0x18/0x28
dump_stack+0xd8/0x134
panic+0x180/0x398
add_taint+0x0/0xb0
arm64_serror_panic+0x78/0x88
do_serror+0x68/0x180
el1_error+0x84/0x100
pci_generic_config_read+0x3c/0xe0
dw_pcie_rd_other_conf+0x78/0x110
pci_bus_read_config_dword+0x88/0xe8
pci_bus_generic_read_dev_vendor_id+0x30/0x1b0
pci_bus_read_dev_vendor_id+0x4c/0x78
pci_scan_single_device+0x80/0x100
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Hou Zhiqiang <[email protected]>
[[email protected]: rewrote the commit log, remove Fixes tag]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Currently, dw_pcie_msi_init() allocates and maps page for msi, then
program the PCIE_MSI_ADDR_LO and PCIE_MSI_ADDR_HI. The Root Complex
may lose power during suspend-to-RAM, so when we resume, we want to
redo the latter but not the former. If designware based driver (for
example, pcie-tegra194.c) calls dw_pcie_msi_init() in resume path, the
msi page will be leaked.
As pointed out by Rob and Ard, there's no need to allocate a page for
the MSI address, we could use an address in the driver data.
To avoid map the MSI msg again during resume, we move the map MSI msg
from dw_pcie_msi_init() to dw_pcie_host_init().
Suggested-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jisheng Zhang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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If MSI is disabled, there's no need to program PCIE_MSI_INTR0_MASK
and PCIE_MSI_INTR0_ENABLE registers.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jisheng Zhang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
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After applying "PCI: dwc: Add common iATU register support",
there is no need to set own iATU in the Keystone driver itself.
Suggested-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kunihiko Hayashi <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
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This gets iATU register area from reg property that has reg-names "atu".
In Synopsys DWC version 4.80 or later, since iATU register area is
separated from core register area, this area is necessary to get from
DT independently.
Suggested-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kunihiko Hayashi <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
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Enable pci-meson to build as a module whenever ARCH_MESON is enabled.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Kevin Hilman <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Cc: Yue Wang <[email protected]>
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PCI host bridge driver can be probed before the gpiochip it requires,
so, of_get_named_gpio() can return -EPROBE_DEFER. Current code lets the
kirin_pcie_probe() directly return -ENODEV, which results in the PCI
host controller driver probe failure; with this error code the PCI host
controller driver will not be probed again when the gpiochip driver is
loaded.
Fix the above issue by letting kirin_pcie_probe() return -EPROBE_DEFER in
such a case.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bean Huo <[email protected]>
[[email protected]: commit log]
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Fixes warning given by executing "make C=2 drivers/pci/"
Sparse output:
CHECK drivers/pci/controller/dwc/pcie-designware.c
drivers/pci/controller/dwc/pcie-designware.c:432:52: warning:
cast truncates bits from constant value (ffffffff7fffffff becomes
7fffffff)
Link: https://lore.kernel.org/r/7ea7f7d342f97c758949a17b870012f52ce5b3f5.1600767645.git.gustavo.pimentel@synopsys.com
Reported-by: Bjorn Helgaas <[email protected]>
Signed-off-by: Gustavo Pimentel <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Joao Pinto <[email protected]>
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Add PCIe EP mode support for ls1088a and ls2088a, there are some
difference between LS1 and LS2 platform, so refactor the code of
the EP driver.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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dw_pcie_ep_raise_msix_irq was never called in the exisitng driver
before, because the ls1046a platform don't support the MSIX feature
and msix_capable was always set to false.
Now that add the ls1088a platform with MSIX support, use the doorbell
method to support the MSIX feature.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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The different PCIe controller in one board may be have different
capability of MSI or MSIX, so change the way of getting the MSI
capability, make it more flexible.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
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Fix some format issue of the code in EP driver.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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Each PF of EP device should have its own MSI or MSIX capabitily
struct, so create a dw_pcie_ep_func struct and move the msi_cap
and msix_cap to this struct from dw_pcie_ep, and manage the PFs
via a list.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
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Move the function of getting MSI capability to the front of init
function, because the init function of the EP platform driver will use
the return value by the function of getting MSI capability.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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Add the doorbell mode of MSI-X in DWC EP driver.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Andrew Murray <[email protected]>
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Add multiple PFs support for DWC, due to different PF have different
config space, we use func_conf_select callback function to access
the different PF's config space, the different chip company need to
implement this callback function when use the DWC IP core and intend
to support multiple PFs feature.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Hou Zhiqiang <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Acked-by: Gustavo Pimentel <[email protected]>
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Convert the remaining cases of register accesses using dbi_base rather
than dw_pcie_(read|write)[bwl]_dbi accessors.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Pratyush Anand <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: [email protected]
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The Designware controller has common registers to set number of fast
training sequence ordered sets. The Artpec6, Intel, and Tegra driver
initialize these register fields. Let's move the initialization to the
common setup code and drivers just have to provide the value.
There's a slight change in that the common clock mode N_FTS field is
now initialized. Previously only the Intel driver set this. It's not
clear from the code if common clock mode is used in the Artpec6 or Tegra
driver. It depends on the DWC configuration. Given the field is not
initialized while the others are, it seems unlikely common clock mode
is used.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Jesper Nilsson <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: [email protected]
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'max_width' is read, but never used, so let's remove it.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Dilip Kota <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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The PCI_CAP_ID_EXP offset is only needed by intel_pcie_link_setup(), so
let's retrieve it there and avoid storing the offset.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Dilip Kota <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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A driver doesn't need to check for DT 'device_type' property, so let's
remove the check.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Dilip Kota <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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The Intel driver is the only one to set PORT_LINK_DLL_LINK_EN. The
default value is set and it seems pretty certain that enabling link
initialization is always required. Maybe it could just be dropped from
the Intel driver, but lets move setting it into the common code to be
sure.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Dilip Kota <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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keystone would force gen2 if no DT property. Now it relies on the
PCI_EXP_LNKCAP value.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Stanimir Varbanov <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Pratyush Anand <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
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The ATU registers are only accessed in pcie-designware.c and can be private
to it.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
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The DBI2 appears to be write-only and there's no read accesses in the code
anyways, so let's remove all the read_dbi2 related code.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
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The Tegra driver has its own defines for common Designware Port Logic
registers. Convert it to use the standard register definitions.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Jingoo Han <[email protected]>
Cc: Gustavo Pimentel <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Thierry Reding <[email protected]>
Cc: Jonathan Hunter <[email protected]>
Cc: [email protected]
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While the Designware controller appears to hard code the PCI_CAP_ID_EXP
capability register at 0x70, there's no need to hard code this in the
driver as it is discoverable.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Murali Karicheri <[email protected]>
Cc: Pratyush Anand <[email protected]>
Cc: [email protected]
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The QCom driver has its own defines for common PCI config space
registers. It also hard codes the capability register offsets which are
discoverable. Convert it to use the standard register definitions.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Stanimir Varbanov <[email protected]>
Cc: Andy Gross <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: [email protected]
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The i.MX6 driver has its own defines for common PCI config space
registers. It also hard codes the capability register offsets which are
discoverable. Convert it to use the standard register definitions.
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Lorenzo Pieralisi <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: Lucas Stach <[email protected]>
Cc: Lorenzo Pieralisi <[email protected]>
Cc: Bjorn Helgaas <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Pengutronix Kernel Team <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: NXP Linux Team <[email protected]>
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