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path: root/drivers/pci/controller/dwc
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2019-03-06Merge branch 'remotes/lorenzo/pci/endpoint'Bjorn Helgaas6-5/+196
- Use memcpy_fromio()/memcpy_toio() instead of plain memcpy() in PCI endpoint framework (Wen Yang) - Add interface to discover supported endpoint features to replace a bitfield that wasn't flexible enough (Kishon Vijay Abraham I) - Implement the new supported-feature interface for designware-plat, dra7xx, rockchip, cadence (Kishon Vijay Abraham I) - Fix issues with 64-bit BAR in endpoints (Kishon Vijay Abraham I) - Add layerscape endpoint mode support (Xiaowei Bao) * remotes/lorenzo/pci/endpoint: misc: pci_endpoint_test: Add the layerscape EP device support PCI: layerscape: Add EP mode support arm64: dts: Add the PCIE EP node in dts dt-bindings: add DT binding for the layerscape PCIe controller with EP mode PCI: endpoint: Remove features member in struct pci_epc PCI: designware-plat: Remove setting epc->features in Designware plat EP driver PCI: rockchip: Remove pci_epf_linkup() from Rockchip EP driver PCI: cadence: Remove pci_epf_linkup() from Cadence EP driver PCI: pci-epf-test: Use pci_epc_get_features() to get EPC features PCI: pci-epf-test: Do not allocate next BARs memory if current BAR is 64Bit PCI: pci-epf-test: Remove setting epf_bar flags in function driver PCI: endpoint: Fix pci_epf_alloc_space() to set correct MEM TYPE flags PCI: endpoint: Add helper to get first unreserved BAR PCI: cadence: Populate ->get_features() cdns_pcie_epc_ops PCI: rockchip: Populate ->get_features() dw_pcie_ep_ops PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_ops PCI: designware-plat: Populate ->get_features() dw_pcie_ep_ops PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_ops PCI: endpoint: Add new pci_epc_ops to get EPC features PCI: endpoint: functions: Use memcpy_fromio()/memcpy_toio()
2019-03-01PCI: dwc: skip MSI init if MSIs have been explicitly disabledLucas Stach1-1/+1
Since 7c5925afbc58 (PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API) the MSI init claims one of the controller IRQs as a chained IRQ line for the MSI controller. On some designs, like the i.MX6, this line is shared with a PCIe legacy IRQ. When the line is claimed for the MSI domain, any device trying to use this legacy IRQs will fail to request this IRQ line. As MSI and legacy IRQs are already mutually exclusive on the DWC core, as the core won't forward any legacy IRQs once any MSI has been enabled, users wishing to use legacy IRQs already need to explictly disable MSI support (usually via the pci=nomsi kernel commandline option). To avoid any issues with MSI conflicting with legacy IRQs, just skip all of the DWC MSI initalization, including the IRQ line claim, when MSI is disabled. Fixes: 7c5925afbc58 ("PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API") Tested-by: Tim Harvey <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Cc: [email protected]
2019-03-01PCI: dwc: Remove superfluous shifting in definitionsAndrey Smirnov1-7/+7
Surrounding definitions no longer use explicit shift, so "<< 0" here serve no purpose. Remove them. No functional change intended. Signed-off-by: Andrey Smirnov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Chris Healy <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Leonard Crestez <[email protected]> Cc: "A.s. Dong" <[email protected]> Cc: Richard Zhu <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-03-01PCI: dwc: Make use of GENMASK/FIELD_PREPAndrey Smirnov1-13/+16
Convert various multi-bit fields to be defined using GENMASK/FIELD_PREP. This way bit field boundaries are defined in a single place only, as well as defined in a way that makes it easier to verify them against the reference manual. No functional change intended. Signed-off-by: Andrey Smirnov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Chris Healy <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Leonard Crestez <[email protected]> Cc: "A.s. Dong" <[email protected]> Cc: Richard Zhu <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-03-01PCI: dwc: Make use of BIT() in constant definitionsAndrey Smirnov3-9/+8
Avoid using explicit left shifts and convert various definitions to use BIT() instead. No functional change intended. Signed-off-by: Andrey Smirnov <[email protected]> [[email protected]: fixed PORT_LOGIC_SPEED_CHANGE redefinition] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Chris Healy <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Leonard Crestez <[email protected]> Cc: "A.s. Dong" <[email protected]> Cc: Richard Zhu <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-03-01PCI: dwc: Share code for dw_pcie_rd/wr_other_conf()Andrey Smirnov1-38/+23
Default implementation of pcie_rd_other_conf() and dw_pcie_wd_other_conf() share more than 80% of their code. Move shared code into a dedicated subroutine and convert pcie_rd_other_conf() and dw_pcie_wd_other_conf() to use it. No functional change intended. Signed-off-by: Andrey Smirnov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Chris Healy <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Leonard Crestez <[email protected]> Cc: "A.s. Dong" <[email protected]> Cc: Richard Zhu <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-03-01PCI: dwc: Make use of IS_ALIGNED()Andrey Smirnov1-2/+2
Make the intent a bit more clear as well as get rid of explicit arithmetic by using IS_ALIGNED() to determine if "addr" is aligned to "size". No functional change intended. Signed-off-by: Andrey Smirnov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Chris Healy <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Leonard Crestez <[email protected]> Cc: "A.s. Dong" <[email protected]> Cc: Richard Zhu <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-03-01PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQAndrey Smirnov1-1/+17
The PCIe IP block has an additional clock, "pcie_aux", that needs to be controlled by the driver. Add code to support it. Signed-off-by: Andrey Smirnov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Chris Healy <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Leonard Crestez <[email protected]> Cc: "A.s. Dong" <[email protected]> Cc: Richard Zhu <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: Rob Herring <[email protected]> Cc: [email protected]
2019-02-28PCI: qcom: Don't deassert reset GPIO during probeBjorn Andersson1-1/+1
Acquiring the reset GPIO low means that reset is being deasserted, this is followed almost immediately with qcom_pcie_host_init() asserting it, initializing it and then finally deasserting it again, for the link to come up. Some PCIe devices requires a minimum time between the initial deassert and subsequent reset cycles. In a platform that boots with the reset GPIO asserted this requirement is being violated by this deassert/assert pulse. Acquire the reset GPIO high to prevent this situation by matching the state to the subsequent asserted state. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Bjorn Andersson <[email protected]> [[email protected]: updated commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected]
2019-02-21PCI: layerscape: Add EP mode supportXiaowei Bao2-1/+157
Add the PCIe EP mode support to the layerscape platform controller. Signed-off-by: Xiaowei Bao <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Minghuan Lian <[email protected]> Reviewed-by: Zhiqiang Hou <[email protected]> Reviewed-by: Kishon Vijay Abraham I <[email protected]>
2019-02-15PCI: designware-plat: Remove setting epc->features in Designware plat EP driverKishon Vijay Abraham I1-4/+0
Now that pci-epf-test uses get_features callback and dw_plat_pcie_epc_features in Designware plat EP driver already indicates it doesn't support linkup notification and is MSIX capable, remove setting epc->features which is not used anymore by the endpoint function driver. Tested-by: Gustavo Pimentel <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-02-14PCI: pci-dra7xx: Populate ->get_features() dw_pcie_ep_opsKishon Vijay Abraham I1-0/+13
Populate ->get_features() dw_pcie_ep_ops to return the EPC features supported by DRA7xx PCIe endpoint controller. Tested-by: Gustavo Pimentel <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-02-14PCI: designware-plat: Populate ->get_features() dw_pcie_ep_opsKishon Vijay Abraham I1-0/+13
Populate ->get_features() dw_pcie_ep_ops to return the EPC features supported by Designware PCIe endpoint controller. Tested-by: Gustavo Pimentel <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-02-14PCI: dwc: Add ->get_features() callback function to dw_pcie_ep_opsKishon Vijay Abraham I2-0/+13
Each platform using Designware PCIe core can support different set of endpoint features. Add a new callback function ->get_features() in dw_pcie_ep_ops so that each platform using Designware PCIe core can advertise its supported features to the endpoint function driver. Tested-by: Gustavo Pimentel <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-02-12PCI: imx: Add workaround for e10728, IMX7d PCIe PLL failureTrent Piepho1-0/+57
This implements the workound described in the NXP IMX7d erratum e10728. Initial VCO oscillation may fail under corner conditions such as cold temperature. It causes PCIe PLL to fail to lock in the initialization phase, which results in the PCIe link failing to come up. The workaround is to disable Duty-Cycle Corrector (DCC) calibration after G_RST. To do this it is necessary to gain access to the undocumented and currently unused PCIe PHY register bank. A new device tree node of type "fsl,imx7d-pcie-phy" is created for the PHY block and the existing PCIe device uses a phandle named "fsl,imx7d-pcie-phy" to point to it. Signed-off-by: Trent Piepho <[email protected]> [[email protected]: updated log string, commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]>
2019-02-12PCI: dwc: Print debug error message when MSI-X entry control mask bit is setGustavo Pimentel1-1/+3
Add debug error message when MSI-X entry control mask bit is set, to help debug the reason why a MSI-X interrupt is not being triggered. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Joao Pinto <[email protected]>
2019-02-04PCI: imx6: Add support for i.MX8MQAndrey Smirnov2-4/+77
Add code needed to support i.MX8MQ variant. Signed-off-by: Andrey Smirnov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Chris Healy <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Leonard Crestez <[email protected]> Cc: "A.s. Dong" <[email protected]> Cc: Richard Zhu <[email protected]>
2019-02-04PCI: imx6: Convert DIRECT_SPEED_CHANGE quirk code to use a flagAndrey Smirnov1-4/+9
Both i.MX7D and i.MX8MQ have the same behaviour when it comes to clearing DIRECT_SPEED_CHANGE bit when no speed change occurs, so to handle variants correctly add a flag instead of checking the IP block variant. Signed-off-by: Andrey Smirnov <[email protected]> [[email protected]: updated log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Chris Healy <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Leonard Crestez <[email protected]> Cc: "A.s. Dong" <[email protected]> Cc: Richard Zhu <[email protected]>
2019-02-04PCI: imx6: Mark PHY functions as i.MX6 specificAndrey Smirnov1-0/+12
PCIe PHY IP block on i.MX7D differs from the one used on i.MX6 family, so none of the code in the current implementation of imx6_setup_phy_mpll() or imx6_pcie_reset_phy() is applicable. Introduce IMX6_PCIE_FLAG_IMX6_PHY and check for it in the aforementioned functions to make sure they are only executed on appropriate PCIe IP variants. Tested-by: Trent Piepho <[email protected]> Signed-off-by: Andrey Smirnov <[email protected]> [[email protected]: updated log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Chris Healy <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Leonard Crestez <[email protected]> Cc: "A.s. Dong" <[email protected]> Cc: Richard Zhu <[email protected]>
2019-02-04PCI: imx6: Introduce drvdataAndrey Smirnov1-19/+37
Introduce driver data struct. This will simplify handling of device specific differences. Signed-off-by: Stefan Agner <[email protected]> [[email protected] reformatted drvdata, to simplify future diffs] Signed-off-by: Andrey Smirnov <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Chris Healy <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Leonard Crestez <[email protected]> Cc: "A.s. Dong" <[email protected]> Cc: Richard Zhu <[email protected]>
2019-02-01PCI: dwc: Replace bit rotation operation (1 << bit) with BIT(bit)Gustavo Pimentel1-3/+3
Replace bit rotation operation (1 << bit) with BIT(bit), which simplifies code reading. No functional change is intended. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Joao Pinto <[email protected]> Cc: Jingoo Han <[email protected]>
2019-02-01PCI: dwc: Improve code readability and simplify mask/unmask operationsGustavo Pimentel2-7/+7
Improve code readability and simplifies mask/unmask operations by inverting the applied logic (no functional change is intended). Replace variable name from irq_status to irq_mask, since its goal is to keep track of which interrupts are masked or not. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Joao Pinto <[email protected]> Cc: Jingoo Han <[email protected]>
2019-02-01PCI: dwc: Rename variable name from data to d on dw_pcie_irq_domain_free()Gustavo Pimentel1-3/+3
Rename variable from data to d to maintain consistency between driver functions. No functional change is intended. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Joao Pinto <[email protected]> Cc: Jingoo Han <[email protected]>
2019-02-01PCI: dwc: Rename variable name from data to d on dw_pci_msi_set_affinity()Gustavo Pimentel1-1/+1
Rename variable from data to d to maintain consistency between driver functions. No functional change is intended. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Joao Pinto <[email protected]> Cc: Jingoo Han <[email protected]>
2019-02-01PCI: dwc: Rename variable name from data to d on dw_pci_setup_msi_msg()Gustavo Pimentel1-5/+5
Rename variable from data to d to maintain consistency between driver functions, such as dw_pci_setup_msi_msg(). No functional change is intended. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Joao Pinto <[email protected]> Cc: Jingoo Han <[email protected]>
2019-02-01PCI: dwc: Rename variable name from data to d on dw_pci_bottom_mask/unmask()Gustavo Pimentel1-10/+10
Rename variable from data to d to maintain consistency between driver functions, such as dw_msi_mask_irq() and dw_msi_unmask_irq(). No functional change is intended. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Joao Pinto <[email protected]> Cc: Jingoo Han <[email protected]>
2019-02-01PCI: dwc: Remove unnecessary header include (signal.h)Gustavo Pimentel1-1/+0
Remove unnecessary header include (signal.h) since it doesn't provide any needed symbols. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Joao Pinto <[email protected]> Cc: Jingoo Han <[email protected]>
2019-02-01PCI: dwc: Remove unnecessary header include (of_gpio.h)Gustavo Pimentel1-1/+0
Remove unnecessary header include (of_gpio.h) since it doesn't provide any needed symbols. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Joao Pinto <[email protected]> Cc: Jingoo Han <[email protected]>
2019-01-31Revert "PCI: armada8k: Add support for gpio controlled reset signal"Baruch Siach1-16/+0
Revert commit 3d71746c42 ("PCI: armada8k: Add support for gpio controlled reset signal"). That commit breaks boot on Macchiatobin board when a Mellanox NIC is present in the PCIe slot. It turns out that full reset cycle requires first comphy serdes initialization. Reset signal toggle without comphy initialization makes access to PCI configuration registers stall indefinitely. U-Boot toggles the Macchiatobin PCIe reset line already at boot, after initializing the comphy serdes. So while commit 3d71746c42 ("PCI: armada8k: Add support for gpio controlled reset signal") enables PCIe on platforms that U-Boot does not touch the reset line (like Clearfog GT-8K), it breaks PCIe (and boot) on the Macchiatobin board. Revert commit 3d71746c42 ("PCI: armada8k: Add support for gpio controlled reset signal") entirely to fix the Macchiatobin regression. Reported-by: Sven Auhagen <[email protected]> Signed-off-by: Baruch Siach <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-01-31PCI: imx: Fix checking pd_pcie_phy device link additionLeonard Crestez1-4/+4
The check on the device_link_add() return value is wrong; this leads to erroneous code execution, so fix it. Fixes: 3f7cceeab895 ("PCI: imx: Add multi-pd support") Signed-off-by: Leonard Crestez <[email protected]> [[email protected]: updated commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-01-31PCI: imx: Fix probe failure without power domainLeonard Crestez1-0/+3
On chips without a separate power domain for PCI (such as 6q/6qp) the imx6_pcie_attach_pd() function incorrectly returns an error. Fix by returning 0 if dev_pm_domain_attach_by_name() does not find anything. Fixes: 3f7cceeab895 ("PCI: imx: Add multi-pd support") Reported-by: Lukas F.Hartmann <[email protected]> Signed-off-by: Leonard Crestez <[email protected]> [[email protected]: updated commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-01-31PCI: dwc: dra7xx: Invoke phy_set_mode() API to set PHY mode to PHY_MODE_PCIEKishon Vijay Abraham I1-0/+4
Certain PHYs used with PCIe controller can also be used with other controllers such as USB or SATA. In order to configure the PHY to work with PCIe controller, invoke phy_set_mode() API with mode set to PHY_MODE_PCIE. Signed-off-by: Kishon Vijay Abraham I <[email protected]> [[email protected]: updated commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-01-31PCI: dwc: dra7xx: Enable x2 mode support for dra74x, dra76x and dra72xKishon Vijay Abraham I1-0/+77
dra74x/dra76x and dra72x have separate compatible strings. Add support for these compatible strings in pci-dra7xx driver to perform syscon configurations required to get x2 mode working. Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2019-01-08PCI: amlogic: Fix build failure due to missing gpio headerCorentin Labbe1-0/+1
Building the driver when GPIOLIB=n is not selected is causing the following compilation failure: drivers/pci/controller/dwc/pci-meson.c: In function 'meson_pcie_assert_reset': drivers/pci/controller/dwc/pci-meson.c:290:2: error: implicit declaration of function 'gpiod_set_value_cansleep'; did you mean 'gpio_set_value_cansleep'? [-Werror=implicit-function-declaration] gpiod_set_value_cansleep(mp->reset_gpio, 0); ^~~~~~~~~~~~~~~~~~~~~~~~ gpio_set_value_cansleep drivers/pci/controller/dwc/pci-meson.c: In function 'meson_pcie_probe': drivers/pci/controller/dwc/pci-meson.c:540:19: error: implicit declaration of function 'devm_gpiod_get'; did you mean 'devm_gpio_free'? [-Werror=implicit-function-declaration] mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); ^~~~~~~~~~~~~~ devm_gpio_free drivers/pci/controller/dwc/pci-meson.c:540:48: error: 'GPIOD_OUT_LOW' undeclared (first use in this function); did you mean 'GPIOF_INIT_LOW'? mp->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); ^~~~~~~~~~~~~ GPIOF_INIT_LOW Add the missing linux/gpio/consumer.h header to fix it. Fixes: 9c0ef6d34fdb ("PCI: amlogic: Add the Amlogic Meson PCIe controller driver") Signed-off-by: Corentin Labbe <[email protected]> [[email protected]: commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2019-01-05Merge tag 'pci-v4.21-changes' of ↵Linus Torvalds12-34/+1265
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - Remove unused lists from ASPM pcie_link_state (Frederick Lawler) - Fix Broadcom CNB20LE host bridge unintended sign extension (Colin Ian King) - Expand Kconfig "PF" acronyms (Randy Dunlap) - Update MAINTAINERS for arch/x86/kernel/early-quirks.c (Bjorn Helgaas) - Add missing include to drivers/pci.h (Alexandru Gagniuc) - Override Synopsys USB 3.x HAPS device class so dwc3-haps can claim it instead of xhci (Thinh Nguyen) - Clean up P2PDMA documentation (Randy Dunlap) - Allow runtime PM even if driver doesn't supply callbacks (Jarkko Nikula) - Remove status check after submitting Switchtec MRPC Firmware Download commands to avoid Completion Timeouts (Kelvin Cao) - Set Switchtec coherent DMA mask to allow 64-bit DMA (Boris Glimcher) - Fix Switchtec SWITCHTEC_IOCTL_EVENT_IDX_ALL flag overwrite issue (Joey Zhang) - Enable write combining for Switchtec MRPC Input buffers (Kelvin Cao) - Add Switchtec MRPC DMA mode support (Wesley Sheng) - Skip VF scanning on powerpc, which does this in firmware (Sebastian Ott) - Add Amlogic Meson PCIe controller driver and DT bindings (Yue Wang) - Constify histb dw_pcie_host_ops structure (Julia Lawall) - Support multiple power domains for imx6 (Leonard Crestez) - Constify layerscape driver data (Stefan Agner) - Update imx6 Kconfig to allow imx6 PCIe in imx7 kernel (Trent Piepho) - Support armada8k GPIO reset (Baruch Siach) - Support suspend/resume support on imx6 (Leonard Crestez) - Don't hard-code DesignWare DBI/ATU offst (Stephen Warren) - Skip i.MX6 PHY setup on i.MX7D (Andrey Smirnov) - Remove Jianguo Sun from HiSilicon STB maintainers (Lorenzo Pieralisi) - Mask DesignWare interrupts instead of disabling them to avoid lost interrupts (Marc Zyngier) - Add locking when acking DesignWare interrupts (Marc Zyngier) - Ack DesignWare interrupts in the proper callbacks (Marc Zyngier) - Use devm resource parser in mediatek (Honghui Zhang) - Remove unused mediatek "num-lanes" DT property (Honghui Zhang) - Add UniPhier PCIe controller driver and DT bindings (Kunihiko Hayashi) - Enable MSI for imx6 downstream components (Richard Zhu) * tag 'pci-v4.21-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (40 commits) PCI: imx: Enable MSI from downstream components s390/pci: skip VF scanning PCI/IOV: Add flag so platforms can skip VF scanning PCI/IOV: Factor out sriov_add_vfs() PCI: uniphier: Add UniPhier PCIe host controller support dt-bindings: PCI: Add UniPhier PCIe host controller description PCI: amlogic: Add the Amlogic Meson PCIe controller driver dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller arm64: dts: mt7622: Remove un-used property for PCIe arm: dts: mt7623: Remove un-used property for PCIe dt-bindings: PCI: MediaTek: Remove un-used property PCI: mediatek: Remove un-used variant in struct mtk_pcie_port MAINTAINERS: Remove Jianguo Sun from HiSilicon STB DWC entry PCI: dwc: Don't hard-code DBI/ATU offset PCI: imx: Add imx6sx suspend/resume support PCI: armada8k: Add support for gpio controlled reset signal PCI: dwc: Adjust Kconfig to allow IMX6 PCIe host on IMX7 PCI: dwc: layerscape: Constify driver data PCI: imx: Add multi-pd support PCI: Override Synopsys USB 3.x HAPS device class ...
2019-01-02Merge branch 'pci/imx6'Bjorn Helgaas1-0/+10
- Enable MSI for imx6 downstream components (Richard Zhu) * pci/imx6: PCI: imx: Enable MSI from downstream components
2019-01-02Merge branch 'remotes/lorenzo/pci/uniphier'Bjorn Helgaas3-0/+482
- Add UniPhier PCIe controller driver and DT bindings (Kunihiko Hayashi) * remotes/lorenzo/pci/uniphier: PCI: uniphier: Add UniPhier PCIe host controller support dt-bindings: PCI: Add UniPhier PCIe host controller description # Conflicts: # drivers/pci/controller/dwc/Kconfig # drivers/pci/controller/dwc/Makefile
2019-01-02Merge branch 'remotes/lorenzo/pci/dwc-msi'Bjorn Helgaas1-13/+24
- Mask DesignWare interrupts instead of disabling them to avoid lost interrupts (Marc Zyngier) - Add locking when acking DesignWare interrupts (Marc Zyngier) - Ack DesignWare interrupts in the proper callbacks (Marc Zyngier) * remotes/lorenzo/pci/dwc-msi: PCI: dwc: Move interrupt acking into the proper callback PCI: dwc: Take lock when ACKing an interrupt PCI: dwc: Use interrupt masking instead of disabling
2019-01-02Merge branch 'remotes/lorenzo/pci/dwc'Bjorn Helgaas9-21/+146
- Constify histb dw_pcie_host_ops structure (Julia Lawall) - Support multiple power domains for imx6 (Leonard Crestez) - Constify layerscape driver data (Stefan Agner) - Update imx6 Kconfig to allow imx6 PCIe in imx7 kernel (Trent Piepho) - Support armada8k GPIO reset (Baruch Siach) - Support suspend/resume support on imx6 (Leonard Crestez) - Don't hard-code DesignWare DBI/ATU offst (Stephen Warren) - Skip i.MX6 PHY setup on i.MX7D (Andrey Smirnov) - Remove Jianguo Sun from HiSilicon STB maintainers (Lorenzo Pieralisi) * remotes/lorenzo/pci/dwc: MAINTAINERS: Remove Jianguo Sun from HiSilicon STB DWC entry PCI: dwc: Don't hard-code DBI/ATU offset PCI: imx: Add imx6sx suspend/resume support PCI: armada8k: Add support for gpio controlled reset signal PCI: dwc: Adjust Kconfig to allow IMX6 PCIe host on IMX7 PCI: dwc: layerscape: Constify driver data PCI: imx: Add multi-pd support dt-bindings: imx6q-pcie: Add multi-pd bindings for imx6sx PCI: histb: Constify dw_pcie_host_ops structure
2019-01-01PCI: imx: Enable MSI from downstream componentsRichard Zhu1-0/+10
The MSI Enable bit in the MSI Capability (PCIe r4.0, sec 7.7.1.2) controls whether a Function can request service using MSI. i.MX6 Root Ports implement the MSI Capability and may use MSI to request service for events like PME, hotplug, AER, etc. In addition, on i.MX6, the MSI Enable bit controls delivery of MSI interrupts from components below the Root Port. Prior to f3fdfc4ac3a2 ("PCI: Remove host driver Kconfig selection of CONFIG_PCIEPORTBUS"), enabling CONFIG_PCI_IMX6 automatically also enabled CONFIG_PCIEPORTBUS, and when portdrv claimed the Root Ports, it set the MSI Enable bit so it could use PME, hotplug, AER, etc. As a side effect, that also enabled delivery of MSI interrupts from downstream components. The imx6q-pcie driver itself does not depend on portdrv, so set MSI Enable in imx6q-pcie so MSI from downstream components works even if nobody uses MSI for the Root Port events. Fixes: f3fdfc4ac3a2 ("PCI: Remove host driver Kconfig selection of CONFIG_PCIEPORTBUS") Signed-off-by: Richard Zhu <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Tested-by: Sven Van Asbroeck <[email protected]> Tested-by: Trent Piepho <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]>
2018-12-19PCI: uniphier: Add UniPhier PCIe host controller supportKunihiko Hayashi3-0/+482
This introduces specific glue layer for UniPhier platform to support PCIe host controller that is based on the DesignWare PCIe core, and this driver supports Root Complex (host) mode. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2018-12-19PCI: amlogic: Add the Amlogic Meson PCIe controller driverYue Wang3-0/+603
The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. This patch adds the driver support for Meson PCIe controller. Link: https://lore.kernel.org/linux-pci/[email protected]/ Signed-off-by: Yue Wang <[email protected]> Signed-off-by: Hanjie Lin <[email protected]> [[email protected]: updated coding/comment style] Signed-off-by: Lorenzo Pieralisi <[email protected]>
2018-12-18PCI: dwc: Don't hard-code DBI/ATU offsetStephen Warren4-8/+35
The DWC PCIe core contains various separate register spaces: DBI, DBI2, ATU, DMA, etc. The relationship between the addresses of these register spaces is entirely determined by the implementation of the IP block, not by the IP block design itself. Hence, the DWC driver must not make assumptions that one register space can be accessed at a fixed offset from any other register space. To avoid such assumptions, introduce an explicit/separate register pointer for the ATU register space. In particular, the current assumption is not valid for NVIDIA's T194 SoC. The ATU register space is only used on systems that require unrolled ATU access. This property is detected at run-time for host controllers, and when this is detected, this patch provides a default value for atu_base that matches the previous assumption re: register layout. An alternative would be to update all drivers for HW that requires unrolled access to explicitly set atu_base. However, it's hard to tell which drivers would require atu_base to be set. The unrolled property is not detected for endpoint systems, and so any endpoint driver that requires unrolled access must explicitly set the iatu_unroll_enabled flag (none do at present), and so a check is added to require the driver to also set atu_base while at it. Signed-off-by: Stephen Warren <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Acked-by: Vidya Sagar <[email protected]>
2018-12-18PCI: imx: Add imx6sx suspend/resume supportLeonard Crestez1-5/+39
Enable PCI suspend/resume support on imx6sx SOCs. This is similar to imx7d with a few differences: * The PM_Turn_Off bit is exposed through an IOMUX GPR, like all other pcie control bits on 6sx. * The pcie_inbound_axi clk needs to be turned off in suspend. On resume it is restored via resume -> deassert_core_reset -> enable_ref_clk. Most of the resume logic is shared with the initial reset after probe. Signed-off-by: Leonard Crestez <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Andrey Smirnov <[email protected]> Acked-by: Lucas Stach <[email protected]>
2018-12-18PCI: armada8k: Add support for gpio controlled reset signalBaruch Siach1-0/+16
Add support for the gpio reset signal binding as described in the designware-pcie.txt DT binding document. Both the documented 'reset-gpio' property name and the more standard 'reset-gpios' name are supported. Signed-off-by: Baruch Siach <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Thomas Petazzoni <[email protected]>
2018-12-18PCI: dwc: Adjust Kconfig to allow IMX6 PCIe host on IMX7Trent Piepho1-2/+2
The IMX6 PCI-e host driver also supports the IMX7d. However, the Kconfig dependencies of the driver prevented it from being enabled unless the kernel was built with both IMX6 and IMX7 support. It works fine to build with only IMX7 support enabled therefore adjust the Kconfig entry to allow this configuration. Signed-off-by: Trent Piepho <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Cc: Andrey Smirnov <[email protected]>
2018-12-18PCI: dwc: layerscape: Constify driver dataStefan Agner1-5/+5
Constify driver data since they do not get changed at runtime. Signed-off-by: Stefan Agner <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2018-12-18PCI: imx: Add multi-pd supportLeonard Crestez1-0/+48
On some chips the PCIe and PCIE_PHY blocks are in separate power domains which can be power-gated independently. The PCI driver needs to handle this by keeping both domain active. This is intended for imx6sx where PCIe is in DISPLAY and PCIE_PHY in its own domain. Defining the DISPLAY domain requires a way for PCIe to keep it active or it will break when displays are off. The power-domains on imx6sx are meant to look like this: power-domains = <&pd_disp>, <&pd_pci>; power-domain-names = "pcie", "pcie_phy"; Signed-off-by: Leonard Crestez <[email protected]> [[email protected]: updated commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Ulf Hansson <[email protected]>
2018-12-11PCI: dwc: Move interrupt acking into the proper callbackMarc Zyngier1-6/+7
The write to the status register is really an ACK for the HW, and should be treated as such by the driver. Let's move it to the irq_ack() callback, which will prevent people from moving it around in order to paper over other bugs. Fixes: 8c934095fa2f ("PCI: dwc: Clear MSI interrupt status after it is handled, not before") Fixes: 7c5925afbc58 ("PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API") Link: https://lore.kernel.org/linux-pci/[email protected]/ Reported-by: Trent Piepho <[email protected]> Tested-by: Niklas Cassel <[email protected]> Tested-by: Gustavo Pimentel <[email protected]> Tested-by: Stanimir Varbanov <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> [[email protected]: updated commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: [email protected]
2018-12-11PCI: dwc: Take lock when ACKing an interruptMarc Zyngier1-0/+5
Bizarrely, there is no lock taken in the irq_ack() helper. This puts the ACK callback provided by a specific platform in a awkward situation where there is no synchronization that would be expected on other callback. Introduce the required lock, giving some level of uniformity among callbacks. Fixes: 7c5925afbc58 ("PCI: dwc: Move MSI IRQs allocation to IRQ domains hierarchical API") Link: https://lore.kernel.org/linux-pci/[email protected]/ Tested-by: Niklas Cassel <[email protected]> Tested-by: Gustavo Pimentel <[email protected]> Tested-by: Stanimir Varbanov <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> [[email protected]: updated commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: [email protected]
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