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path: root/drivers/pci/controller/dwc/pcie-qcom.c
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2020-10-21Merge branch 'remotes/lorenzo/pci/qcom'Bjorn Helgaas1-0/+13
- Make sure PCIe is reset before init to work around QSDK U-Boot issue (Ansuel Smith) - Set iproc affinity mask on MSI interrupts (Mark Tomlinson) * remotes/lorenzo/pci/qcom: PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0
2020-09-10PCI: dwc: Centralize link gen settingRob Herring1-11/+0
keystone would force gen2 if no DT property. Now it relies on the PCI_EXP_LNKCAP value. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Richard Zhu <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Stanimir Varbanov <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Pratyush Anand <[email protected]> Cc: Thierry Reding <[email protected]> Cc: Jonathan Hunter <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected]
2020-09-08PCI: dwc/qcom: Use common PCI register definitionsRob Herring1-10/+8
The QCom driver has its own defines for common PCI config space registers. It also hard codes the capability register offsets which are discoverable. Convert it to use the standard register definitions. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Stanimir Varbanov <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: [email protected]
2020-09-08PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init()Rob Herring1-3/+1
Move the IS_ENABLED(CONFIG_PCI_MSI) check into dw_pcie_msi_init() instead of duplicating it in all the drivers. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Richard Zhu <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: NXP Linux Team <[email protected]> Cc: Yue Wang <[email protected]> Cc: Kevin Hilman <[email protected]> Cc: Jesper Nilsson <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]> Cc: Xiaowei Song <[email protected]> Cc: Binghui Wang <[email protected]> Cc: Stanimir Varbanov <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Kunihiko Hayashi <[email protected]> Cc: Masahiro Yamada <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2020-09-07PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0Ansuel Smith1-0/+13
Qsdk U-Boot can incorrectly leave the PCIe interface in an undefined state if bootm command is used instead of bootipq. This is caused by the not deinit of PCIe when bootm is called. Reset the PCIe before init anyway to fix this U-Boot bug. Link: https://lore.kernel.org/r/[email protected] Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Cc: [email protected] # v4.19+
2020-08-05Merge branch 'remotes/lorenzo/pci/runtime-pm'Bjorn Helgaas1-4/+2
- Fix runtime power management imbalance for cadence, dra7xx, qcom, rcar (Dinghao Liu) * remotes/lorenzo/pci/runtime-pm: PCI: rcar: Fix runtime PM imbalance on error PCI: qcom: Fix runtime PM imbalance on error PCI: cadence: Fix runtime PM imbalance on error PCI: dwc: pci-dra7xx: Fix runtime PM imbalance on error
2020-07-17PCI: dwc: Convert to devm_platform_ioremap_resource_byname()Dejin Zheng1-4/+2
Use devm_platform_ioremap_resource_byname() to simplify the code since it contains platform_get_resource_byname() and devm_ioremap_resource() respectively. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dejin Zheng <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Gustavo Pimentel <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-07-07PCI: qcom: Replace define with standard valueAnsuel Smith1-10/+5
Lots of define are actually already defined in pci_regs.h, directly use the standard defines. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Support pci speed set for ipq806xSham Muthayyan1-0/+13
Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to some hardware limitations. Add support for speed setting defined by the max-link-speed binding. If not defined the max speed is set to GEN2 by default. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Sham Muthayyan <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Add ipq8064 rev2 variantAnsuel Smith1-1/+3
Ipq8064-v2 have tx term offset set to 0. Introduce this variant to permit different offset based on the revision. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Add support for tx term offset for rev 2.1.0Ansuel Smith1-1/+16
Add tx term offset support to pcie qcom driver need in some revision of the ipq806x SoC. Ipq8064 needs tx term offset set to 7. Link: https://lore.kernel.org/r/[email protected] Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected] # v4.5+
2020-07-07PCI: qcom: Define some PARF params needed for ipq8064 SoCAnsuel Smith1-0/+24
Set some specific value for Tx De-Emphasis, Tx Swing and Rx equalization needed on some ipq8064 based device (Netgear R7800 for example). Without this the system locks on kernel load. Link: https://lore.kernel.org/r/[email protected] Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected] # v4.5+
2020-07-07PCI: qcom: Use bulk clk api and assert on errorAnsuel Smith1-85/+46
Rework 2.1.0 revision to use bulk clk api and fix missing assert on reset_control_deassert error. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Add missing reset for ipq806xAnsuel Smith1-0/+12
Add missing ext reset used by ipq8064 SoC in PCIe qcom driver. Link: https://lore.kernel.org/r/[email protected] Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected] # v4.5+
2020-07-07PCI: qcom: Change duplicate PCI reset to phy resetAbhishek Sahu1-10/+8
The deinit issues reset_control_assert for PCI twice and does not contain phy reset. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abhishek Sahu <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Add missing ipq806x clocks in PCIe driverAnsuel Smith1-5/+33
Aux and Ref clk are missing in PCIe qcom driver. Add support for this optional clks for ipq8064/apq8064 SoC. Link: https://lore.kernel.org/r/[email protected] Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Sham Muthayyan <[email protected]> Signed-off-by: Ansuel Smith <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2020-07-07PCI: qcom: Fix runtime PM imbalance on errorDinghao Liu1-4/+2
pm_runtime_get_sync() increments the runtime PM usage counter even when it returns an error code, thus a matching decrement is needed on the error handling path to keep the counter balanced. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
2020-02-26PCI: qcom: Fix the fixup of PCI_VENDOR_ID_QCOMBjorn Andersson1-1/+7
There exists non-bridge PCIe devices with PCI_VENDOR_ID_QCOM, so limit the fixup to only affect the relevant PCIe bridges. Fixes: 322f03436692 ("PCI: qcom: Use default config space read function") Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected] # v5.2+
2020-01-10PCI: qcom: Add support for SDM845 PCIe controllerBjorn Andersson1-0/+150
The SDM845 has one Gen2 and one Gen3 controller, add support for these. Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Reviewed-by: Philipp Zabel <[email protected]> Reviewed-by: Andrew Murray <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2019-05-30PCI: qcom: Ensure that PERST is asserted for at least 100 msNiklas Cassel1-0/+2
Currently, there is only a 1 ms sleep after asserting PERST. Reading the datasheets for different endpoints, some require PERST to be asserted for 10 ms in order for the endpoint to perform a reset, others require it to be asserted for 50 ms. Several SoCs using this driver uses PCIe Mini Card, where we don't know what endpoint will be plugged in. The PCI Express Card Electromechanical Specification r2.0, section 2.2, "PERST# Signal" specifies: "On power up, the deassertion of PERST# is delayed 100 ms (TPVPERL) from the power rails achieving specified operating limits." Add a sleep of 100 ms before deasserting PERST, in order to ensure that we are compliant with the spec. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected] # 4.5+
2019-05-29PCI: qcom: Add QCS404 PCIe controller supportBjorn Andersson1-26/+38
The QCS404 platform contains a PCIe version 2.4.0 controller and a Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the IPQ4019, but this support touches clocks and resets related to the PHY as well and there's no upstream driver for the PHY. On QCS404 we must initialize the PHY, so a separate PHY driver is implemented to take care of this and the controller driver is updated to not require the PHY related resources. This is done by relying on the fact that operations in both the clock and reset framework are NOPs when passed NULL, so we can isolate this change to only the qcom_pcie_get_resources_2_4_0() function. For QCS404 we also need to enable the AHB (iface) clock, in order to access the register space of the controller, but as this is not part of the IPQ4019 DT binding this is only added for new users of the 2.4.0 controller. Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Niklas Cassel <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2019-05-29PCI: qcom: Use clk bulk API for 2.4.0 controllersBjorn Andersson1-37/+16
Before introducing the QCS404 platform, which uses the same PCIe controller as IPQ4019, migrate this to use the bulk clock API, in order to make the error paths slighly cleaner. Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Niklas Cassel <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2019-05-07PCI: qcom: Use default config space read functionMarc Gonzalez1-17/+6
Move the device class fudge to a proper fixup function, and remove qcom_pcie_rd_own_conf() which has become useless. dw_pcie_setup_rc() already did the right thing, but it's broken on older qcom chips, such as 8064. Signed-off-by: Marc Gonzalez <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2019-02-28PCI: qcom: Don't deassert reset GPIO during probeBjorn Andersson1-1/+1
Acquiring the reset GPIO low means that reset is being deasserted, this is followed almost immediately with qcom_pcie_host_init() asserting it, initializing it and then finally deasserting it again, for the link to come up. Some PCIe devices requires a minimum time between the initial deassert and subsequent reset cycles. In a platform that boots with the reset GPIO asserted this requirement is being violated by this deassert/assert pulse. Acquire the reset GPIO high to prevent this situation by matching the state to the subsequent asserted state. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Bjorn Andersson <[email protected]> [[email protected]: updated commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]> Cc: [email protected]
2018-09-18PCI: qcom: Fix error handling in runtime PM supportBjorn Andersson1-17/+39
The driver does not cope with the fact that probe can fail in a number of cases after enabling runtime PM on the device; this results in warnings about "Unbalanced pm_runtime_enable". Furthermore if probe fails after invoking qcom_pcie_host_init() the power-domain will be left referenced. As it is not possible for the error handling in qcom_pcie_host_init() to handle errors happening after returning from that function the pm_runtime_get_sync() is moved to qcom_pcie_probe() as well. Fixes: 854b69efbdd2 ("PCI: qcom: add runtime pm support to pcie_port") Signed-off-by: Bjorn Andersson <[email protected]> [[email protected]: updated commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2018-07-13PCI: qcom: Drop unnecessary root_bus_nr settingShawn Guo1-1/+0
Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Stanimir Varbanov <[email protected]>
2018-06-08PCI: Collect all native drivers under drivers/pci/controller/Shawn Lin1-0/+1299
Native PCI drivers for root complex devices were originally all in drivers/pci/host/. Some of these devices can also be operated in endpoint mode. Drivers for endpoint mode didn't seem to fit in the "host" directory, so we put both the root complex and endpoint drivers in per-device directories, e.g., drivers/pci/dwc/, drivers/pci/cadence/, etc. These per-device directories contain trivial Kconfig and Makefiles and clutter drivers/pci/. Make a new drivers/pci/controllers/ directory and collect all the device-specific drivers there. No functional change intended. Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Shawn Lin <[email protected]> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <[email protected]>
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