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path: root/drivers/pci/controller/dwc/pcie-designware-plat.c
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2018-07-19pci-epf-test/pci_endpoint_test: Add MSI-X supportGustavo Pimentel1-0/+1
Add MSI-X support and update driver documentation accordingly. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
2018-07-19PCI: dwc: Add legacy interrupt callback handlerGustavo Pimentel1-2/+1
Currently DesignWare IP does not handle legacy interrupts. Add a legacy interrupt callback handler. Signed-off-by: Gustavo Pimentel <[email protected]> [[email protected]: updated commit log] Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
2018-07-19PCI: dwc: Add MSI-X callbacks handlerGustavo Pimentel1-0/+2
Add PCIe config space capability search function. Add sysfs set/get interface to allow the change of EP MSI-X maximum number. Add EP MSI-X callback for triggering interruptions. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
2018-07-19PCI: Update xxx_pcie_ep_raise_irq() and pci_epc_raise_irq() signaturesGustavo Pimentel1-1/+1
Change {cdns, dra7xx, artpec6, dw, rockchip}_pcie_ep_raise_irq() and pci_epc_raise_irq() signature, namely the interrupt_num variable type from u8 to u16 to accommodate 2048 maximum MSI-X interrupts. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Alan Douglas <[email protected]> Acked-by: Shawn Lin <[email protected]> Acked-by: Jesper Nilsson <[email protected]> Acked-by: Joao Pinto <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
2018-07-19PCI: dwc: Fix EP link notification implementationGustavo Pimentel1-0/+3
Move specific features settings from EP shared code (pcie-designware-ep.c) to the driver (pcie-designware-plat.c). Previous implementation disables the EP link notification by default for all SoCs that uses EP DesignWare IP, which affects directly the dra7xx and artpec6 SoCs. Signed-off-by: Gustavo Pimentel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Kishon Vijay Abraham I <[email protected]>
2018-07-13PCI: designware-plat: Drop unnecessary root_bus_nr settingShawn Guo1-1/+0
Function dw_pcie_host_init() already initializes the root_bus_nr field of 'struct pcie_port', so the -1 assignment prior to calling dw_pcie_host_init() in platform specific driver is not really needed. Drop it. Signed-off-by: Shawn Guo <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Gustavo Pimentel <[email protected]> Cc: Joao Pinto <[email protected]>
2018-06-08PCI: Collect all native drivers under drivers/pci/controller/Shawn Lin1-0/+259
Native PCI drivers for root complex devices were originally all in drivers/pci/host/. Some of these devices can also be operated in endpoint mode. Drivers for endpoint mode didn't seem to fit in the "host" directory, so we put both the root complex and endpoint drivers in per-device directories, e.g., drivers/pci/dwc/, drivers/pci/cadence/, etc. These per-device directories contain trivial Kconfig and Makefiles and clutter drivers/pci/. Make a new drivers/pci/controllers/ directory and collect all the device-specific drivers there. No functional change intended. Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Shawn Lin <[email protected]> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <[email protected]>
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