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path: root/drivers/pci/controller/dwc/pcie-al.c
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2020-09-08PCI: dwc: Remove storing of PCI resourcesRob Herring1-3/+4
The PCI bridge resources are stored in pci_host_bridge.windows, so there's no need to store them in a DWC specific struct. There's also no need to parse the resources and store them a 2nd time as they are mainly used for one time setup of iATU windows. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Murali Karicheri <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: Jonathan Chocron <[email protected]> Cc: Jingoo Han <[email protected]> Cc: Gustavo Pimentel <[email protected]>
2020-09-08PCI: dwc: al: Use pci_ops for child config space accessorsRob Herring1-50/+13
Now that DWC drivers can setup their own pci_ops for the root and child buses, convert the Amazon driver to use the standard pci_ops for child bus config accesses. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Cc: Jonathan Chocron <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Bjorn Helgaas <[email protected]>
2020-07-23PCI: controller: Remove duplicate error messageDejin Zheng1-10/+3
devm_pci_remap_cfg_resource() will print an error message by itself when goes wrong, so remove the duplicate error message. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dejin Zheng <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Rob Herring <[email protected]>
2020-05-01PCI: Constify struct pci_ecam_opsRob Herring1-1/+1
struct pci_ecam_ops is typically DT match table data which is defined to be const. It's also best practice for ops structs to be const. Ideally, we'd make struct pci_ops const as well, but that becomes pretty invasive, so for now we just cast it where needed. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Acked-by: Catalin Marinas <[email protected]> Cc: Catalin Marinas <[email protected]> Cc: Will Deacon <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Cc: Andrew Murray <[email protected]> Cc: Bjorn Helgaas <[email protected]> Cc: "Rafael J. Wysocki" <[email protected]> Cc: Len Brown <[email protected]> Cc: Jonathan Chocron <[email protected]> Cc: Zhou Wang <[email protected]> Cc: Robert Richter <[email protected]> Cc: Toan Le <[email protected]> Cc: Marc Gonzalez <[email protected]> Cc: Mans Rullgard <[email protected]> Cc: [email protected]
2019-09-16PCI: dwc: al: Add Amazon Annapurna Labs PCIe controller driverJonathan Chocron1-0/+365
This driver is DT based and utilizes the DesignWare APIs. It allows using a smaller ECAM range for a larger bus range - usually an entire bus uses 1MB of address space, but the driver can use it for a larger number of buses. This is achieved by using a HW mechanism which allows changing the BUS part of the "final" outgoing config transaction. There are 2 HW regs, one which is basically a bitmask determining which bits to take from the AXI transaction itself and another which holds the complementary part programmed by the driver. All link initializations are handled by the boot FW. Signed-off-by: Jonathan Chocron <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Reviewed-by: Gustavo Pimentel <[email protected]> Reviewed-by: Andrew Murray <[email protected]>
2019-04-25PCI: al: Add Amazon Annapurna Labs PCIe host controller driverJonathan Chocron1-0/+93
Add driver for Amazon's Annapurna Labs PCIe host controller. The controller is based on DesignWare's IP. The controller doesn't support accessing the Root Port's config space via ECAM, so we obtain its base address via an AMZN0001 device. Furthermore, the DesignWare PCIe controller doesn't filter out config transactions sent to devices 1 and up on its bus, so they are filtered by the driver. All subordinate buses do support ECAM access. Implementing specific PCI config access functions involves: - Adding an init function to obtain the Root Port's base address from an AMZN0001 device. - Adding a new entry in the MCFG quirk array. [bhelgaas: Note that there is no Kconfig option for this driver because it is only intended for use with the generic ACPI host bridge driver. This driver is only needed because the DesignWare IP doesn't completely support ECAM access to the root bus.] Link: https://lore.kernel.org/lkml/[email protected] Co-developed-by: Vladimir Aerov <[email protected]> Signed-off-by: Jonathan Chocron <[email protected]> Signed-off-by: Vladimir Aerov <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: David Woodhouse <[email protected]> Reviewed-by: Benjamin Herrenschmidt <[email protected]> Acked-by: Lorenzo Pieralisi <[email protected]>