aboutsummaryrefslogtreecommitdiff
path: root/drivers/pci/access.c
AgeCommit message (Collapse)AuthorFilesLines
2020-08-05Merge branch 'pci/misc'Bjorn Helgaas1-4/+4
- Convert PCIe capability PCIBIOS errors to errno (Bolarinwa Olayemi Saheed) - Align PCIe capability and PCI accessor return values (Bolarinwa Olayemi Saheed) - Replace http:// links with https:// (Alexander A. Klimov) - Replace lkml.org, spinics, gmane with lore.kernel.org (Bjorn Helgaas) - Update panic message to mention kzalloc(), not kmalloc() (Liao Pingfang) - Move PCI_VENDOR_ID_REDHAT definition to pci_ids.h (Huacai Chen) - Remove unused pci_lost_interrupt() (Heiner Kallweit) * pci/misc: PCI: Remove unused pci_lost_interrupt() PCI: Move PCI_VENDOR_ID_REDHAT definition to pci_ids.h PCI: Fix error in panic message PCI: Replace lkml.org, spinics, gmane with lore.kernel.org PCI: Replace http:// links with https:// PCI: Align PCIe capability and PCI accessor return values PCI: Convert PCIe capability PCIBIOS errors to errno
2020-07-07PCI: Fix pci_cfg_wait queue locking problemBjorn Helgaas1-6/+2
The pci_cfg_wait queue is used to prevent user-space config accesses to devices while they are recovering from reset. Previously we used these operations on pci_cfg_wait: __add_wait_queue(&pci_cfg_wait, ...) __remove_wait_queue(&pci_cfg_wait, ...) wake_up_all(&pci_cfg_wait) The wake_up acquires the wait queue lock, but the add and remove do not. Originally these were all protected by the pci_lock, but cdcb33f98244 ("PCI: Avoid possible deadlock on pci_lock and p->pi_lock"), moved wake_up_all() outside pci_lock, so it could race with add/remove operations, which caused occasional kernel panics, e.g., during vfio-pci hotplug/unplug testing: Unable to handle kernel read from unreadable memory at virtual address ffff802dac469000 Resolve this by using wait_event() instead of __add_wait_queue() and __remove_wait_queue(). The wait queue lock is held by both wait_event() and wake_up_all(), so it provides mutual exclusion. Fixes: cdcb33f98244 ("PCI: Avoid possible deadlock on pci_lock and p->pi_lock") Link: https://lore.kernel.org/linux-pci/[email protected]/T/#u Based-on: https://lore.kernel.org/linux-pci/[email protected]/ Based-on-patch-by: Xiang Zheng <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Tested-by: Xiang Zheng <[email protected]> Cc: Heyi Guo <[email protected]> Cc: Biaoxiang Ye <[email protected]>
2020-06-26PCI: Align PCIe capability and PCI accessor return valuesBolarinwa Olayemi Saheed1-4/+4
The PCI config accessors (pci_read_config_word(), et al) return PCIBIOS_SUCCESSFUL (zero) or positive error values like PCIBIOS_FUNC_NOT_SUPPORTED. The PCIe capability accessors similarly return PCIBIOS errors, but in addition, they can return -EINVAL. This makes it harder than it should be to check for errors. Return PCIBIOS_BAD_REGISTER_NUMBER instead of -EINVAL in all PCIe capability accessors. Suggested-by: Bjorn Helgaas <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bolarinwa Olayemi Saheed <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2019-10-18PCI/AER: Save AER Capability for suspend/resumePatel, Mayurkumar1-1/+1
Previously we did not save and restore the AER configuration on suspend/resume, so the configuration may be lost after resume. Save the AER configuration during suspend and restore it during resume. [bhelgaas: commit log] Link: https://lore.kernel.org/r/92EBB4272BF81E4089A7126EC1E7B28492C3B007@IRSMSX101.ger.corp.intel.com Signed-off-by: Mayurkumar Patel <[email protected]> Signed-off-by: Kuppuswamy Sathyanarayanan <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]>
2019-09-07PCI: Make pcie_downstream_port() available outside of access.cMika Westerberg1-9/+0
pcie_downstream_port() is useful in other places where code needs to determine whether the PCIe port is downstream so make it available outside of access.c. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mika Westerberg <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]>
2018-10-04PCI: Uninline PCI bus accessors for better ftracingKeith Busch1-2/+2
The PCI bus config accessors could be inlined into other accessor functions, which makes it so they can't be traced. Force them to never be inlined so that ftrace can hook into these functions. Signed-off-by: Keith Busch <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2018-04-04Merge branch 'pci/vpd'Bjorn Helgaas1-368/+0
- consolidate VPD code in vpd.c (Bjorn Helgaas) * pci/vpd: PCI/VPD: Move VPD structures to vpd.c PCI/VPD: Move VPD quirks to vpd.c PCI/VPD: Move VPD sysfs code to vpd.c PCI/VPD: Move VPD access code to vpd.c
2018-03-19PCI: Tidy commentsBjorn Helgaas1-5/+7
Remove pointless comments that tell us the file name, remove blank line comments, follow multi-line comment conventions. No functional change intended. Signed-off-by: Bjorn Helgaas <[email protected]>
2018-03-19PCI/VPD: Move VPD access code to vpd.cBjorn Helgaas1-368/+0
Move the VPD-related code from access.c to vpd.c. The goal is to encapsulate all the VPD code and structures in vpd.c. No functional change intended. Signed-off-by: Bjorn Helgaas <[email protected]>
2018-02-01Merge branch 'pci/spdx' into nextBjorn Helgaas1-0/+1
* pci/spdx: PCI: Add SPDX GPL-2.0+ to replace implicit GPL v2 or later statement PCI: Add SPDX GPL-2.0+ to replace GPL v2 or later boilerplate PCI: Add SPDX GPL-2.0 to replace COPYING boilerplate PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate PCI: Add SPDX GPL-2.0 when no license was specified
2018-01-26PCI: Add SPDX GPL-2.0 when no license was specifiedBjorn Helgaas1-0/+1
b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") added SPDX GPL-2.0 to several PCI files that previously contained no license information. Add SPDX GPL-2.0 to all other PCI files that did not contain any license information and hence were under the default GPL version 2 license of the kernel. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Greg Kroah-Hartman <[email protected]>
2018-01-18PCI: Add wrappers for dev_printk()Frederick Lawler1-5/+3
Add PCI-specific dev_printk() wrappers and use them to simplify the code slightly. No functional change intended. Signed-off-by: Frederick Lawler <[email protected]> [bhelgaas: squash into one patch] Signed-off-by: Bjorn Helgaas <[email protected]>
2017-06-28PCI: Provide Kconfig option for lockless config space accessorsThomas Gleixner1-4/+12
The generic PCI configuration space accessors are globally serialized via pci_lock. On larger systems this causes massive lock contention when the configuration space has to be accessed frequently. One such access pattern is the Intel Uncore performance counter unit. Provide a kernel config option which can be selected by an architecture when the low level PCI configuration space accessors in the architecture use their own serialization or can operate completely lockless. Signed-off-by: Thomas Gleixner <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> Cc: Andi Kleen <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Stephane Eranian <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: [email protected] Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2017-05-26PCI: Make error code types consistent in pci_{read,write}_config_*Brian Norris1-6/+6
Callers normally treat the config space accessors as returning PCBIOS_* error codes, not Linux error codes (or they don't look at them at all). We have pcibios_err_to_errno() in case the error code needs to be translated. Fixes: 4b1038834739 ("PCI: Don't attempt config access to disconnected devices") Signed-off-by: Brian Norris <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Keith Busch <[email protected]>
2017-04-28Merge branch 'pci/misc' into nextBjorn Helgaas1-1/+1
* pci/misc: PCI: Change pci_host_common_probe() visibility PCI: Fix typo pci_cfg_access_lock() comment PCI: Include pci.h for struct pci_ops definition
2017-04-19PCI: Include PCI-to-PCIe bridges as "Downstream Ports"Bjorn Helgaas1-1/+2
A PCI/PCI-X to PCI Express bridge, sometimes referred to as a "reverse bridge", is a bridge with conventional PCI or PCI-X on its primary side and a PCI Express Port on its secondary (downstream) side. That PCIe Port is a Downstream Port and could be connected to a slot, just like a Root Port or a Switch Downstream Port. Make pcie_downstream_port() return true for them, so we can access the Slot registers in the PCIe capability. Signed-off-by: Bjorn Helgaas <[email protected]>
2017-04-04PCI: Fix typo pci_cfg_access_lock() commentBrian Norris1-1/+1
There is no pci_cfg_access_unlocked(). I think the author meant pci_cfg_access_unlock(). Signed-off-by: Brian Norris <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2017-03-29PCI: Don't attempt config access to disconnected devicesKeith Busch1-0/+18
If we've detected the PCI device is disconnected, there is no need to attempt to access its config space since we know the operation will fail. Make all the config reads and writes return -ENODEV error immediately when in such a state. If a caller requests a config read to a disconnected device, return a data value of all 1's. This is the same as what hardware is expected to return when accessing a removed device, but software can do this faster without relying on hardware. Tested-by: Krishna Dhulipala <[email protected]> Signed-off-by: Keith Busch <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Christoph Hellwig <[email protected]> Reviewed-by: Wei Zhang <[email protected]>
2017-03-29PCI: Export PCI device config accessorsKeith Busch1-0/+38
Replace the inline PCI device config read and write accessors with exported functions. This is preparing for these functions to make use of private data. Tested-by: Krishna Dhulipala <[email protected]> Signed-off-by: Keith Busch <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Christoph Hellwig <[email protected]> Reviewed-by: Wei Zhang <[email protected]>
2017-03-02sched/headers: Prepare to move signal wakeup & sigpending methods from ↵Ingo Molnar1-1/+1
<linux/sched.h> into <linux/sched/signal.h> Fix up affected files that include this signal functionality via sched.h. Acked-by: Linus Torvalds <[email protected]> Cc: Mike Galbraith <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Cc: [email protected] Signed-off-by: Ingo Molnar <[email protected]>
2017-02-15Merge branch 'pci/vpd' into nextBjorn Helgaas1-1/+1
* pci/vpd: PCI: Increase VPD access timeout to 125ms
2017-02-03PCI: Increase VPD access timeout to 125msMatthew R. Ochs1-1/+1
The PCI core uses a fixed 50ms timeout when waiting for VPD accesses to complete. When an access does not complete within this period, a warning is logged and an error returned to the caller. While this default timeout is valid for most hardware, some devices can experience longer access delays under certain circumstances. For example, one of the IBM CXL Flash devices can take up to ~120ms in a worst-case scenario. These types of devices can benefit from an extended timeout. To support devices with a longer access delay, increase the timeout in pci_vpd_wait() to 125ms. The PCI specification is silent with respect to VPD delays, therefore there is no concern for violating a threshold. Tested-by: Uma Krishnan <[email protected]> Signed-off-by: Matthew R. Ochs <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Gavin Shan <[email protected]>
2017-01-30PCI: Avoid possible deadlock on pci_lock and p->pi_lockBjorn Helgaas1-1/+2
pci_lock is an IRQ-safe spinlock that protects all accesses to PCI configuration space (see PCI_OP_READ() and PCI_OP_WRITE() in pci/access.c). The pci_cfg_access_unlock() path acquires pci_lock, then p->pi_lock (inside wake_up_all()). According to lockdep, there is a possible path involving snbep_uncore_pci_read_counter() that could acquire them in the reverse order: acquiring p->pi_lock, then pci_lock, which could result in a deadlock. Lockdep details are in the bugzilla below. Avoid the possible deadlock by dropping pci_lock before waking up any config access waiters. Link: https://bugzilla.kernel.org/show_bug.cgi?id=192901 Signed-off-by: Bjorn Helgaas <[email protected]>
2016-11-21PCI: Warn on possible RW1C corruption for sub-32 bit config writesBjorn Helgaas1-2/+14
Hardware that supports only 32-bit config writes is not spec-compliant. For example, if software performs a 16-bit write, we must do a 32-bit read, merge in the 16 bits we intend to write, followed by a 32-bit write. If the 16 bits we *don't* intend to write happen to have any RW1C (write-one- to-clear) bits set, we just inadvertently cleared something we shouldn't have. Add a rate-limited warning when we do sub-32 bit config writes. Remove similar probe-time warnings from some of the affected host bridge drivers. Signed-off-by: Bjorn Helgaas <[email protected]> Enthusiastically-Acked-by: Russell King <[email protected]> Acked-by: Shawn Lin <[email protected]> # rockchip Acked-by: Thierry Reding <[email protected]>
2016-04-15PCI: Add pci_set_vpd_size() to set VPD sizeHariprasad Shenai1-0/+42
After 104daa71b396 ("PCI: Determine actual VPD size on first access"), the PCI core computes the valid VPD size by parsing the VPD starting at offset 0x0. We don't attempt to read past that valid size because that causes some devices to crash. However, some devices do have data past that valid size. For example, Chelsio adapters contain two VPD structures, and the driver needs both of them. Add pci_set_vpd_size(). If a driver knows it is safe to read past the end of the VPD data structure at offset 0, it can use pci_set_vpd_size() to allow access to as much data as it needs. [bhelgaas: changelog, split patches, rename to pci_set_vpd_size() and return int (not ssize_t)] Fixes: 104daa71b396 ("PCI: Determine actual VPD size on first access") Tested-by: Steve Wise <[email protected]> Signed-off-by: Casey Leedom <[email protected]> Signed-off-by: Hariprasad Shenai <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2016-03-10PCI: Sleep rather than busy-wait for VPD access completionBjorn Helgaas1-8/+10
Use usleep_range() instead of udelay() while waiting for a VPD access to complete. This is not a performance path, so no need to hog the CPU. Rationale for usleep_range() parameters: We clear PCI_VPD_ADDR_F for a read (or set it for a write), then wait for the device to change it. For a device that updates PCI_VPD_ADDR between our config write and subsequent config read, we won't sleep at all and can get the device's maximum rate. Sleeping a minimum of 10 usec per 4-byte access limits throughput to about 400Kbytes/second. VPD is small (32K bytes at most), and most devices use only a fraction of that. We back off exponentially up to 1024 usec per iteration. If we reach 1024, we've already waited up to 1008 usec (16 + 32 + ... + 512), so if we miss an update and wait an extra 1024 usec, we can still get about 1/2 of the device's maximum rate. Tested-by: Shane Seymour <[email protected]> Tested-by: Babu Moger <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Hannes Reinecke <[email protected]>
2016-02-29PCI: Fold struct pci_vpd_pci22 into struct pci_vpdBjorn Helgaas1-30/+17
We only support one flavor of VPD, so there's no need to complicate things by having a "generic" struct pci_vpd and a more specific struct pci_vpd_pci22. Fold struct pci_vpd_pci22 directly into struct pci_vpd. [bhelgaas: remove NULL check before kfree of dev->vpd (per kfreeaddr.cocci)] Tested-by: Shane Seymour <[email protected]> Tested-by: Babu Moger <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Hannes Reinecke <[email protected]>
2016-02-29PCI: Rename VPD symbols to remove unnecessary "pci22"Bjorn Helgaas1-19/+19
There's only one kind of VPD, so we don't need to qualify it as "the version described by PCI spec rev 2.2." Rename the following symbols to remove unnecessary "pci22": PCI_VPD_PCI22_SIZE -> PCI_VPD_MAX_SIZE pci_vpd_pci22_size() -> pci_vpd_size() pci_vpd_pci22_wait() -> pci_vpd_wait() pci_vpd_pci22_read() -> pci_vpd_read() pci_vpd_pci22_write() -> pci_vpd_write() pci_vpd_pci22_ops -> pci_vpd_ops pci_vpd_pci22_init() -> pci_vpd_init() Tested-by: Shane Seymour <[email protected]> Tested-by: Babu Moger <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Hannes Reinecke <[email protected]>
2016-02-29PCI: Remove struct pci_vpd_ops.release function pointerBjorn Helgaas1-8/+1
The struct pci_vpd_ops.release function pointer is always pci_vpd_pci22_release(), so there's no need for the flexibility of a function pointer. Inline the pci_vpd_pci22_release() body into pci_vpd_release() and remove pci_vpd_pci22_release() and the struct pci_vpd_ops.release function pointer. Tested-by: Shane Seymour <[email protected]> Tested-by: Babu Moger <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Hannes Reinecke <[email protected]>
2016-02-29PCI: Move pci_vpd_release() from header file to pci/access.cBjorn Helgaas1-0/+6
Move pci_vpd_release() so it's next to the other VPD functions. This puts it next to pci_vpd_pci22_init(), which allocates the space freed by pci_vpd_release(). Tested-by: Shane Seymour <[email protected]> Tested-by: Babu Moger <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Hannes Reinecke <[email protected]>
2016-02-29PCI: Move pci_read_vpd() and pci_write_vpd() close to other VPD codeBjorn Helgaas1-32/+30
pci_read_vpd() and pci_write_vpd() were stranded in the middle of config accessor functions. Move them close to the other VPD code in the file. No functional change. Tested-by: Shane Seymour <[email protected]> Tested-by: Babu Moger <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Hannes Reinecke <[email protected]>
2016-02-29PCI: Determine actual VPD size on first accessHannes Reinecke1-2/+85
PCI-2.2 VPD entries have a maximum size of 32k, but might actually be smaller than that. To figure out the actual size one has to read the VPD area until the 'end marker' is reached. Per spec, reading outside of the VPD space is "not allowed." In practice, it may cause simple read errors or even crash the card. To make matters worse not every PCI card implements this properly, leaving us with no 'end' marker or even completely invalid data. Try to determine the size of the VPD data when it's first accessed. If no valid data can be read an I/O error will be returned when reading or writing the sysfs attribute. As the amount of VPD data is unknown initially the size of the sysfs attribute will always be set to '0'. [bhelgaas: changelog, use 0/1 (not false/true) for bitfield, tweak pci_vpd_pci22_read() error checking] Tested-by: Shane Seymour <[email protected]> Tested-by: Babu Moger <[email protected]> Signed-off-by: Hannes Reinecke <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Cc: Alexander Duyck <[email protected]>
2016-02-29PCI: Use bitfield instead of bool for struct pci_vpd_pci22.busyBjorn Helgaas1-5/+5
Make struct pci_vpd_pci22.busy a 1-bit field instead of a bool. We intend to add another flag, and two bitfields are cheaper than two bools. Tested-by: Shane Seymour <[email protected]> Tested-by: Babu Moger <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Hannes Reinecke <[email protected]>
2016-01-08PCI: Fix all whitespace issuesBogicevic Sasa1-4/+4
Fix all whitespace issues (missing or needed whitespace) in all files in drivers/pci. Code is compiled with allyesconfig before and after code changes and objects are recorded and checked with objdiff and they are not changed after this commit. Signed-off-by: Bogicevic Sasa <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2015-09-24PCI: Use function 0 VPD for identical functions, regular VPD for othersAlex Williamson1-22/+0
932c435caba8 ("PCI: Add dev_flags bit to access VPD through function 0") added PCI_DEV_FLAGS_VPD_REF_F0. Previously, we set the flag on every non-zero function of quirked devices. If a function turned out to be different from function 0, i.e., it had a different class, vendor ID, or device ID, the flag remained set but we didn't make VPD accessible at all. Flip this around so we only set PCI_DEV_FLAGS_VPD_REF_F0 for functions that are identical to function 0, and allow regular VPD access for any other functions. [bhelgaas: changelog, stable tag] Fixes: 932c435caba8 ("PCI: Add dev_flags bit to access VPD through function 0") Signed-off-by: Alex Williamson <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Myron Stowe <[email protected]> Acked-by: Mark Rustad <[email protected]> CC: [email protected]
2015-09-24PCI: Fix devfn for VPD access through function 0Alex Williamson1-3/+6
Commit 932c435caba8 ("PCI: Add dev_flags bit to access VPD through function 0") passes PCI_SLOT(devfn) for the devfn parameter of pci_get_slot(). Generally this works because we're fairly well guaranteed that a PCIe device is at slot address 0, but for the general case, including conventional PCI, it's incorrect. We need to get the slot and then convert it back into a devfn. Fixes: 932c435caba8 ("PCI: Add dev_flags bit to access VPD through function 0") Signed-off-by: Alex Williamson <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Myron Stowe <[email protected]> Acked-by: Mark Rustad <[email protected]> CC: [email protected]
2015-07-21PCI: Add dev_flags bit to access VPD through function 0Mark Rustad1-1/+60
Add a dev_flags bit, PCI_DEV_FLAGS_VPD_REF_F0, to access VPD through function 0 to provide VPD access on other functions. This is for hardware devices that provide copies of the same VPD capability registers in multiple functions. Because the kernel expects that each function has its own registers, both the locking and the state tracking are affected by VPD accesses to different functions. On such devices for example, if a VPD write is performed on function 0, *any* later attempt to read VPD from any other function of that device will hang. This has to do with how the kernel tracks the expected value of the F bit per function. Concurrent accesses to different functions of the same device can not only hang but also corrupt both read and write VPD data. When hangs occur, typically the error message: vpd r/w failed. This is likely a firmware bug on this device. will be seen. Never set this bit on function 0 or there will be an infinite recursion. Signed-off-by: Mark Rustad <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Alexander Duyck <[email protected]> CC: [email protected]
2015-07-14PCI: Add pcie_downstream_port() (true for Root and Switch Downstream Ports)Bjorn Helgaas1-10/+13
As used in the PCIe spec, "Downstream Port" includes both Root Ports and Switch Downstream Ports. We sometimes checked for PCI_EXP_TYPE_DOWNSTREAM when we should have checked for PCI_EXP_TYPE_ROOT_PORT or PCI_EXP_TYPE_DOWNSTREAM. For a Root Port without a slot, the effect of this was that using pcie_capability_read_word() to read PCI_EXP_SLTSTA returned zero instead of showing the Presence Detect State bit hardwired to one as the PCIe Spec, r3.0, sec 7.8, requires. (This read is completed in software because previous PCIe spec versions didn't require PCI_EXP_SLTSTA to exist at all.) Nothing in the kernel currently depends on this (pciehp only reads PCI_EXP_SLTSTA on ports with slots), so this is a cleanup and not a functional change. Add a pcie_downstream_port() helper function and use it. Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Rafael J. Wysocki <[email protected]>
2015-01-22PCI: Add generic config accessorsRob Herring1-0/+87
Many PCI controllers' configuration space accesses are memory-mapped and vary only in address calculation and access checks. There are 2 main access methods: a decoded address space such as ECAM or a single address and data register similar to x86. This implementation can support both cases as well as be used in cases that need additional pre- or post-access handling. Add a new pci_ops member, map_bus, which can do access checks and any necessary setup. It returns the address to use for the configuration space access. The access types supported are 32-bit only accesses or correct byte, word, or dword sized accesses. Tested-by: Thierry Reding <[email protected]> Signed-off-by: Rob Herring <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-by: Thierry Reding <[email protected]>
2014-11-13PCI: Apply _HPX Link Control settings to all devices with a linkYinghai Lu1-1/+1
Previously we applied _HPX type 2 record Link Control register settings only to bridges with a subordinate bus. But it's better to apply them to all devices with a link because if the subordinate bus has not been allocated yet, we won't apply settings to the device. Use pcie_cap_has_lnkctl() to determine whether the device has a Link Control register instead of looking at dev->subordinate. [bhelgaas: changelog] Fixes: 6cd33649fa83 ("PCI: Add pci_configure_device() during enumeration") Signed-off-by: Yinghai Lu <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2014-06-10PCI: Merge multi-line quoted stringsRyan Desfosses1-4/+1
Merge quoted strings that are broken across lines into a single entity. The compiler merges them anyway, but checkpatch complains about it, and merging them makes it easier to grep for strings. No functional change. [bhelgaas: changelog, do the same for everything under drivers/pci] Signed-off-by: Ryan Desfosses <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2014-05-27PCI: Fix return value from pci_user_{read,write}_config_*()Gavin Shan1-8/+4
The PCI user-space config accessors pci_user_{read,write}_config_*() return negative error numbers, which were introduced by commit 34e3207205ef ("PCI: handle positive error codes"). That patch converted all positive error numbers from platform-specific PCI config accessors to -EINVAL, which means the callers don't know anything about the specific cause of the failure. The patch fixes the issue by converting the positive PCIBIOS_* error values to generic negative error numbers with pcibios_err_to_errno(). [bhelgaas: changelog] Signed-off-by: Gavin Shan <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Greg Thelen <[email protected]>
2014-01-13PCI: Remove unused pci_vpd_truncate()Stephen Hemminger1-24/+0
My philosophy is unused code is dead code. And dead code is subject to bit rot and is a likely source of bugs. Use it or lose it. This reverts db5679437a2b ("PCI: add interface to set visible size of VPD"), removing this interface: pci_vpd_truncate() [bhelgaas: split to separate patch, also remove prototype from pci.h] Signed-off-by: Stephen Hemminger <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2013-08-28PCI: Remove pcie_cap_has_devctl()Bjorn Helgaas1-6/+1
pcie_cap_has_devctl() does nothing, so remove it. Simplicity over consistency in this case. No functional change. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-By: Jiang Liu <[email protected]>
2013-08-28PCI: Support PCIe Capability Slot registers only for ports with slotsBjorn Helgaas1-3/+3
Previously we allowed callers to access Slot Capabilities, Status, and Control for Root Ports even if the Root Port did not implement a slot. This seems dubious because the spec only requires these registers if a slot is implemented. It's true that even Root Ports without slots must have *space* for these slot registers, because the Root Capabilities, Status, and Control registers are after the slot registers in the capability. However, for a v1 PCIe Capability, the *semantics* of the slot registers are undefined unless a slot is implemented. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-By: Jiang Liu <[email protected]>
2013-08-28PCI: Remove PCIe Capability version checksBjorn Helgaas1-6/+3
Previously we relied on the PCIe r3.0, sec 7.8, spec language that says "For Functions that do not implement the [Link, Slot, Root] registers, these spaces must be hardwired to 0b," which means that for v2 PCIe capabilities, we don't need to check the device type at all. But it's simpler if we don't need to check the capability version at all, and I think the spec is explicit enough about which registers are required for which types that we can remove the version checks. Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-By: Jiang Liu <[email protected]>
2013-08-28PCI: Allow PCIe Capability link-related register access for switchesBjorn Helgaas1-2/+6
Every PCIe device has a link, except Root Complex Integrated Endpoints and Root Complex Event Collectors. Previously we didn't give access to PCIe capability link-related registers for Upstream Ports, Downstream Ports, and Bridges, so attempts to read PCI_EXP_LNKCTL incorrectly returned zero. See PCIe spec r3.0, sec 7.8 and 1.3.2.3. Reference: http://lkml.kernel.org/r/979A8436335E3744ADCD3A9F2A2B68A52AD136BE@SJEXCHMB10.corp.ad.broadcom.com Reported-by: Yuval Mintz <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> Reviewed-By: Jiang Liu <[email protected]>
2013-02-15PCI: Fix PCI Express Capability accessors for PCI_EXP_FLAGSAlex Williamson1-1/+1
PCI_EXP_FLAGS_TYPE is a mask, not an offset. Fix it. Previously, pcie_capability_read_word(..., PCI_EXP_FLAGS, ...) would fail. [bhelgaas: tweak changelog] Signed-off-by: Alex Williamson <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]> CC: [email protected] # v3.7+
2013-01-30PCI: Use PCI Express Capability accessorMyron Stowe1-2/+2
Use PCI Express Capability access functions to simplify device Capabilities Register usages. Signed-off-by: Myron Stowe <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
2012-08-23PCI: Add accessors for PCI Express CapabilityJiang Liu1-0/+202
The PCI Express Capability (PCIe spec r3.0, sec 7.8) comes in two versions, v1 and v2. In v1 Capability structures (PCIe spec r1.0 and r1.1), some fields are optional, so the structure size depends on the device type. This patch adds functions to access this capability so drivers don't have to be aware of the differences between v1 and v2. Note that these new functions apply only to the "PCI Express Capability," not to any of the other "PCI Express Extended Capabilities" (AER, VC, ACS, MFVC, etc.) Function pcie_capability_read_word/dword() reads the PCIe Capabilities register and returns the value in the reference parameter "val". If the PCIe Capabilities register is not implemented on the PCIe device, "val" is set to 0. Function pcie_capability_write_word/dword() writes the value to the specified PCIe Capability register. Function pcie_capability_clear_and_set_word/dword() sets and/or clears bits of a PCIe Capability register. [bhelgaas: changelog, drop "pci_" prefixes, don't export pcie_capability_reg_implemented()] Signed-off-by: Jiang Liu <[email protected]> Signed-off-by: Yijing Wang <[email protected]> Signed-off-by: Bjorn Helgaas <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.