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This adds some additional register definitions for 8723bu, as well as
a bit define for USB RXDMA aggregation in REG_RXDMA_AGG_PG_TH.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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rtl8192cu/rtl8188cu/rtl8723au use the same values, but 8723bu and
8192eu have their own.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Usual gcc i386 issue reported by kbuildbot
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Fix a silly bug where the debug level was overwritten rather than
amended for untested chips.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Newer generation chips require the firmware be notified before we
start the IQK calibration.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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The firmware command API differs slightly between new and old
devices. The new generation requires the size since there is no
extension bit encoded into the command number.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Likewise for 8723bu, use a pointer to the efuse.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Make the code easier to read and less error prone by using a pointer
to the efuse.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Signed-off-by: Jakub Sitnicki <[email protected]>
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Signed-off-by: Jakub Sitnicki <[email protected]>
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Avoid a negative conditional and an extra level of indentation in the
bigger part of the loop body.
Signed-off-by: Jakub Sitnicki <[email protected]>
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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It is enough to check for either illegal offset or illegal map address
because map address is a value derived from an offset:
map_addr = offset * 8
EFUSE_MAP_LEN = EFUSE_MAX_SECTION_8723A * 8
Leave just the check for an illegal map address because its upper
bound (EFUSE_MAP_LEN) is used also in a couple other places.
Signed-off-by: Jakub Sitnicki <[email protected]>
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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The larger mailboxes also use a different set of mailbox commands.
This provides a list of the 64 bit commands.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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In addition do not apply fixups for 8188/8191/8192 A-cut UMC parts.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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This introduces additional register definitions for newer generation
chips.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Gen1 chips use a 16 bit mailbox extension register, for upto 48 bit
mailbox commands. The newer generation chips use a 32 bit mailbox
extension register instead, for upto 64 bit mailbox commands.
Handle writing the larger mailboxes.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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The different RF module seems to require a different AGC table as well
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Newer chips seem to have some different mac registers, requiring
a different init table.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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So far this is just for 8723BU. It includes writing to a number of
registers I have seen no description for so far.
0x0064
0x0930
0x0944
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Add 8723bu 1T radio init table. The vendor driver indicates that some
registers need special treatment for TFBGA90, TFBGA80, and TFBGA79
packaging. However the vendor driver never actually checks the package
type, so just stick to default values here.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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This adds the 8723bu PHY 1T init table.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Only 1st generation chips do provide USB interrupts, so do not try to
setup interrupts for newer chips (8192eu and 8723bu).
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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The 8723bu, like the 8192eu, can also handle 1024 byte block writes.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Implement first stab at parsing the 8723bu's efuse.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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This provides initial detection of 8723bu devices, and selects the
correct firmware image to load.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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The newer generation chips have different interrupt registers.
Initialize this correct registers on 8192eu.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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The 8192eu (and some other parts) will report an incorrect USB OUT
EP. This tells the chip to drop it - as per the vendor driver.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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The logic for testing auto load failure in rtl8xxxu_auto_llt_table()
was inverted.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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To match the flow of the vendor driver, move the LLT init to after the
firmware is started.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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This reorganizes the device initialization to init page boundaries
before starting the firmware. This matches the flow in the 8192eu
vendor driver.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Newer chips can auto load the LLT table, it is no longer necessary to
build it manually in the driver.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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This implements the rtl8192eu power on sequence, and splits it off
from the rtl8192cu/rtl8723au power on sequence.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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The rtl8192eu can handle 1024 byte block writes, unlike it's
predecessors (8192cu/8188cu).
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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This identifies the chip vendors correctly and also picks the correct
firmware for rtl8192eu.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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This is the start of 8192eu support. For now just detect the device
and parse the efuse.
Signed-off-by: Jes Sorensen <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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Add debugfs key (under CFG80211_CERTIFICATION_ONUS
configuration) to set/clear radar_debug_mode.
In this mode, the driver simply ignores radar
events (but prints them).
The fw is notified about this mode through
a special generic_cfg_feature command.
This mode is relevant only for ap mode. look for
it when initializing ap vif.
Signed-off-by: Eliad Peller <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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When working with AP + P2P, it's possible to get into
a state when the AP is in ROC (due to assiciating station)
while trying to ROC on the P2P interface.
Replace the WARN_ON with wl1271_error to avoid warnings
in this case.
Signed-off-by: Eliad Peller <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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In cfg80211 suspend handler, stop the netif queue and
wait until all the Tx queues become empty. Start the
queues in resume handler.
Signed-off-by: Amitkumar Karwar <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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We met a problem of pm_suspend when repeated closing/opening the lid
on a Lenovo laptop (1/20 reproduce rate), below is the log:
[ 199.735876] PM: Entering mem sleep
[ 199.750516] e1000e: EEE TX LPI TIMER: 00000011
[ 199.856638] Trying to free nonexistent resource <000000000000d000-000000000000d0ff>
[ 201.753566] brcmfmac: brcmf_pcie_suspend: Timeout on response for entering D3 substate
[ 201.753581] pci_legacy_suspend(): brcmf_pcie_suspend+0x0/0x1f0 [brcmfmac] returns -5
[ 201.753585] dpm_run_callback(): pci_pm_suspend+0x0/0x160 returns -5
[ 201.753589] PM: Device 0000:04:00.0 failed to suspend async: error -5
Through debugging, we found when problem happens, it is not the device
fails to enter D3, but the signal D3_ACK comes too early to pass the
waitqueue_active() check.
Just like this:
brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
// signal is triggered here
wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
BRCMF_PCIE_MBDATA_TIMEOUT);
So far I think it is safe to remove waitqueue_active check since there
is only one place to trigger this signal (sending
BRCMF_H2D_HOST_D3_INFORM). And it is not a problem calling wake_up
event earlier than calling wait_event.
Cc: Brett Rudley <[email protected]>
Cc: Hante Meuleman <[email protected]>
Cc: Franky (Zhenhui) Lin <[email protected]>
Cc: Pieter-Paul Giesberts <[email protected]>
Cc: Arend van Spriel <[email protected]>
Signed-off-by: Hui Wang <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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We accidentally return success instead of a negative error code.
Signed-off-by: Dan Carpenter <[email protected]>
Signed-off-by: Kalle Valo <[email protected]>
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https://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next
* update GSCAN capabilities (Ayala)
* fix AES-CMAC in AP mode (Johannes)
* adapt prints to new firmware API
* rx path improvements (Sara and Gregory)
* fixes for the thermal / cooling device code (Chaya Rachel)
* fixes for GO uAPSD handling
* more code for the 9000 device family (Sara)
* infrastructure work for firmware notification (Chaya Rachel)
* improve association reliablity (Sara)
* runtime PM fixes
* fixes for ROC (HS2.0)
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Added r8a7795 SoC support.
Signed-off-by: Ramesh Shanmugasundaram <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Marc Kleine-Budde <[email protected]>
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In case of CAN2.0 EFF frame, the controller handles frame IDs in a
rather bizzare way. The ID is split into an extended part, IDX[28:11]
and standard part, ID[10:0]. In the TX path, the core first sends the
top 11 bits of the IDX, followed by ID and finally the rest of IDX.
In the RX path, the core stores the ID the LSbit part of IDX field,
followed by the LSbit parts of real IDX. The MSbit parts of IDX are
stored in ID field of the register.
This patch implements the necessary bit shuffling to mitigate this
obscure behavior. In case two of these controllers are connected
together, the RX and TX bit swapping nullifies itself and the issue
does not manifest. The issue only manifests when talking to another
different CAN controller.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Marc Kleine-Budde <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Oliver Hartkopp <[email protected]>
Cc: Wolfgang Grandegger <[email protected]>
Reviewed-by: Oliver Hartkopp <[email protected]>
Signed-off-by: Marc Kleine-Budde <[email protected]>
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The RX and TX ID mask for CAN2.0 is 11 bits wide. This patch fixes
the incorrect mask, which caused the CAN IDs to miss the MSBit both
on receive and transmit.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Marc Kleine-Budde <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Oliver Hartkopp <[email protected]>
Cc: Wolfgang Grandegger <[email protected]>
Reviewed-by: Oliver Hartkopp <[email protected]>
Signed-off-by: Marc Kleine-Budde <[email protected]>
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The TX DLC, the transmission length information, was not written
into the transmit configuration register. When using the CAN core
with different CAN controller, the receiving CAN controller will
receive only the ID part of the CAN frame, but no data at all.
This patch adds the TX DLC into the register to fix this issue.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Marc Kleine-Budde <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Oliver Hartkopp <[email protected]>
Cc: Wolfgang Grandegger <[email protected]>
Reviewed-by: Oliver Hartkopp <[email protected]>
Signed-off-by: Marc Kleine-Budde <[email protected]>
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The clock generation does not match reality when using the CAN IP
core outside of the FPGA design. This patch fixes the computation
of values which are programmed into the clock generator registers.
First, there are some off-by-one errors which manifest themselves
only when communicating with different controller, so those are
fixed.
Second, the bits in the clock generator registers have different
meaning depending on whether the core is in ISO CANFD mode or any
of the other modes (BOSCH CANFD or CAN2.0). Detect the ISO CANFD
mode and fix handling of this special case of clock configuration.
Finally, the CAN clock speed is in CANCLOCK register, not SYSCLOCK
register, so fix this as well.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Marc Kleine-Budde <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Oliver Hartkopp <[email protected]>
Cc: Wolfgang Grandegger <[email protected]>
Reviewed-by: Oliver Hartkopp <[email protected]>
Signed-off-by: Marc Kleine-Budde <[email protected]>
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Gscan capabilities were updated with new capabilities supported
by the device. While at it, simplify the firmware support
conditional and move both conditions into the WARN() to make it
easier to undertand and use the unlikely() for both.
Signed-off-by: Ayala Beker <[email protected]>
Signed-off-by: Emmanuel Grumbach <[email protected]>
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The firmware/hardware only supports checking AES-CMAC on RX, not
using it on TX. For station mode this is fine, since it's the only
thing it will ever do. For AP mode, it never receives such frames,
but must be able to transmit them. This is currently broken since
we try to enable them for hardware crypto (for RX only) and then
treat them as TX_CMD_SEC_EXT, leading to FIFO underruns during TX
so the frames never go out to the air.
To fix this, simply use software on TX in AP (and IBSS) mode.
Signed-off-by: Johannes Berg <[email protected]>
Signed-off-by: Emmanuel Grumbach <[email protected]>
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Newer firmware versions put different data in the memory
which is read by the driver upon firmware crash. Just
change the variable names in the code and the name of the
data in the log that we print withouth any functional
change.
On older firmware, there will be a mismatch between the
names that are printed and the content itself, but that's
harmless.
Signed-off-by: Emmanuel Grumbach <[email protected]>
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