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2021-02-11octeontx2-pf: cn10k: Get max mtu supported from admin functionHariprasad Kelam7-18/+97
CN10K supports max MTU of 16K on LMAC links and 64k on LBK links and Octeontx2 silicon supports 9K mtu on both links. Get the same from nix_get_hw_info mbox message in netdev probe. This patch also calculates receive buffer size required based on the MTU set. Signed-off-by: Hariprasad Kelam <[email protected]> Signed-off-by: Subbaraya Sundeep <[email protected]> Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11octeontx2-af: cn10K: Add MTU configurationHariprasad Kelam11-12/+138
OcteonTx3 CN10K silicon supports bigger MTU when compared to 9216 MTU supported by OcteonTx2 silicon variants. Lookback interface supports upto 64K and RPM LMAC interfaces support upto 16K. This patch does the necessary configuration and adds support for PF/VF drivers to retrieve max packet size supported via mbox This patch also configures tx link credit by considering supported fifo size and max packet length for Octeontx3 silicon. This patch also removes platform specific name from the driver name. Signed-off-by: Hariprasad Kelam <[email protected]> Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11octeontx2-af: cn10k: Add support for programmable channelsSubbaraya Sundeep11-17/+359
NIX uses unique channel numbers to identify the packet sources/sinks like CGX,LBK and SDP. The channel numbers assigned to each block are hardwired in CN9xxx silicon. The fixed channel numbers in CN9xxx are: 0x0 | a << 8 | b - LBK(0..3)_CH(0..63) 0x0 | a << 8 - Reserved 0x700 | a - SDP_CH(0..255) 0x800 | a << 8 | b << 4 | c - CGX(0..7)_LMAC(0..3)_CH(0..15) All the channels in the above fixed enumerator(with maximum number of blocks) are not required since some chips have less number of blocks. For CN10K silicon the channel numbers need to be programmed by software in each block with the base channel number and range of channels. This patch calculates and assigns the channel numbers to efficiently distribute the channel number range(0-4095) among all the blocks. The assignment is made based on the actual number of blocks present and also contiguously leaving no holes. The channel numbers remaining after the math are used as new CPT replay channels present in CN10K. Also since channel numbers are not fixed the transmit channel link number needed by AF consumers is calculated by AF and sent along with nix_lf_alloc mailbox response. Signed-off-by: Subbaraya Sundeep <[email protected]> Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11octeontx2-af: cn10k: Add RPM MAC supportHariprasad Kelam11-106/+478
OcteonTx2's next gen platform the CN10K has RPM MAC which has a different serdes when compared to CGX MAC. Though the underlying HW is different, the CSR interface has been designed largely inline with CGX MAC, with few exceptions though. So we are using the same CGX driver for RPM MAC as well and will have a different set of APIs for RPM where ever necessary. This patch adds initial support for CN10K's RPM MAC i.e. the driver registration, communication with firmware etc. For communication with firmware, RPM provides a different IRQ when compared to CGX. The CGX and RPM blocks support different features. Currently few features like ptp, flowcontrol and higig are not supported by RPM. This patch adds new mailbox message "CGX_FEATURES_GET" to get the list of features supported by underlying MAC. RPM has different implementations for RX/TX stats. Unlike CGX, bar offset of stat registers are different. This patch adds support to access the same and dump the values in debugfs. Signed-off-by: Hariprasad Kelam <[email protected]> Signed-off-by: Subbaraya Sundeep <[email protected]> Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11octeontx2-pf: cn10k: Use LMTST lines for NPA/NIX operationsGeetha sowjanya10-135/+328
This patch adds support to use new LMTST lines for NPA batch free and burst SQE flush. Adds new dev_hw_ops structure to hold platform specific functions and create new files cn10k.c and cn10k.h. Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11octeontx2-pf: cn10k: Map LMTST regionGeetha sowjanya3-4/+100
On CN10K platform transmit/receive buffer alloc and free from/to hardware had changed to support burst operation. Whereas pervious silicon's only support single buffer free at a time. To Support the same firmware allocates a DRAM region for each PF/VF for storing LMTLINES. These LMTLINES are used for NPA batch free and for flushing SQE to the hardware. PF/VF LMTST region is accessed via BAR4. PFs LMTST region is followed by its VFs mbox memory. The size of region varies from 2KB to 256KB based on number of LMTLINES configured. This patch adds support for - Mapping PF/VF LMTST region. - Reserves 0-71 (RX + TX + XDP) LMTST lines for NPA batch free operation. - Reserves 72-512 LMTST lines for NIX SQE flush. Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11octeontx2-pf: cn10k: Initialise NIX contextGeetha sowjanya2-31/+80
On CN10K platform NIX RQ and SQ context structure got changed. This patch uses new mbox message "NIX_CN10K_AQ_ENQ" for NIX context initialization on CN10K platform. This patch also updates the nix_rx_parse_s and nix_sqe_sg_s structures to add packet steering bit feilds. Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11octeontx2-af: cn10k: Update NIX and NPA context in debugfsGeetha sowjanya1-2/+175
On CN10K platform NPA and NIX context structure bit fields had changed to support new features like bandwidth steering etc. This patch dumps approprate context for CN10K platform. Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11octeontx2-af: cn10k: Update NIX/NPA context structureGeetha sowjanya3-424/+223
NIX hardware context structure got changed to accommodate new features like bandwidth steering, L3/L4 outer/inner checksum enable/disable etc., on CN10K platform. This patch defines new mbox message NIX_CN10K_AQ_INST for new NIX context initialization. This patch also updates the NPA context structures to accommodate bit field changes made for CN10K platform. This patch also removes Big endian bit fields from existing structures as its support got deprecated in current and upcoming silicons. Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11octeontx2-pf: cn10k: Add mbox support for CN10KSubbaraya Sundeep6-27/+73
Firmware allocates memory regions for PFs and VFs in DRAM. The PFs memory region is used for AF-PF and PF-VF mailbox. This mbox facilitate communication between AF-PF and PF-VF. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. The base address of PF-VF mbox region for each PF is configure at RVU_AF_PF(0..15)_VF_BAR4_ADDR.PF access its mbox region via BAR4 and its VF mbox regions from RVU_PF_VF_BAR4_ADDR register, whereas VF access its mbox region via BAR4. This patch changes mbox initialization to support both CN9XX and CN10K platform. The patch also adds new hw_cap flag to setting hw features like TSO etc and removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms This patch also removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms Signed-off-by: Subbaraya Sundeep <[email protected]> Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11octeontx2-af: cn10k: Add mbox support for CN10K platformSubbaraya Sundeep6-36/+191
Firmware allocates memory regions for PFs and VFs in DRAM. The PFs memory region is used for AF-PF and PF-VF mailbox. This mbox facilitates communication between AF-PF and PF-VF. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. The base address of PF-VF mbox region for each PF is configure at RVU_AF_PF(0..15)_VF_BAR4_ADDR.PF access its mbox region via BAR4 and its VF mbox regions from RVU_PF_VF_BAR4_ADDR register, whereas VF access its mbox region via BAR4. This patch changes mbox initialization to support both CN9XX and CN10K platform. This patch also adds CN10K PTP subsystem and device IDs to ptp driver id table. Signed-off-by: Subbaraya Sundeep <[email protected]> Signed-off-by: Geetha sowjanya <[email protected]> Signed-off-by: Sunil Goutham <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: add TX FC firmware checkStefan Chulski2-7/+33
Patch check that TX FC firmware is running in CM3. If not, global TX FC would be disabled. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: set 802.3x GoP Flow Control modeStefan Chulski1-1/+1
This patch fix GMAC TX flow control autoneg. Flow control autoneg wrongly were disabled with enabled TX flow control. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: add PPv23 RX FIFO flow controlStefan Chulski2-0/+68
New FIFO flow control feature was added in PPv23. PPv2 FIFO polled by HW and trigger pause frame if FIFO fill level is below threshold. FIFO HW flow control enabled with CM3 RXQ&BM flow control with ethtool. Current FIFO thresholds is: 9KB for port with maximum speed 10Gb/s port 4KB for port with maximum speed 5Gb/s port 2KB for port with maximum speed 1Gb/s port Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: add BM protection underrun feature supportStefan Chulski2-0/+34
The PP2v23 hardware supports a feature allowing to double the size of BPPI by decreasing number of pools from 16 to 8. Increasing of BPPI size protect BM drop from BPPI underrun. Underrun could occurred due to stress on DDR and as result slow buffer transition from BPPE to BPPI. New BPPI threshold recommended by spec is: BPPI low threshold - 640 buffers BPPI high threshold - 832 buffers Supported only in PPv23. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: add ethtool flow control configuration supportStefan Chulski2-0/+111
This patch add ethtool flow control configuration support. Tx flow control retrieved correctly by ethtool get function. FW per port ethtool configuration capability added. Patch also takes care about mtu change procedure, if PPv2 switch BM pools during mtu change. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: add RXQ flow control configurationsStefan Chulski2-1/+150
This patch adds RXQ flow control configurations. Flow control disabled by default. Minimum ring size limited to 1024 descriptors. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: enable global flow controlStefan Chulski2-4/+37
This patch enables global flow control in FW and in the phylink validate mask. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: add FCA RXQ non occupied descriptor thresholdStefan Chulski2-7/+40
The firmware needs to monitor the RX Non-occupied descriptor bits for flow control to move to XOFF mode. These bits need to be unmasked to be functional, but they will not raise interrupts as we leave the RX exception summary bit in MVPP2_ISR_RX_TX_MASK_REG clear. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: add FCA periodic timer configurationsStefan Chulski2-0/+58
Flow Control periodic timer would be used if port in XOFF to transmit periodic XOFF frames. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: increase BM pool and RXQ sizeStefan Chulski1-4/+4
BM pool and RXQ size increased to support Firmware Flow Control. Minimum depletion thresholds to support FC are 1024 buffers. BM pool size increased to 2048 to have some 1024 buffers space between depletion thresholds and BM pool size. Jumbo frames require a 9888B buffer, so memory requirements for data buffers increased from 7MB to 24MB. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Reviewed-by: Russell King <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: add PPv23 version definitionStefan Chulski2-15/+24
This patch add PPv23 version definition. PPv23 is new packet processor in CP115. Everything that supported by PPv22, also supported by PPv23. No functional changes in this stage. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Reviewed-by: Russell King <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: always compare hw-version vs MVPP21Stefan Chulski1-19/+19
Currently we have PP2v1 and PP2v2 hw-versions, with some different handlers depending upon condition hw_version = MVPP21/MVPP22. In a future there will be also PP2v3. Let's use now the generic "if equal/notEqual MVPP21" for all cases instead of "if MVPP22". This patch does not change any functionality. It is not intended to introduce PP2v3. It just modifies MVPP21/MVPP22 check-condition bringing it to generic and unified form correct for new-code introducing and PP2v3 net-next generation. Signed-off-by: Stefan Chulski <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: mvpp2: add CM3 SRAM memory mapStefan Chulski2-0/+27
This patch adds CM3 memory map. Signed-off-by: Stefan Chulski <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Acked-by: Marcin Wojtas <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11xen/events: link interdomain events to associated xenbus deviceJuergen Gross1-8/+8
In order to support the possibility of per-device event channel settings (e.g. lateeoi spurious event thresholds) add a xenbus device pointer to struct irq_info() and modify the related event channel binding interfaces to take the pointer to the xenbus device as a parameter instead of the domain id of the other side. While at it remove the stale prototype of bind_evtchn_to_irq_lateeoi(). Signed-off-by: Juergen Gross <[email protected]> Reviewed-by: Boris Ostrovsky <[email protected]> Reviewed-by: Wei Liu <[email protected]> Reviewed-by: Paul Durrant <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11xen/netback: fix spurious event detection for common event caseJuergen Gross1-3/+5
In case of a common event for rx and tx queue the event should be regarded to be spurious if no rx and no tx requests are pending. Unfortunately the condition for testing that is wrong causing to decide a event being spurious if no rx OR no tx requests are pending. Fix that plus using local variables for rx/tx pending indicators in order to split function calls and if condition. Fixes: 23025393dbeb3b ("xen/netback: use lateeoi irq binding") Signed-off-by: Juergen Gross <[email protected]> Reviewed-by: Jan Beulich <[email protected]> Reviewed-by: Paul Durrant <[email protected]> Reviewed-by: Wei Liu <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11Merge tag 'mlx5-for-upstream-2021-02-10' of ↵David S. Miller8-10/+16
git://git.kernel.org/pub/scm/linux/kernel/git/saeed/linux Saeed Mahameed says: ==================== mlx5-for-upstream-2021-02-10 Misc cleanups and trivial fixes for net-next 1) spelling mistakes 2) error path checks fixes 3) unused includes and struct fields cleanup 4) build error when MLX5_ESWITCH=no ==================== Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: ethernet: aquantia: Handle error cleanup of start on openNathan Rossi1-1/+3
The aq_nic_start function can fail in a variety of cases which leaves the device in broken state. An example case where the start function fails is the request_threaded_irq which can be interrupted, resulting in a EINTR result. This can be manually triggered by bringing the link up (e.g. ip link set up) and triggering a SIGINT on the initiating process (e.g. Ctrl+C). This would put the device into a half configured state. Subsequently bringing the link up again would cause the napi_enable to BUG. In order to correctly clean up the failed attempt to start a device call aq_nic_stop. Signed-off-by: Nathan Rossi <[email protected]> Reviewed-by: Igor Russkikh <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11bnxt_en: Fix devlink info's stored fw.psid version format.Vasundhara Volam1-2/+2
The running fw.psid version is in decimal format but the stored fw.psid is in hex format. This can mislead the user to reset the NIC to activate the stored version to become the running version. Fix it to display the stored fw.psid in decimal format. Fixes: 1388875b3916 ("bnxt_en: Add stored FW version info to devlink info_get cb.") Signed-off-by: Vasundhara Volam <[email protected]> Signed-off-by: Michael Chan <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11bnxt_en: reverse order of TX disable and carrier offEdwin Peer1-1/+2
A TX queue can potentially immediately timeout after it is stopped and the last TX timestamp on that queue was more than 5 seconds ago with carrier still up. Prevent these intermittent false TX timeouts by bringing down carrier first before calling netif_tx_disable(). Fixes: c0c050c58d84 ("bnxt_en: New Broadcom ethernet driver.") Signed-off-by: Edwin Peer <[email protected]> Signed-off-by: Michael Chan <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11ibmvnic: Set to CLOSED state even on errorSukadev Bhattiprolu1-3/+1
If set_link_state() fails for any reason, we still cleanup the adapter state and cannot recover from a partial close anyway. So set the adapter to CLOSED state. That way if a new soft/hard reset is processed, the adapter will remain in the CLOSED state until the next ibmvnic_open(). Fixes: 01d9bd792d16 ("ibmvnic: Reorganize device close") Signed-off-by: Sukadev Bhattiprolu <[email protected]> Reported-by: Abdul Haleem <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11r8169: disable detection of bogus xid's 308/388Heiner Kallweit1-3/+6
Several years ago these two entries have been added, but it's not clear why. There's no trace that there has ever been such a chip version, and not even the r8101 vendor driver knows these id's. So let's disable detection, and if nobody complains remove them completely later. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11bonding: 3ad: Print an error for unknown speedsIdo Schimmel1-4/+4
The bond driver needs to be patched to support new ethtool speeds. Currently it emits a single warning [1] when it encounters an unknown speed. As evident by the two previous patches, this is not explicit enough. Instead, promote it to an error. [1] bond10: (slave swp1): unknown ethtool speed (200000) for port 1 (set it to 0) v2: * Use pr_err_once() instead of WARN_ONCE() Signed-off-by: Ido Schimmel <[email protected]> Signed-off-by: Nikolay Aleksandrov <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11bonding: 3ad: add support for 400G speedNikolay Aleksandrov1-0/+9
In order to be able to use 3ad mode with 400G devices we need to extend the supported speeds. Signed-off-by: Nikolay Aleksandrov <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11bonding: 3ad: add support for 200G speedNikolay Aleksandrov1-0/+9
In order to be able to use 3ad mode with 200G devices we need to extend the supported speeds. Signed-off-by: Nikolay Aleksandrov <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11qede: preserve per queue stats across up/down of interfaceBhaskar Upadhaya3-7/+48
Here we do the initialization of coalescing values on load. per queue coalesce values are also restored across up/down of ethernet interface. Signed-off-by: Bhaskar Upadhaya <[email protected]> Signed-off-by: Igor Russkikh <[email protected]> Signed-off-by: Ariel Elior <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11qede: add per queue coalesce support for qede driverBhaskar Upadhaya1-0/+124
per queue coalescing allows better and more finegrained control over interrupt rates. Signed-off-by: Bhaskar Upadhaya <[email protected]> Signed-off-by: Igor Russkikh <[email protected]> Signed-off-by: Ariel Elior <[email protected]> Reported-by: Dan Carpenter <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11qede: add netpoll support for qede driverBhaskar Upadhaya1-1/+2
handle netpoll case when qede_poll is called by netpoll layer with budget 0 Signed-off-by: Bhaskar Upadhaya <[email protected]> Signed-off-by: Igor Russkikh <[email protected]> Signed-off-by: Ariel Elior <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: hns3: fix return of random stack valueGustavo A. R. Silva1-2/+1
Currently, a random stack value is being returned because variable _ret_ is not properly initialized. This variable is actually not used anymore and it should be removed. Fix this by removing all instances of variable ret and return 0. Fixes: 64749c9c38a9 ("net: hns3: remove redundant return value of hns3_uninit_all_ring()") Addresses-Coverity-ID: 1501700 ("Uninitialized scalar variable") Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: stmmac: dwmac-intel-plat: remove unnecessary initializationNobuhiro Iwamatsu1-3/+0
plat_dat is initialized by stmmac_probe_config_dt(). So, initialization is not required by priv->plat. This removes unnecessary initialization and variables. Signed-off-by: Nobuhiro Iwamatsu <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11r8169: re-configure WOL settings on resume from hibernationHeiner Kallweit1-11/+5
So far we don't re-configure WOL-related register bits when waking up from hibernation. I'm not aware of any problem reports, but better play safe and call __rtl8169_set_wol() in the resume() path too. To achieve this move calling __rtl8169_set_wol() to rtl8169_net_resume() and rename the function to rtl8169_runtime_resume(). Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: phy: icplus: add MDI/MDIX support for IP101A/GMichael Walle1-0/+97
Implement the operations to set desired mode and retrieve the current mode. This feature was tested with an IP101G. Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: phy: icplus: add PHY counter for IP101GMichael Walle1-0/+75
The IP101G provides three counters: RX packets, CRC errors and symbol errors. The error counters can be configured to clear automatically on read. Unfortunately, this isn't true for the RX packet counter. Because of this and because the RX packet counter is more likely to overflow, than the error counters implement only support for the error counters. Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: phy: icplus: fix paged register accessMichael Walle1-13/+54
Registers >= 16 are paged. Be sure to set the page. It seems this was working for now, because the default is correct for the registers used in the driver at the moment. But this will also assume, nobody will change the page select register before linux is started. The page select register is _not_ reset with a soft reset of the PHY. To ease the function reuse between the non-paged register space of the IP101A and the IP101G, add noop read_page()/write_page() callbacks so the IP101G functions can also be used for the IP101A. Signed-off-by: Michael Walle <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: phy: icplus: don't set APS_EN bit on IP101GMichael Walle1-7/+20
This bit is reserved as 'always-write-1'. While this is not a particular error, because we are only setting it, guard it by checking the model to prevent errors in the future. Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: phy: icplus: split IP101A/G driverMichael Walle1-3/+66
Unfortunately, the IP101A and IP101G share the same PHY identifier. While most of the functions are somewhat backwards compatible, there is for example the APS_EN bit on the IP101A but on the IP101G this bit reserved. Also, the IP101G has many more functionalities. Deduce the model by accessing the page select register which - according to the datasheet - is not available on the IP101A. If this register is writable, assume we have an IP101G. Split the combined IP101A/G driver into two separate drivers. Signed-off-by: Michael Walle <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: phy: icplus: use the .soft_reset() of the phy-coreMichael Walle1-30/+2
The PHY core already resets the PHY before .config_init() if a .soft_reset() op is registered. Drop the open-coded ip1xx_reset(). Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: phy: icplus: drop address operator for functionsMichael Walle1-5/+5
Don't sometimes use the address operator and sometimes not. Drop it and make the code look uniform. Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: phy: icplus: use PHY_ID_MATCH_EXACT() for IP101A/GMichael Walle1-2/+2
According to the datasheet of the IP101A/G there is no revision field and MII_PHYSID2 always reads as 0x0c54. Use PHY_ID_MATCH_EXACT() then. Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-02-11net: phy: icplus: use PHY_ID_MATCH_MODEL() macroMichael Walle1-9/+10
Simpify the initializations of the structures. There is no functional change. Signed-off-by: Michael Walle <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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