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2023-03-21net: geneve: accept every ethertypeJosef Miegl1-7/+2
The Geneve encapsulation, as defined in RFC 8926, has a Protocol Type field, which states the Ethertype of the payload appearing after the Geneve header. Commit 435fe1c0c1f7 ("net: geneve: support IPv4/IPv6 as inner protocol") introduced a new IFLA_GENEVE_INNER_PROTO_INHERIT flag that allowed the use of other Ethertypes than Ethernet. However, it did not get rid of a restriction that prohibits receiving payloads other than Ethernet, instead the commit white-listed additional Ethertypes, IPv4 and IPv6. This patch removes this restriction, making it possible to receive any Ethertype as a payload, if the IFLA_GENEVE_INNER_PROTO_INHERIT flag is set. The restriction was set in place back in commit 0b5e8b8eeae4 ("net: Add Geneve tunneling protocol driver"), which implemented a protocol layer driver for Geneve to be used with Open vSwitch. The relevant discussion about introducing the Ethertype white-list can be found here: https://lore.kernel.org/netdev/CAEP_g=_1q3ACX5NTHxLDnysL+dTMUVzdLpgw1apLKEdDSWPztw@mail.gmail.com/ <quote> >> + if (unlikely(geneveh->proto_type != htons(ETH_P_TEB))) > > Why? I thought the point of geneve carrying protocol field was to > allow protocols other than Ethernet... is this temporary maybe? Yes, it is temporary. Currently OVS only handles Ethernet packets but this restriction can be lifted once we have a consumer that is capable of handling other protocols. </quote> This white-list was then ported to a generic Geneve netdevice in commit 371bd1061d29 ("geneve: Consolidate Geneve functionality in single module."). Preserving the Ethertype white-list at this point made sense, as the Geneve device could send out only Ethernet payloads anyways. However, now that the Geneve netdevice supports encapsulating other payloads with IFLA_GENEVE_INNER_PROTO_INHERIT and we have a consumer capable of other protocols, it seems appropriate to lift the restriction and allow any Geneve payload to be received. Signed-off-by: Josef Miegl <[email protected]> Reviewed-by: Simon Horman <[email protected]> Reviewed-by: Eyal Birger <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2023-03-21net: dsa: b53: add support for BCM63xx RGMIIsÁlvaro Fernández Rojas2-0/+47
BCM63xx RGMII ports require additional configuration in order to work. Signed-off-by: Álvaro Fernández Rojas <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2023-03-21net: dsa: qca8k: remove assignment of an_enabled in pcs_get_state()Russell King (Oracle)1-1/+0
pcs_get_state() implementations are not supposed to alter an_enabled. Remove this assignment. Fixes: b3591c2a3661 ("net: dsa: qca8k: Switch to PHYLINK instead of PHYLIB") Signed-off-by: Russell King (Oracle) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2023-03-21net: dsa: mv88e6xxx: fix mdio bus' phy_mask memberMarek Behún1-1/+3
Commit 2c7e46edbd03 ("net: dsa: mv88e6xxx: mask apparently non-existing phys during probing") added non-trivial bus->phy_mask in mv88e6xxx_mdio_register() in order to avoid excessive mdio bus transactions during probing. But the mask is incorrect for switches with non-zero phy_base_addr (such as 88E6341). Fix this. Fixes: 2c7e46edbd03 ("net: dsa: mv88e6xxx: mask apparently non-existing phys during probing") Signed-off-by: Marek Behún <[email protected]> Tested-by: Klaus Kudielka <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2023-03-20octeontx2-vf: Add missing free for alloc_percpuJiasheng Jiang1-0/+2
Add the free_percpu for the allocated "vf->hw.lmt_info" in order to avoid memory leak, same as the "pf->hw.lmt_info" in `drivers/net/ethernet/marvell/octeontx2/nic/otx2_pf.c`. Fixes: 5c0512072f65 ("octeontx2-pf: cn10k: Use runtime allocated LMTLINE region") Signed-off-by: Jiasheng Jiang <[email protected]> Reviewed-by: Michal Swiatkowski <[email protected]> Acked-by: Geethasowjanya Akula <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2023-03-20net: cxgb3: remove unused fl_to_qset functionTom Rix1-5/+0
clang with W=1 reports drivers/net/ethernet/chelsio/cxgb3/sge.c:169:32: error: unused function 'fl_to_qset' [-Werror,-Wunused-function] static inline struct sge_qset *fl_to_qset(const struct sge_fl *q, int qidx) ^ This function is not used, so remove it. Signed-off-by: Tom Rix <[email protected]> Reviewed-by: Horatiu Vultur <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2023-03-20net: dsa: mt7530: use external PCS driverDaniel Golle3-254/+71
Implement regmap access wrappers, for now only to be used by the pcs-mtk-lynxi driver. Make use of this external PCS driver and drop the now reduntant implementation in mt7530.c. As a nice side effect the SGMII registers can now also more easily be inspected for debugging via /sys/kernel/debug/regmap. Tested-by: Bjørn Mork <[email protected]> Signed-off-by: Daniel Golle <[email protected]> Tested-by: Frank Wunderlich <[email protected]> Reviewed-by: Russell King (Oracle) <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2023-03-20net: ethernet: mtk_eth_soc: switch to external PCS driverDaniel Golle5-319/+56
Now that we got a PCS driver, use it and remove the now redundant PCS code and it's header macros from the Ethernet driver. Signed-off-by: Daniel Golle <[email protected]> Tested-by: Frank Wunderlich <[email protected]> Reviewed-by: Russell King (Oracle) <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2023-03-20net: pcs: add driver for MediaTek SGMII PCSDaniel Golle3-0/+313
The SGMII core found in several MediaTek SoCs is identical to what can also be found in MediaTek's MT7531 Ethernet switch IC. As this has not always been clear, both drivers developed different implementations to deal with the PCS. Recently Alexander Couzens pointed out this fact which lead to the development of this shared driver. Add a dedicated driver, mostly by copying the code now found in the Ethernet driver. The now redundant code will be removed by a follow-up commit. Suggested-by: Alexander Couzens <[email protected]> Suggested-by: Russell King (Oracle) <[email protected]> Signed-off-by: Daniel Golle <[email protected]> Tested-by: Frank Wunderlich <[email protected]> Reviewed-by: Russell King (Oracle) <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2023-03-20net: ethernet: mtk_eth_soc: ppe: add support for flow accountingDaniel Golle7-9/+172
The PPE units found in MT7622 and newer support packet and byte accounting of hw-offloaded flows. Add support for reading those counters as found in MediaTek's SDK[1]. [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/bc6a6a375c800dc2b80e1a325a2c732d1737df92 Tested-by: Bjørn Mork <[email protected]> Signed-off-by: Daniel Golle <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2023-03-20net: ethernet: mtk_eth_soc: set MDIO bus clock frequencyDaniel Golle2-0/+28
Set MDIO bus clock frequency and allow setting a custom maximum frequency from device tree. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Tested-by: Bjørn Mork <[email protected]> Signed-off-by: Daniel Golle <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2023-03-20net: ethernet: mtk_eth_soc: add support for MT7981 SoCDaniel Golle4-3/+73
The MediaTek MT7981 SoC comes with two 1G/2.5G SGMII ports, just like MT7986. In addition MT7981 is equipped with a built-in 1000Base-T PHY which can be used with GMAC1. As many MT7981 boards make use of inverting SGMII signal polarity, add new device-tree attribute 'mediatek,pn_swap' to support them. Signed-off-by: Daniel Golle <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2023-03-20r8169: consolidate disabling ASPM before EPHY accessHeiner Kallweit1-39/+3
Now that rtl_hw_aspm_clkreq_enable() is a no-op for chip versions < 32, we can consolidate disabling ASPM before EPHY access in rtl_hw_start(). Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net: phy: meson-gxl: reuse functionality of the SMSC PHY driverHeiner Kallweit2-69/+9
The Amlogic Meson internal PHY's have the same register layout as certain SMSC PHY's (also for non-c22-standard registers). This seems to be more than just coincidence. Apparently they also need the same workaround for EDPD mode (energy detect power down). Therefore let's reuse SMSC PHY driver functionality in the meson-gxl PHY driver. Tested with a G12A internal PHY. I don't have GXL test hw, therefore I replace only the callbacks that are identical in the SMSC PHY driver. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net: phy: smsc: export functions for use by meson-gxl PHY driverHeiner Kallweit1-7/+13
The Amlogic Meson internal PHY's have the same register layout as certain SMSC PHY's (also for non-c22-standard registers). This seems to be more than just coincidence. Apparently they also need the same workaround for EDPD mode (energy detect power down). Therefore let's export SMSC PHY driver functionality for use by the meson-gxl PHY driver. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: Chris Healy <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net/ps3_gelic_net: Use dma_mapping_errorGeoff Levand1-11/+13
The current Gelic Etherenet driver was checking the return value of its dma_map_single call, and not using the dma_mapping_error() routine. Fixes runtime problems like these: DMA-API: ps3_gelic_driver sb_05: device driver failed to check map error WARNING: CPU: 0 PID: 0 at kernel/dma/debug.c:1027 .check_unmap+0x888/0x8dc Fixes: 02c1889166b4 ("ps3: gigabit ethernet driver for PS3, take3") Reviewed-by: Alexander Duyck <[email protected]> Signed-off-by: Geoff Levand <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net/ps3_gelic_net: Fix RX sk_buff lengthGeoff Levand2-11/+13
The Gelic Ethernet device needs to have the RX sk_buffs aligned to GELIC_NET_RXBUF_ALIGN, and also the length of the RX sk_buffs must be a multiple of GELIC_NET_RXBUF_ALIGN. The current Gelic Ethernet driver was not allocating sk_buffs large enough to allow for this alignment. Also, correct the maximum and minimum MTU sizes, and add a new preprocessor macro for the maximum frame size, GELIC_NET_MAX_FRAME. Fixes various randomly occurring runtime network errors. Fixes: 02c1889166b4 ("ps3: gigabit ethernet driver for PS3, take3") Signed-off-by: Geoff Levand <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20usb: plusb: remove unused pl_clear_QuickLink_features functionTom Rix1-6/+0
clang with W=1 reports drivers/net/usb/plusb.c:65:1: error: unused function 'pl_clear_QuickLink_features' [-Werror,-Wunused-function] pl_clear_QuickLink_features(struct usbnet *dev, int val) ^ This static function is not used, so remove it. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net: usb: lan78xx: Limit packet length to skb->lenSzymon Heidrich1-1/+17
Packet length retrieved from descriptor may be larger than the actual socket buffer length. In such case the cloned skb passed up the network stack will leak kernel memory contents. Additionally prevent integer underflow when size is less than ETH_FCS_LEN. Fixes: 55d7de9de6c3 ("Microchip's LAN7800 family USB 2/3 to 10/100/1000 Ethernet device driver") Signed-off-by: Szymon Heidrich <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net/mlx5e: Update IPsec per SA packets/bytes countRaed Salem4-41/+42
Providing per SA packets/bytes statistics mandates creating unique counter per SA flow for Rx/Tx, whenever offloaded SA statistics is desired query the specific SA counter to provide the stack with the needed data. Signed-off-by: Raed Salem <[email protected]> Link: https://lore.kernel.org/r/7d5ce20ac495f3054afb633128700e7b7eeeb3cd.1678714336.git.leon@kernel.org Signed-off-by: Leon Romanovsky <[email protected]>
2023-03-20net/mlx5e: Use one rule to count all IPsec Tx offloaded trafficRaed Salem2-5/+55
Currently one counter is shared between all IPsec Tx offloaded rules to count the total amount of packets/bytes that was IPsec Tx offloaded, replace this scheme by adding a new flow table (ft) with one rule that counts all flows that passes through this table (like Rx status ft), this ft is pointed by all IPsec Tx offloaded rules. The above allows to have a counter per tx flow rule in while keeping a separate global counter that store the aggregation outcome of all these per flow counters. Signed-off-by: Raed Salem <[email protected]> Link: https://lore.kernel.org/r/09b9119d1deb6e482fd2d17e1f5760d7c5be1e48.1678714336.git.leon@kernel.org Signed-off-by: Leon Romanovsky <[email protected]>
2023-03-20net/mlx5e: Support IPsec acquire default SARaed Salem1-5/+21
During XFRM stack acquire flow, a default SA is created to be updated later, once acquire netlink message is handled in user space. This SA is also passed to IPsec offload supporting driver, however this SA acts only as placeholder and does not have context suitable for offloading in HW yet. Identify this kind of SA by special offload flag (XFRM_DEV_OFFLOAD_FLAG_ACQ), and create a SW only context. In such cases with special mark so it won't be installed in HW in addition flow and on remove/delete free this SW only context. Signed-off-by: Raed Salem <[email protected]> Link: https://lore.kernel.org/r/8f36d6b61631dcd73fef0a0ac623456030bc9db0.1678714336.git.leon@kernel.org Signed-off-by: Leon Romanovsky <[email protected]>
2023-03-20net/mlx5e: Allow policies with reqid 0, to support IKE policy holesRaed Salem3-27/+59
IKE policies hole, is special policy that exists to allow for IKE traffic to bypass IPsec encryption even though there is already a policies and SA(s) configured on same endpoints, these policies does not nessecarly have the reqid configured, so need to add an exception for such policies. These kind of policies are allowed under the condition that at least upper protocol and/or ips are not 0. Signed-off-by: Raed Salem <[email protected]> Link: https://lore.kernel.org/r/cbcadde312c24de74c47d9b0616f86a5818cc9bf.1678714336.git.leon@kernel.org Signed-off-by: Leon Romanovsky <[email protected]>
2023-03-20net/mlx5e: Use chains for IPsec policy priority offloadPaul Blakey4-84/+315
Currently, policy priority field is ignored and so order of matching is unpredictable. Use chains for RX/TX policy offload to support the priority field. Signed-off-by: Paul Blakey <[email protected]> Reviewed-by: Raed Salem <[email protected]> Link: https://lore.kernel.org/r/9ef3ef88858217932696ad413b1b147b799a11be.1678714336.git.leon@kernel.org Signed-off-by: Leon Romanovsky <[email protected]>
2023-03-20net/mlx5: fs_core: Allow ignore_flow_level on TX destPaul Blakey1-1/+2
ignore_flow_level is also supported by firmware on TX, remove this limitation. Signed-off-by: Paul Blakey <[email protected]> Reviewed-by: Raed Salem <[email protected]> Reviewed-by: Saeed Mahameed <[email protected]> Link: https://lore.kernel.org/r/d0025722bfac0a82da758eb540fbf1ff3cacdf74.1678714336.git.leon@kernel.org Signed-off-by: Leon Romanovsky <[email protected]>
2023-03-20net/mlx5: fs_chains: Refactor to detach chains from tc usagePaul Blakey4-69/+55
To support more generic chains that will be used on other namespaces and without tc, refactor to remove the dependency on tc terms. Signed-off-by: Paul Blakey <[email protected]> Reviewed-by: Raed Salem <[email protected]> Link: https://lore.kernel.org/r/bb8570d532d569285b5bff981578507bd15350cb.1678714336.git.leon@kernel.org Signed-off-by: Leon Romanovsky <[email protected]>
2023-03-20net: qcom/emac: Fix use after free bug in emac_remove due to race conditionZheng Wang1-0/+6
In emac_probe, &adpt->work_thread is bound with emac_work_thread. Then it will be started by timeout handler emac_tx_timeout or a IRQ handler emac_isr. If we remove the driver which will call emac_remove to make cleanup, there may be a unfinished work. The possible sequence is as follows: Fix it by finishing the work before cleanup in the emac_remove and disable timeout response. CPU0 CPU1 |emac_work_thread emac_remove | free_netdev | kfree(netdev); | |emac_reinit_locked |emac_mac_down |//use netdev Fixes: b9b17debc69d ("net: emac: emac gigabit ethernet controller driver") Signed-off-by: Zheng Wang <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net: dsa: ocelot: add support for external physColin Foster1-7/+9
The VSC7512 has four ports with internal phys that are already supported. There are additional ports that can be configured to work with external phys. Add support for these additional ethernet ports. Signed-off-by: Colin Foster <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net: dsa: felix: allow serdes configuration for dsa portsColin Foster2-0/+8
Ports for Ocelot devices (VSC7511, VSC7512, VSC7513 and VSC7514) support external phys. When external phys are used, additional configuration on each port is required to enable QSGMII mode and set external phy modes. Add a configurable hook into these routines, so the external ports can be used. Signed-off-by: Colin Foster <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net: dsa: felix: allow configurable phylink_mac_configColin Foster2-0/+15
If a user of the Felix driver has a port running in SGMII / QSGMII mode, it will need to utilize phylink_mac_config(). Add this configurability. Signed-off-by: Colin Foster <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net: dsa: felix: attempt to initialize internal hsio pllsColin Foster1-0/+3
The VSC7512 and VSC7514 have internal PLLs that can be used to control different peripherals. Initialize these high speed I/O (HSIO) PLLs when they exist, so that dependent peripherals like QSGMII can function. Signed-off-by: Colin Foster <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net: mscc: ocelot: expose serdes configuration functionColin Foster2-26/+43
During chip initialization, ports that use SGMII / QSGMII to interface to external phys need to be configured on the VSC7513 and VSC7514. Expose this configuration routine, so it can be used by DSA drivers. Signed-off-by: Colin Foster <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net: mscc: ocelot: expose generic phylink_mac_config routineColin Foster2-18/+29
The ocelot-switch driver can utilize the phylink_mac_config routine. Move this to the ocelot library location and export the symbol to make this possible. Signed-off-by: Colin Foster <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20net: mscc: ocelot: expose ocelot_pll5_init routineColin Foster2-30/+31
Ocelot chips have an internal PLL that must be used when communicating through external phys. Expose the init routine, so it can be used by other drivers. Signed-off-by: Colin Foster <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-20wifi: rtl8xxxu: Support new chip RTL8710BU aka RTL8188GUBitterblue Smith12-62/+2481
This chip is found in cheap "free driver" USB adapters from Aliexpress. Initially they pretend to be a CD-ROM containing the driver for Windows. "Ejecting" switches the device to wifi mode. Features: 2.4 GHz, b/g/n mode, 1T1R, 150 Mbps. This chip is more unique than other Realtek chips: * The registers at addresses 0x0-0xff, which all the other chips use, can't be used here. New registers at 0x8000-0x80ff must be used instead. And it's not a simple matter of adding 0x8000: 0x2 (REG_SYS_FUNC) became 0x8004, 0x80 (REG_MCU_FW_DL) became 0x8090, etc. * Also there are a few new registers which must be accessed indirectly because their addresses don't fit in 16 bits. No other chips seem to have these. * The vendor driver compiles to 8188gu.ko, but the code calls the chip RTL8710B(U) pretty much everywhere, including messages visible to the user. Another difference compared to the other chips supported by rtl8xxxu is that it has a new PHY status struct, or three of them actually, from which we extract the RSSI, among other things. This is not unique, though, just new. The chips supported by rtw88 also use it. Signed-off-by: Bitterblue Smith <[email protected]> Reviewed-by: Ping-Ke Shih <[email protected]> Tested-by: Philipp Hortmann <[email protected]> # Edimax N150 Signed-off-by: Kalle Valo <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-20wifi: rtl8xxxu: RTL8192EU always needs full initBitterblue Smith1-0/+1
Always run the entire init sequence (rtl8xxxu_init_device()) for RTL8192EU. It's what the vendor driver does too. This fixes a bug where the device is unable to connect after rebooting: wlp3s0f3u2: send auth to ... (try 1/3) wlp3s0f3u2: send auth to ... (try 2/3) wlp3s0f3u2: send auth to ... (try 3/3) wlp3s0f3u2: authentication with ... timed out Rebooting leaves the device powered on (partially? at least the firmware is still running), but not really in a working state. Cc: [email protected] Signed-off-by: Bitterblue Smith <[email protected]> Acked-by: Jes Sorensen <[email protected]> Signed-off-by: Kalle Valo <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-03-19mlxsw: core_thermal: Fix fan speed in maximum cooling stateIdo Schimmel1-6/+1
The cooling levels array is supposed to prevent the system fans from being configured below a 20% duty cycle as otherwise some of them get stuck at 0 RPM. Due to an off-by-one error, the last element in the array was not initialized, causing it to be set to zero, which in turn lead to fans being configured with a 0% duty cycle in maximum cooling state. Since commit 332fdf951df8 ("mlxsw: thermal: Fix out-of-bounds memory accesses") the contents of the array are static. Therefore, instead of fixing the initialization of the array, simply remove it and adjust thermal_cooling_device_ops::set_cur_state() so that the configured duty cycle is never set below 20%. Before: # cat /sys/class/thermal/thermal_zone0/cdev0/type mlxsw_fan # echo 10 > /sys/class/thermal/thermal_zone0/cdev0/cur_state # cat /sys/class/hwmon/hwmon0/name mlxsw # cat /sys/class/hwmon/hwmon0/pwm1 0 After: # cat /sys/class/thermal/thermal_zone0/cdev0/type mlxsw_fan # echo 10 > /sys/class/thermal/thermal_zone0/cdev0/cur_state # cat /sys/class/hwmon/hwmon0/name mlxsw # cat /sys/class/hwmon/hwmon0/pwm1 255 This bug was uncovered when the thermal subsystem repeatedly tried to configure the cooling devices to their maximum state due to another issue [1]. This resulted in the fans being stuck at 0 RPM, which eventually lead to the system undergoing thermal shutdown. [1] https://lore.kernel.org/netdev/ZA3CFNhU4AbtsP4G@shredder/ Fixes: a421ce088ac8 ("mlxsw: core: Extend cooling device with cooling levels") Signed-off-by: Ido Schimmel <[email protected]> Reviewed-by: Vadim Pasternak <[email protected]> Signed-off-by: Petr Machata <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19net: lan966x: Stop using packing libraryHoratiu Vultur2-25/+50
When a frame is injected from CPU, it is required to create an IFH(Inter frame header) which sits in front of the frame that is transmitted. This IFH, contains different fields like destination port, to bypass the analyzer, priotity, etc. Lan966x it is using packing library to set and get the fields of this IFH. But this seems to be an expensive operations. If this is changed with a simpler implementation, the RX will be improved with ~5Mbit while on the TX is a much bigger improvement as it is required to set more fields. Below are the numbers for TX. Before: [ 5] 0.00-10.02 sec 439 MBytes 367 Mbits/sec 0 sender After: [ 5] 0.00-10.00 sec 578 MBytes 485 Mbits/sec 0 sender Signed-off-by: Horatiu Vultur <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19net: lan966x: Don't read RX timestamp if not neededHoratiu Vultur4-14/+15
Whenever a frame was received to the CPU, the HW is timestamping the frame. In the IFH(Inter Frame Header) it is found the nanosecond part of the timestamps the SW is required to read from HW the second part. But reading the second part it seems to be a expensive operations, so so change this such to read the second part only when rx filter is enabled. Doing this change gives the RX a performance boost of ~70mbit. before: [ 5] 0.00-10.01 sec 546 MBytes 457 Mbits/sec 0 sender now: [ 5] 0.00-10.01 sec 652 MBytes 530 Mbits/sec 0 sender Signed-off-by: Horatiu Vultur <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19net: sfp: fix state loss when updating state_hw_maskRussell King (Oracle)1-0/+5
Andrew reports that the SFF modules on one of the ZII platforms do not indicate link up due to the SFP code believing that LOS indicating that there is no signal being received from the remote end, but in fact the LOS signal is showing that there is signal. What makes SFF modules different from SFPs is they typically have an inverted LOS, which uncovered this issue. When we read the hardware state, we mask it with state_hw_mask so we ignore anything we're not interested in. However, we don't re-read when state_hw_mask changes, leading to sfp->state being stale. Arrange for a software poll of the module state after we have parsed the EEPROM in sfp_sm_mod_probe() and updated state_*_mask. This will generate any necessary events for signal changes for the state machine as well as updating sfp->state. Reported-by: Andrew Lunn <[email protected]> Tested-by: Andrew Lunn <[email protected]> Fixes: 8475c4b70b04 ("net: sfp: re-implement soft state polling setup") Signed-off-by: Russell King (Oracle) <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19net: stmmac: Fix for mismatched host/device DMA address widthJochen Henneberg5-18/+21
Currently DMA address width is either read from a RO device register or force set from the platform data. This breaks DMA when the host DMA address width is <=32it but the device is >32bit. Right now the driver may decide to use a 2nd DMA descriptor for another buffer (happens in case of TSO xmit) assuming that 32bit addressing is used due to platform configuration but the device will still use both descriptor addresses as one address. This can be observed with the Intel EHL platform driver that sets 32bit for addr64 but the MAC reports 40bit. The TX queue gets stuck in case of TCP with iptables NAT configuration on TSO packets. The logic should be like this: Whatever we do on the host side (memory allocation GFP flags) should happen with the host DMA width, whenever we decide how to set addresses on the device registers we must use the device DMA address width. This patch renames the platform address width field from addr64 (term used in device datasheet) to host_addr and uses this value exclusively for host side operations while all chip operations consider the device DMA width as read from the device register. Fixes: 7cfc4486e7ea ("stmmac: intel: Configure EHL PSE0 GbE and PSE1 GbE to 32 bits DMA addressing") Signed-off-by: Jochen Henneberg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19net: macb: Reset TX when TX halt times outHarini Katakam1-2/+8
Reset TX when halt times out i.e. disable TX, clean up TX BDs, interrupts (already done) and enable TX. This addresses the issue observed when iperf is run at 10Mps Half duplex where, after multiple collisions and retries, TX halts. Signed-off-by: Harini Katakam <[email protected]> Signed-off-by: Michal Simek <[email protected]> Signed-off-by: Radhey Shyam Pandey <[email protected]> Reviewed-by: Michal Swiatkowski <[email protected]> Acked-by: Nicolas Ferre <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19ixgb: Remove ixgb driverTony Nguyen13-6292/+0
There are likely no users of this driver as the hardware has been discontinued since 2010. Remove the driver and all references to it in documentation. Suggested-by: Jakub Kicinski <[email protected]> Signed-off-by: Tony Nguyen <[email protected]> Acked-by: Jesse Brandeburg <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19net: mdio: fix owner field for mdio buses registered using ACPIFlorian Fainelli1-4/+6
Bus ownership is wrong when using acpi_mdiobus_register() to register an mdio bus. That function is not inline, so when it calls mdiobus_register() the wrong THIS_MODULE value is captured. CC: Maxime Bizon <[email protected]> Fixes: 803ca24d2f92 ("net: mdio: Add ACPI support code for mdio") Signed-off-by: Florian Fainelli <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19net: mdio: fix owner field for mdio buses registered using device-treeMaxime Bizon2-10/+13
Bus ownership is wrong when using of_mdiobus_register() to register an mdio bus. That function is not inline, so when it calls mdiobus_register() the wrong THIS_MODULE value is captured. Signed-off-by: Maxime Bizon <[email protected]> Fixes: 90eff9096c01 ("net: phy: Allow splitting MDIO bus/device support from PHYs") [florian: fix kdoc, added Fixes tag] Signed-off-by: Florian Fainelli <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19net: phy: Ensure state transitions are processed from phy_stop()Florian Fainelli1-7/+16
In the phy_disconnect() -> phy_stop() path, we will be forcibly setting the PHY state machine to PHY_HALTED. This invalidates the old_state != phydev->state condition in phy_state_machine() such that we will neither display the state change for debugging, nor will we invoke the link_change_notify() callback. Factor the code by introducing phy_process_state_change(), and ensure that we process the state change from phy_stop() as well. Fixes: 5c5f626bcace ("net: phy: improve handling link_change_notify callback") Signed-off-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19Merge branch '1GbE' of ↵David S. Miller4-94/+84
git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue Tony Nguyen says: ==================== Intel Wired LAN Driver Updates 2023-03-16 (igb, igbvf, igc) This series contains updates to igb, igbvf, and igc drivers. Lin Ma removes rtnl_lock() when disabling SRIOV on remove which was causing deadlock on igb. Akihiko Odaki delays enabling of SRIOV on igb to prevent early messages that could get ignored and clears MAC address when PF returns nack on reset; indicating no MAC address was assigned for igbvf. Gaosheng Cui frees IRQs in error path for igbvf. Akashi Takahiro fixes logic on checking TAPRIO gate support for igc. ==================== Signed-off-by: David S. Miller <[email protected]>
2023-03-19xirc2ps_cs: Fix use after free bug in xirc2ps_detachZheng Wang1-0/+5
In xirc2ps_probe, the local->tx_timeout_task was bounded with xirc2ps_tx_timeout_task. When timeout occurs, it will call xirc_tx_timeout->schedule_work to start the work. When we call xirc2ps_detach to remove the driver, there may be a sequence as follows: Stop responding to timeout tasks and complete scheduled tasks before cleanup in xirc2ps_detach, which will fix the problem. CPU0 CPU1 |xirc2ps_tx_timeout_task xirc2ps_detach | free_netdev | kfree(dev); | | | do_reset | //use dev Fixes: 1da177e4c3f4 ("Linux-2.6.12-rc2") Signed-off-by: Zheng Wang <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19net: phy: at803x: Replace of_gpio.h with what indeed is usedAndy Shevchenko1-2/+1
of_gpio.h in this driver is solely used as a proxy to other headers. This is incorrect usage of the of_gpio.h. Replace it .h with what indeed is used in the code. Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2023-03-19net: smc91x: Replace of_gpio.h with what indeed is usedAndy Shevchenko1-1/+1
of_gpio.h in this driver is solely used as a proxy to other headers. This is incorrect usage of the of_gpio.h. Replace it .h with what indeed is used in the code. Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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