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2024-03-05net: phy: Add phydev->enable_tx_lpi to simplify adjust link callbacksAndrew Lunn1-0/+7
MAC drivers which support EEE need to know the results of the EEE auto-neg in order to program the hardware to perform EEE or not. The oddly named phy_init_eee() can be used to determine this, it returns 0 if EEE should be used, or a negative error code, e.g. -EOPPROTONOTSUPPORT if the PHY does not support EEE or negotiate resulted in it not being used. However, many MAC drivers get this wrong. Add phydev->enable_tx_lpi which indicates the result of the autoneg for EEE, including if EEE is administratively disabled with ethtool. The MAC driver can then access this in the same way as link speed and duplex in the adjust link callback. If enable_tx_lpi is true, the MAC should send low power indications and does not need to consider anything else with respect to EEE. Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: Oleksij Rempel <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-03-05net: phy: micrel: lan8814 cable improvement errataHoratiu Vultur1-0/+19
When the length of the cable is more than 100m and the lan8814 is configured to run in 1000Base-T Slave then the register of the device needs to be optimized. Workaround this by setting the measure time to a value of 0xb. This value can be set regardless of the configuration. This issue is described in 'LAN8814 Silicon Errata and Data Sheet Clarification' and according to that, this will not be corrected in a future silicon revision. Reviewed-by: Wojciech Drewek <[email protected]> Signed-off-by: Horatiu Vultur <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Acked-by: Arun Ramadoss <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-03-05net: phy: micrel: lan8814 led errataHoratiu Vultur1-0/+19
Lan8814 phy led behavior is not correct. It was noticed that the led still remains ON when the cable is unplugged while there was traffic passing at that time. The fix consists in clearing bit 10 of register 0x38, in this way the led behaviour is correct and gets OFF when there is no link. Reviewed-by: Wojciech Drewek <[email protected]> Signed-off-by: Horatiu Vultur <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-03-01net: phy: qcom: qca808x: fill in possible_interfacesRobert Marko1-0/+12
Currently QCA808x driver does not fill the possible_interfaces. 2.5G QCA808x support SGMII and 2500Base-X while 1G model only supports SGMII, so fill the possible_interfaces accordingly. Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Russell King (Oracle) <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-03-01net: phy: qcom: qca808x: add helper for checking for 1G only modelRobert Marko1-5/+12
There are 2 versions of QCA808x, one 2.5G capable and one 1G capable. Currently, this matter only in the .get_features call however, it will be required for filling supported interface modes so lets add a helper that can be reused. Signed-off-by: Robert Marko <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-28net: phy: dp83826: disable WOL at initCatalin Popescu1-1/+1
Commit d1d77120bc28 ("net: phy: dp83826: support TX data voltage tuning") introduced a regression in that WOL is not disabled by default for DP83826. WOL should normally be enabled through ethtool. Fixes: d1d77120bc28 ("net: phy: dp83826: support TX data voltage tuning") Signed-off-by: Catalin Popescu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-27net: phy: simplify genphy_c45_ethtool_set_eeeHeiner Kallweit1-9/+4
Simplify the function, no functional change intended. - Remove not needed variable unsupp, I think code is even better readable now. - Move setting phydev->eee_enabled out of the if clause - Simplify return value handling Signed-off-by: Heiner Kallweit <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2024-02-26net: phy: dp83826: support configuring RMII master/slave operation modeJérémie Dautheribes1-5/+38
The TI DP83826 PHY can operate between two RMII modes: - master mode (PHY operates from a 25MHz clock reference) - slave mode (PHY operates from a 50MHz clock reference) By default, the operation mode is configured by hardware straps. Add support to configure the operation mode from within the driver. Signed-off-by: Jérémie Dautheribes <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-26net: phy: dp83826: Add support for phy-mode configurationJérémie Dautheribes1-0/+11
The TI DP83826 PHY can operate in either MII mode or RMII mode. By default, it is configured by straps. It can also be configured by writing to the bit 5 of register 0x17 - RMII and Status Register (RCSR). When phydev->interface is rmii, rmii mode must be enabled, otherwise mii mode must be set. This prevents misconfiguration of hw straps. Signed-off-by: Jérémie Dautheribes <[email protected]> Reviewed-by: Maxime Chevallier <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-22Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-1/+3
Cross-merge networking fixes after downstream PR. Conflicts: net/ipv4/udp.c f796feabb9f5 ("udp: add local "peek offset enabled" flag") 56667da7399e ("net: implement lockless setsockopt(SO_PEEK_OFF)") Adjacent changes: net/unix/garbage.c aa82ac51d633 ("af_unix: Drop oob_skb ref before purging queue in GC.") 11498715f266 ("af_unix: Remove io_uring code for GC.") Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-22net: phy: realtek: Fix rtl8211f_config_init() for RTL8211F(D)(I)-VD-CG PHYSiddharth Vadapalli1-1/+3
Commit bb726b753f75 ("net: phy: realtek: add support for RTL8211F(D)(I)-VD-CG") extended support of the driver from the existing support for RTL8211F(D)(I)-CG PHY to the newer RTL8211F(D)(I)-VD-CG PHY. While that commit indicated that the RTL8211F_PHYCR2 register is not supported by the "VD-CG" PHY model and therefore updated the corresponding section in rtl8211f_config_init() to be invoked conditionally, the call to "genphy_soft_reset()" was left as-is, when it should have also been invoked conditionally. This is because the call to "genphy_soft_reset()" was first introduced by the commit 0a4355c2b7f8 ("net: phy: realtek: add dt property to disable CLKOUT clock") since the RTL8211F guide indicates that a PHY reset should be issued after setting bits in the PHYCR2 register. As the PHYCR2 register is not applicable to the "VD-CG" PHY model, fix the rtl8211f_config_init() function by invoking "genphy_soft_reset()" conditionally based on the presence of the "PHYCR2" register. Fixes: bb726b753f75 ("net: phy: realtek: add support for RTL8211F(D)(I)-VD-CG") Signed-off-by: Siddharth Vadapalli <[email protected]> Reviewed-by: Simon Horman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: move interrupt configurationDimitri Fedrau1-8/+8
Move interrupt configuration from mv88q222x_revb0_config_init to mv88q2xxx_config_init. Same register and bits are used for the 88q2xxx devices. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Stefan Eichenberger <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: remove duplicated assignment of pma_extableDimitri Fedrau1-7/+1
Remove assignment of phydev->pma_extable in mv88q222x_revb0_config_init. It is already done in mv88q2xxx_config_init, just call mv88q2xxx_config_init. Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: cleanup mv88q2xxx_config_initDimitri Fedrau1-8/+1
mv88q2xxx_config_init calls genphy_c45_read_pma which is done by mv88q2xxx_read_status, it calls also mv88q2xxx_config_aneg which is also called by the PHY state machine. Let the PHY state machine handle the phydriver ops in their intendend way. Reviewed-by: Andrew Lunn <[email protected]> Tested-by: Stefan Eichenberger <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: switch to mv88q2xxx_config_anegDimitri Fedrau1-12/+1
Switch to mv88q2xxx_config_aneg for Marvell 88Q2220 devices and remove the mv88q222x_config_aneg function which is basically a copy of the mv88q2xxx_config_aneg function. Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: make mv88q2xxx_config_aneg genericDimitri Fedrau1-1/+1
Marvell 88Q2xxx devices follow the same scheme, after configuration they need a soft reset. Soft resets differ between devices, so we use the .soft_reset callback instead of creating .config_aneg callbacks for each device. Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: add cable test supportDimitri Fedrau1-0/+107
Add cable test support for Marvell 88Q222x devices. Reported distance granularity is 1m. 1m cable, open: Cable test started for device eth0. Cable test completed for device eth0. Pair A code Open Circuit Pair A, fault length: 1.00m 1m cable, shorted: Cable test started for device eth0. Cable test completed for device eth0. Pair A code Short within Pair Pair A, fault length: 1.00m 6m cable, open: Cable test started for device eth0. Cable test completed for device eth0. Pair A code Open Circuit Pair A, fault length: 6.00m 6m cable, shorted: Cable test started for device eth0. Cable test completed for device eth0. Pair A code Short within Pair Pair A, fault length: 6.00m Signed-off-by: Dimitri Fedrau <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: add support for temperature sensorDimitri Fedrau2-0/+147
Marvell 88q2xxx devices have an inbuilt temperature sensor. Add hwmon support for this sensor. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Guenter Roeck <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: add suspend / resume opsDimitri Fedrau1-0/+34
Add suspend/resume ops for Marvell 88Q2xxx devices. Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: add interrupt support for link detectionDimitri Fedrau1-4/+119
Added .config_intr and .handle_interrupt callbacks. Whenever the link goes up or down an interrupt will be triggered. Interrupts are configured separately for 100/1000BASET1. Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: add driver for the Marvell 88Q2220 PHYDimitri Fedrau1-6/+204
Add a driver for the Marvell 88Q2220. This driver allows to detect the link, switch between 100BASE-T1 and 1000BASE-T1 and switch between master and slave mode. Autonegotiation is supported. Reviewed-by: Andrew Lunn <[email protected]> Tested-by: Gregor Herburger <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: marvell-88q2xxx: fix typosDimitri Fedrau1-11/+17
Rename mv88q2xxxx_get_sqi to mv88q2xxx_get_sqi and mv88q2xxxx_get_sqi_max to mv88q2xxx_get_sqi_max. Fix linebreaks and use everywhere hexadecimal numbers written with lowercase letters instead of mixing it up. Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: c45: detect 100/1000BASE-T1 linkmode advertisementsDimitri Fedrau1-1/+2
Set 100BT1 and 1000BT1 linkmode advertisement bits to adv_l_mask to enable detection. Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Dimitri Fedrau <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-21net: phy: mxl-gpy: fill in possible_interfaces for GPY21x chipsetRaju Lakkaraju1-6/+14
Fill in the possible_interfaces member. GPY21x phys support the SGMII and 2500base-X interfaces Signed-off-by: Raju Lakkaraju <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-18net: phy: aquantia: add AQR813 PHY IDChristian Marangi1-0/+21
Aquantia AQR813 is the Octal Port variant of the AQR113. Add PHY ID for it to provide support for it. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-17net: phy: c45: add support for MDIO_AN_EEE_ADV2Heiner Kallweit1-0/+27
Add support for handling the EEE advertisement 2 register. For now only 2500baseT and 5000baseT modes are supported. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-17net: phy: c45: add support for EEE link partner ability 2 to ↵Heiner Kallweit1-0/+11
genphy_c45_read_eee_lpa Add support for reading EEE link partner ability 2 register. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-17net: phy: c45: add and use genphy_c45_read_eee_cap2Heiner Kallweit1-0/+31
Add and use genphy_c45_read_eee_cap2(), complementing genphy_c45_read_eee_cap1(). Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-17net: phy: add PHY_EEE_CAP2_FEATURESHeiner Kallweit1-0/+11
As a prerequisite for adding EEE CAP2 register support, complement PHY_EEE_CAP1_FEATURES with PHY_EEE_CAP2_FEATURES. For now only 2500baseT and 5000baseT modes are supported. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-16net: phy: aquantia: add AQR113 PHY IDChristian Marangi1-0/+21
Add Aquantia AQR113 PHY ID. Aquantia AQR113 is just a chip size variant of the already supported AQR133C where the only difference is the PHY ID and the hw chip size. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-15Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-0/+1
Cross-merge networking fixes after downstream PR. No conflicts. Adjacent changes: net/core/dev.c 9f30831390ed ("net: add rcu safety to rtnl_prop_list_size()") 723de3ebef03 ("net: free altname using an RCU callback") net/unix/garbage.c 11498715f266 ("af_unix: Remove io_uring code for GC.") 25236c91b5ab ("af_unix: Fix task hung while purging oob_skb in GC.") drivers/net/ethernet/renesas/ravb_main.c ed4adc07207d ("net: ravb: Count packets instead of descriptors in GbEth RX path" ) c2da9408579d ("ravb: Add Rx checksum offload support for GbEth") net/mptcp/protocol.c bdd70eb68913 ("mptcp: drop the push_pending field") 28e5c1380506 ("mptcp: annotate lockless accesses around read-mostly fields") Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-15net: fill in MODULE_DESCRIPTION()s for mdio_devresBreno Leitao1-0/+1
W=1 builds now warn if module is built without a MODULE_DESCRIPTION(). Add descriptions to the PHY MDIO helpers. Suggested-by: Andrew Lunn <[email protected]> Signed-off-by: Breno Leitao <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-15net: mdio_bus: make mdio_bus_type constRicardo B. Marliere2-3/+2
Since commit d492cc2573a0 ("driver core: device.h: make struct bus_type a const *"), the driver core can properly handle constant struct bus_type, move the mdio_bus_type variable to be a constant structure as well, placing it into read-only memory which can not be modified at runtime. Cc: Greg Kroah-Hartman <[email protected]> Suggested-by: Greg Kroah-Hartman <[email protected]> Signed-off-by: Ricardo B. Marliere <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Greg Kroah-Hartman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2024-02-15net: phy: aquantia: add AQR111 and AQR111B0 PHY IDChristian Marangi1-0/+52
Add Aquantia AQR111 and AQR111B0 PHY ID. These PHY advertise 10G speed but actually supports up to 5G speed, hence some manual fixup is needed. The Aquantia AQR111B0 PHY is just a variant of the AQR111 with smaller chip size. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2024-02-15net: phy: qca807x: move interface mode check to .config_init_onceRobert Marko1-5/+5
Currently, we are checking whether the PHY package mode matches the individual PHY interface modes at PHY package probe time, but at that time we only know the PHY package mode and not the individual PHY interface modes as of_get_phy_mode() that populates it will only get called once the netdev to which PHY-s are attached to is being probed and thus this check will always fail and return -EINVAL. So, lets move this check to .config_init_once as at that point individual PHY interface modes should be populated. Fixes: d1cb613efbd3 ("net: phy: qcom: add support for QCA807x PHY Family") Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2024-02-14net: phy: dp83826: support TX data voltage tuningCatalin Popescu1-4/+126
DP83826 offers the possibility to tune the voltage of logical levels of the MLT-3 encoded TX data. This is useful when there is a voltage drop in between the PHY and the connector and we want to increase the voltage levels to compensate for that drop. Prior to PHY configuration, the driver SW resets the PHY which has the same effect as the HW reset pin according to the datasheet. Hence, there's no need to force update the VOD_CFG registers to make sure they hold their reset values. VOD_CFG registers need to be updated only if the DT has been configured with values other than the reset ones. Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Catalin Popescu <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-13net: phy: aquantia: clear PMD Global Transmit Disable bit during initRobert Marko1-0/+9
PMD Global Transmit Disable bit should be cleared for normal operation. This should be HW default, however I found that on Asus RT-AX89X that uses AQR113C PHY and firmware 5.4 this bit is set by default. With this bit set the AQR cannot achieve a link with its link-partner and it took me multiple hours of digging through the vendor GPL source to find this out, so lets always clear this bit during .config_init() to avoid a situation like this in the future. Signed-off-by: Robert Marko <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2024-02-10net: phy: qca807x: add support for configurable LEDChristian Marangi1-2/+254
QCA8072/5 have up to 2 LEDs attached for PHY. LEDs can be configured to be ON/hw blink or be set to HW control. Hw blink mode is set to blink at 4Hz or 250ms. PHY can support both copper (TP) or fiber (FIBRE) kind and supports different HW control modes based on the port type. HW control modes supported for netdev trigger for copper ports are: - LINK_10 - LINK_100 - LINK_1000 - TX - RX - FULL_DUPLEX - HALF_DUPLEX HW control modes supported for netdev trigger for fiber ports are: - LINK_100 - LINK_1000 - TX - RX - FULL_DUPLEX - HALF_DUPLEX LED support conflicts with GPIO controller feature and must be disabled if gpio-controller is used for the PHY. Signed-off-by: Christian Marangi <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-10net: phy: qcom: generalize some qca808x LED functionsChristian Marangi3-34/+65
Generalize some qca808x LED functions in preparation for qca807x LED support. The LED implementation of qca808x and qca807x is the same but qca807x supports also Fiber port and have different hw control bits for Fiber port. To limit code duplication introduce micro functions that takes reg instead of LED index to tweak all the supported LED modes. Signed-off-by: Christian Marangi <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-10net: phy: qcom: move common qca808x LED define to shared headerChristian Marangi2-65/+65
The LED implementation of qca808x and qca807x is the same but qca807x supports also Fiber port and have different hw control bits for Fiber port. In preparation for qca807x introduction, move all the common define to shared header. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-10net: phy: qcom: add support for QCA807x PHY FamilyRobert Marko3-0/+606
This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s. They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te, 100BASE-TX and 1000BASE-T PHY-s. They feature 2 SerDes, one for PSGMII or QSGMII connection with MAC, while second one is SGMII for connection to MAC or fiber. Both models have a combo port that supports 1000BASE-X and 100BASE-FX fiber. PHY package can be configured in 3 mode following this table: First Serdes mode Second Serdes mode Option 1 PSGMII for copper Disabled ports 0-4 Option 2 PSGMII for copper 1000BASE-X / 100BASE-FX ports 0-4 Option 3 QSGMII for copper SGMII for ports 0-3 copper port 4 Each PHY inside of QCA807x series has 4 digitally controlled output only pins that natively drive LED-s. But some vendors used these to driver generic LED-s controlled by userspace, so lets enable registering each PHY as GPIO controller and add driver for it. These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x boards. Co-developed-by: Christian Marangi <[email protected]> Signed-off-by: Robert Marko <[email protected]> Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-10net: phy: provide whether link has changed in c37_read_statusChristian Marangi3-4/+13
Some PHY driver might require additional regs call after genphy_c37_read_status() is called. Expand genphy_c37_read_status to provide a bool wheather the link has changed or not to permit PHY driver to skip additional regs call if nothing has changed. Every user of genphy_c37_read_status() is updated with the new additional bool. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-10net: phy: qcom: move more function to shared libraryChristian Marangi4-240/+244
Move more function to shared library in preparation for introduction of new PHY Family qca807x that will make use of both functions from at803x and qca808x as it's a transition PHY with some implementation of at803x and some from the new qca808x. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-10net: phy: add devm/of_phy_package_join helperChristian Marangi1-0/+96
Add devm/of_phy_package_join helper to join PHYs in a PHY package. These are variant of the manual phy_package_join with the difference that these will use DT nodes to derive the base_addr instead of manually passing an hardcoded value. An additional value is added in phy_package_shared, "np" to reference the PHY package node pointer in specific PHY driver probe_once and config_init_once functions to make use of additional specific properties defined in the PHY package node in DT. The np value is filled only with of_phy_package_join if a valid PHY package node is found. A valid PHY package node must have the node name set to "ethernet-phy-package". Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-10net: phy: add support for scanning PHY in PHY packages nodesChristian Marangi1-8/+36
Add support for scanning PHY in PHY package nodes. PHY packages nodes are just container for actual PHY on the MDIO bus. Their PHY address defined in the PHY package node are absolute and reflect the address on the MDIO bus. mdio_bus.c and of_mdio.c is updated to now support and parse also PHY package subnode by checking if the node name match "ethernet-phy-package". As PHY package reg is mandatory and each PHY in the PHY package must have a reg, every invalid PHY Package node is ignored and will be skipped by the autoscan fallback. Signed-off-by: Christian Marangi <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-09net: phy: realtek: use generic MDIO helpers to simplify the codeHeiner Kallweit1-17/+3
Use generic MDIO helpers to simplify the code. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-07net: phy: realtek: add 5Gbps support to rtl822x_config_aneg()Heiner Kallweit1-4/+8
RTL8126 as an evolution of RTL8125 supports 5Gbps. rtl822x_config_aneg() is used by the PHY driver for the integrated PHY, therefore add 5Gbps support to it. Signed-off-by: Heiner Kallweit <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-07net: phy: realtek: use generic MDIO constantsMarek Behún1-17/+13
Drop the ad-hoc MDIO constants used in the driver and use generic constants instead. Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2024-02-07net: phy: c45 scanning: Don't consider -ENODEV fatalAndrew Lunn1-2/+6
When scanning the MDIO bus for C22 devices, the driver returning -ENODEV is not considered fatal, it just indicates the MDIO bus master knows there is no device at that address, maybe because of hardware limitation. Make the C45 scan code act on -ENODEV the same way, to make C22 and C45 more uniform. It is expected all reads for a given address will return -ENODEV, so within get_phy_c45_ids() only the first place a read occurs has been changed. Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2024-02-06net: phy: add helper phy_advertise_eee_allHeiner Kallweit1-0/+16
Per default phylib preserves the EEE advertising at the time of phy probing. The EEE advertising can be changed from user space, in addition this helper allows to set the EEE advertising to all supported modes from drivers in kernel space. Suggested-by: Andrew Lunn <[email protected]> Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
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