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2019-04-02net: phy: realtek: use genphy_read_abilitiesHeiner Kallweit1-24/+12
Use new function genphy_read_abilities(). This allows to remove all calls to genphy_config_init(). Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-04-02net: phy: use genphy_read_abilities in genphy driverHeiner Kallweit1-2/+1
Currently the genphy driver populates phydev->supported like this: First all possible feature bits are set, then genphy_config_init() reads the available features from the chip and remove all unsupported features from phydev->supported. This can be simplified by using genphy_read_abilities(). Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-04-02net: phy: add genphy_read_abilitiesHeiner Kallweit1-0/+48
Similar to genphy_c45_pma_read_abilities() add a function to dynamically detect the abilities of a Clause 22 PHY. This is mainly copied from genphy_config_init(). Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-04-01net: phy: aquantia: add SGMII statisticsHeiner Kallweit1-2/+112
The AQR107 family has SGMII statistics counters. Let's expose them to ethtool. To interpret the counters correctly one has to be aware that rx on SGMII side is tx on ethernet side. The counters are populated by the chip in 100Mbps/1Gbps mode only. v2: - add constant AQR107_SGMII_STAT_SZ - add struct aqr107_priv to be prepared for more private data fields - let aqr107_get_stat() return U64_MAX in case of an error Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-04-01net: phy: improve genphy_read_statusHeiner Kallweit1-15/+8
This patch improves few aspects of genphy_read_status(): - Don't initialize lpagb, it's not needed. - Move initializing phydev->speed et al before the if clause. - In auto-neg case, skip populating lp_advertising if we don't have a link. This avoids quite some unnecessary MDIO reads in case of phylib polling mode. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-04-01net: phy: aquantia: add suspend / resume callbacks for AQR107 familyHeiner Kallweit1-0/+16
Add suspend / resume callbacks for AQR107 family. Suspend powers down the complete chip except MDIO and internal CPU. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-27Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller4-15/+37
2019-03-27net: phy: mdio-bcm-unimac: remove redundant !timeout checkColin Ian King1-4/+1
The check for zero timeout is always true at the end of the proceeding while loop; the only other exit path in the loop is if the unimac MDIO is not busy. Remove the redundant zero timeout check and always return -ETIMEDOUT on this timeout return path. Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-27net: phy: marvell: add PHY tunable fast link down support for 88E1540Heiner Kallweit1-0/+108
1000BaseT standard requires that a link is reported as down earliest after 750ms. Several use case however require a much faster detecion of a broken link. Fast Link Down supports this by intentionally violating a the standard. This patch exposes the Fast Link Down feature of 88E1540 and 88E6390. These PHY's can be found as internal PHY's in several switches: 88E6352, 88E6240, 88E6176, 88E6172, and 88E6390(X). Fast Link Down and EEE are mutually exclusive. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-26net: phy: aquantia: inform about proprietary 1000Base-T2 mode being in useHeiner Kallweit1-1/+13
The AQCS109 supports a proprietary 2-pair 1Gbps mode. The standard registers don't allow to tell between 1000BaseT and 1000BaseT2. Add reporting this proprietary mode based on a vendor register. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-26net: phy: aquantia: report PHY details like firmware versionHeiner Kallweit1-0/+62
Add reporting firmware details. These details are available only once the firmware has finished initializing the chip. This can take some time and we need to poll for init completion. v2: - Propagate timeout in aqr107_wait_reset_complete(). Don't bail out completely on timeout because chip may be functional even w/o firmware image. Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-26net: phy: aquantia: print remote capabilities if link partner is Aquantia PHYHeiner Kallweit1-0/+49
If both link partners are Aquantia PHY's then additional information is exchanged as part of the auto-negotiation. Report remote capabilities if link partner is Aquantia PHY. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-26net: phy: bcm54xx: Encode link speed and activity into LEDsVladimir Oltean1-0/+13
Previously the green and amber LEDs on this quad PHY were solid, to indicate an encoding of the link speed (10/100/1000). This keeps the LEDs always on just as before, but now they flash on Rx/Tx activity. Signed-off-by: Vladimir Oltean <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-26net: phy: aquantia: simplify aqr_config_anegHeiner Kallweit1-32/+13
Simplify aqr_config_aneg(). Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-25net: phy: don't clear BMCR in genphy_soft_resetHeiner Kallweit1-1/+1
So far we effectively clear the BMCR register. Some PHY's can deal with this (e.g. because they reset BMCR to a default as part of a soft-reset) whilst on others this causes issues because e.g. the autoneg bit is cleared. Marvell is an example, see also thread [0]. So let's be a little bit more gentle and leave all bits we're not interested in as-is. This change is needed for PHY drivers to properly deal with the original patch. [0] https://marc.info/?t=155264050700001&r=1&w=2 Fixes: 6e2d85ec0559 ("net: phy: Stop with excessive soft reset") Tested-by: Phil Reid <[email protected]> Tested-by: liweihang <[email protected]> Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-23net: phy: Re-parent menus for MDIO bus drivers correctlyFlorian Fainelli1-0/+3
After 90eff9096c01 ("net: phy: Allow splitting MDIO bus/device support from PHYs") the various MDIO bus drivers were no longer parented with config PHYLIB but with config MDIO_BUS which is not a menuconfig, fix this by depending on MDIO_DEVICE which is a menuconfig. This is visually nicer and less confusing for users. Fixes: 90eff9096c01 ("net: phy: Allow splitting MDIO bus/device support from PHYs") Signed-off-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-23net: phy: Correct Cygnus/Omega PHY driver promptFlorian Fainelli1-2/+1
The tristate prompt should have been replaced rather than defined a few lines below, rebase mistake. Fixes: 17cc9821766c ("net: phy: Move Omega PHY entry to Cygnus PHY driver") Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-22net: phy: aquantia: add downshift supportHeiner Kallweit1-10/+145
Aquantia PHY's of the AQR107 family support the downshift feature. Add support for it as standard PHY tunable so that it can be controlled via ethtool. The AQCS109 supports a proprietary 2-pair 1Gbps mode. If two such PHY's are connected to each other with a 2-pair cable, they may not be able to establish a link if both advertise modes > 1Gbps. v2: - add downshift event detection - warn if downshift occurred - read downshifted rate from vendor register - enable downshift per default on all AQR107 family members Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-21net: phy: Move Omega PHY entry to Cygnus PHY driverFlorian Fainelli3-4/+149
Cygnus and Omega are part of the same business unit and product line, it makes sense to group PHY entries by products such that a platform can select only the drivers that it needs. Bring all the functionality that the BCM7XXX_28NM_GPHY() macro hides for us and remove the Omega PHY entry from bcm7xxx.c. As an added bonus, we now have a proper mdio_device_id entry to permit auto-loading. Signed-off-by: Florian Fainelli <[email protected]> Reviewed-by: Scott Branden <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-21net: phy: Prepare for moving Omega out of bcm7xxxFlorian Fainelli3-71/+76
The Omega PHY entry was added to bcm7xxx.c out of convenience and this breaks the one driver per product line paradigm that was applied up until now. Since the AFE initialization is shared between Omega and BCM7xxx move the relevant functions to bcm-phy-lib.[ch]. No functional changes introduced. Signed-off-by: Florian Fainelli <[email protected]> Reviewed-by: Scott Branden <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-21net: phy: mdio-bcm-unimac: Remove print of base addressFlorian Fainelli1-1/+1
Since commit ad67b74d2469 ("printk: hash addresses printed with %p") pointers are being hashed when printed. Displaying the virtual memory at bootup time is not helpful, especially given we use a dev_info() which already displays the platform device's address. Signed-off-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-21net: phy: Add DP83825I to the DP83822 driverDan Murphy1-14/+20
Add the DP83825I ethernet PHY to the DP83822 driver. These devices share the same WoL register bits and addresses. The phy_driver init was made into a macro as there may be future devices appended to this driver that will share the register space. http://www.ti.com/lit/gpn/dp83825i Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Dan Murphy <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-20net: phy: aquantia: check for changed interface mode in read_statusNikita Yushchenko1-2/+44
Depending on the auto-negotiated speed the PHY may change the interface mode. Check for new mode and set phydev->interface accordingly. Signed-off-by: Nikita Yushchenko <[email protected]> Signed-off-by: Andrew Lunn <[email protected]> [[email protected]: picked from bigger patch and reworked] Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-20net: phy: aquantia: check for supported interface modes in config_initAndrew Lunn1-0/+17
Let config_init check for unsupported interface modes on AQR107/AQCS109. Signed-off-by: Andrew Lunn <[email protected]> [[email protected]: adjusted for AQR107/AQCS109 specifics] Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-20net: phy: improve handling link_change_notify callbackHeiner Kallweit3-50/+15
Currently the Phy driver's link_change_notify callback is called whenever the state machine is run (every second if polling), no matter whether the state changed or not. This isn't needed and may confuse users considering the name of the callback. Actually it contradicts its kernel-doc description. Therefore let's change the behavior and call this callback only in case of an actual state change. This requires changes to the at803x and rockchip drivers. at803x can be simplified so that it reacts on a state change to PHY_NOLINK only. The rockchip driver can also be much simplified. We simply re-init the AFE/DSP registers whenever we change to PHY_RUNNING and speed is 100Mbps. This causes very small overhead because we do this even if the speed was 100Mbps already. But this is negligible and I think justified by the much simpler code. Changes are compile-tested only. A little bit problematic seems to be to find somebody with the hardware to test the changes to the two PHY drivers. See also [0]. David may be able to test the Rockchip driver. [0] https://marc.info/?t=153782508800006&r=1&w=2 Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-15net: phy: meson-gxl: fix interrupt supportJerome Brunet1-0/+6
If an interrupt is already pending when the interrupt is enabled on the GXL phy, no IRQ will ever be triggered. The fix is simply to make sure pending IRQs are cleared before setting up the irq mask. Fixes: cf127ff20af1 ("net: phy: meson-gxl: add interrupt support") Signed-off-by: Jerome Brunet <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-04phy: mdio-mux: fix Kconfig dependenciesArnd Bergmann1-1/+1
MDIO_BUS_MUX can only be selected if OF_MDIO is already turned on: WARNING: unmet direct dependencies detected for MDIO_BUS_MUX Depends on [n]: NETDEVICES [=y] && MDIO_BUS [=m] && OF_MDIO [=n] Selected by [m]: - MDIO_BUS_MUX_MULTIPLEXER [=m] && NETDEVICES [=y] && MDIO_BUS [=m] && OF [=y] Fixes: 7865ad6551c9 ("drivers: net: phy: mdio-mux: Add support for Generic Mux controls") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-04net: phy: use phy_modify_mmd_changed in genphy_c45_an_config_anegHeiner Kallweit1-9/+8
As can be seen from the usage of the return value, we should use phy_modify_mmd_changed() here. Fixes: 9a5dc8af4416 ("net: phy: add genphy_c45_an_config_aneg") Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-03net: phy: remove gen10g_no_soft_resetHeiner Kallweit4-12/+5
genphy_no_soft_reset and gen10g_no_soft_reset are both the same no-ops, one is enough. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-03net: phy: don't export gen10g_read_statusHeiner Kallweit1-2/+1
gen10g_read_status is deprecated, therefore stop exporting it. We don't want to encourage anybody to use it. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-03net: phy: remove gen10g_config_initHeiner Kallweit3-16/+0
ETHTOOL_LINK_MODE_10000baseT_Full_BIT is set anyway in the supported and advertising bitmap because it's part of PHY_10GBIT_FEATURES. And all users of gen10g_config_init use PHY_10GBIT_FEATURES. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-03net: phy: remove gen10g_suspend and gen10g_resumeHeiner Kallweit1-14/+0
phy_suspend() and phy_resume() are no-ops anyway if no callback is defined. Therefore we don't need these stubs. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-03net: phy: use genphy_c45_aneg_done in genphy_aneg_doneHeiner Kallweit1-8/+4
Now that we have it let's use genphy_c45_aneg_done() in phy_aneg_done(). Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-03-02Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller3-1/+19
2019-03-01net: phy: phylink: fix uninitialized variable in phylink_get_mac_stateHeiner Kallweit1-0/+4
When debugging an issue I found implausible values in state->pause. Reason in that state->pause isn't initialized and later only single bits are changed. Also the struct itself isn't initialized in phylink_resolve(). So better initialize state->pause and other not yet initialized fields. v2: - use right function name in subject v3: - initialize additional fields Fixes: 9525ae83959b ("phylink: add phylink infrastructure") Signed-off-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-27net: phy: marvell10g: Use the generic C45 helper to read the 2110 featuresMaxime Chevallier1-1/+1
Contrary to the 3310, the 2110 PHY correctly reports it's 2.5G/5G abilities. We can therefore use the genphy_c45_pma_read_abilities helper to build the list of features. Signed-off-by: Maxime Chevallier <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-27net: phy: marvell10g: Let genphy_c45_pma_read_abilities set Aneg bitMaxime Chevallier1-10/+0
The genphy_c45_pma_read_abilities helper now sets the Autoneg ability in phydev->supported according to what the AN MMD reports. We therefore don't need to manually do that in mv3310_get_features(). Signed-off-by: Maxime Chevallier <[email protected]> Suggested-by: Heiner Kallweit <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-27net: phy: dp83867: add soft reset delayMax Uvarov1-0/+3
Similar to dp83640 delay after soft reset is needed to set up registers correctly. Signed-off-by: Max Uvarov <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-27drivers: net: phy: mdio-mux: Add support for Generic Mux controlsPankaj Bansal3-0/+135
Add support for Generic Mux controls, when Mdio mux node is a consumer of mux produced by some other device. Signed-off-by: Pankaj Bansal <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-27net: phy: Micrel KSZ8061: link failure after cable connectRajasingh Thavamani1-1/+12
With Micrel KSZ8061 PHY, the link may occasionally not come up after Ethernet cable connect. The vendor's (Microchip, former Micrel) errata sheet 80000688A.pdf descripes the problem and possible workarounds in detail, see below. The batch implements workaround 1, which permanently fixes the issue. DESCRIPTION Link-up may not occur properly when the Ethernet cable is initially connected. This issue occurs more commonly when the cable is connected slowly, but it may occur any time a cable is connected. This issue occurs in the auto-negotiation circuit, and will not occur if auto-negotiation is disabled (which requires that the two link partners be set to the same speed and duplex). END USER IMPLICATIONS When this issue occurs, link is not established. Subsequent cable plug/unplaug cycle will not correct the issue. WORk AROUND There are four approaches to work around this issue: 1. This issue can be prevented by setting bit 15 in MMD device address 1, register 2, prior to connecting the cable or prior to setting the Restart Auto-negotiation bit in register 0h. The MMD registers are accessed via the indirect access registers Dh and Eh, or via the Micrel EthUtil utility as shown here: . if using the EthUtil utility (usually with a Micrel KSZ8061 Evaluation Board), type the following commands: > address 1 > mmd 1 > iw 2 b61a . Alternatively, write the following registers to write to the indirect MMD register: Write register Dh, data 0001h Write register Eh, data 0002h Write register Dh, data 4001h Write register Eh, data B61Ah 2. The issue can be avoided by disabling auto-negotiation in the KSZ8061, either by the strapping option, or by clearing bit 12 in register 0h. Care must be taken to ensure that the KSZ8061 and the link partner will link with the same speed and duplex. Note that the KSZ8061 defaults to full-duplex when auto-negotiation is off, but other devices may default to half-duplex in the event of failed auto-negotiation. 3. The issue can be avoided by connecting the cable prior to powering-up or resetting the KSZ8061, and leaving it plugged in thereafter. 4. If the above measures are not taken and the problem occurs, link can be recovered by setting the Restart Auto-Negotiation bit in register 0h, or by resetting or power cycling the device. Reset may be either hardware reset or software reset (register 0h, bit 15). PLAN This errata will not be corrected in the future revision. Fixes: 7ab59dc15e2f ("drivers/net/phy/micrel_phy: Add support for new PHYs") Signed-off-by: Alexander Onnasch <[email protected]> Signed-off-by: Rajasingh Thavamani <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-25net: phy: aquantia: add hwmon supportHeiner Kallweit4-0/+273
This adds HWMON support for the temperature sensor and the related alarms on the 107/108/109 chips. This patch is based on work from Nikita and Andrew. I added: - support for changing alarm thresholds via sysfs - move HWMON code to a separate source file to improve maintainability - smaller changes like using IS_REACHABLE instead of ifdef (avoids problems if PHY driver is built in and HWMON is a module) v2: - remove struct aqr_priv - rename header file to aquantia.h v3: - add conditional compiling of aquantia_hwmon.c - improve converting sensor register values to/from long - add helper aqr_hwmon_test_bit Signed-off-by: Nikita Yushchenko <[email protected]> Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-25net: phy: aquantia: rename aquantia.c to aquantia_main.cHeiner Kallweit2-0/+1
Rename aquantia.c to aquantia_main.c to be prepared for adding new functionality to separate source code files. Signed-off-by: Heiner Kallweit <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-24net: phy: fix reading fixed phy statusHeiner Kallweit1-0/+3
With the switch to phy_resolve_aneg_linkmode() we don't read from the chip any longer what is advertised but use phydev->advertising directly. For a fixed phy however this bitmap is empty so far, what results in no common mode being found. This breaks DSA. Fix this by advertising everything that is supported. For a normal phy this done by phy_probe(). Fixes: 5502b218e001 ("net: phy: use phy_resolve_aneg_linkmode in genphy_read_status") Signed-off-by: Heiner Kallweit <[email protected]> Tested-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-24net: phy: improve auto-neg emulation in swphyHeiner Kallweit1-9/+1
Auto-neg emulation currently doesn't set bit BMCR_ANENABLE in BMCR, add this. Users will ignore speed and duplex settings in BMCR because we're emulating auto-neg, therefore we can remove related code. See also following discussion [0]. [0] https://marc.info/?t=155041784900002&r=1&w=2 Signed-off-by: Heiner Kallweit <[email protected]> Tested-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-24net: phy: marvell10g: add support for the 88x2110 PHYMaxime Chevallier1-0/+13
This patch adds support for the 88x2110 PHY, which is similar to the already supported 88x3310 PHY without the SFP interface. It supports 10/100/1000BASET along with 2.5GBASET, 5GBASET and 10GBASET, with the same interface modes that are used by the 3310. This PHY don't have the same issue as the 88x3310 regarding 2.5/5G abilities, and correctly follows the 802.3bz standard to list the supported abilities. Signed-off-by: Maxime Chevallier <[email protected]> Suggested-by: Antoine Tenart <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-24net: phy: marvell10g: Force reading of 2.5/5GMaxime Chevallier1-0/+35
As per 802.3bz, if bit 14 of (1.11) "PMA Extended Abilities" indicates whether or not we should read register (1.21) "2.52/5G PMA Extended Abilities", which contains information on the support of 2.5GBASET and 5GBASET. After testing on several variants of PHYS of this family, it appears that bit 14 in (1.11) isn't always set when it should be. PHYs 88X3310 (on MacchiatoBin) and 88E2010 do support 2.5G and 5GBASET, but don't have 1.11.14 set. Their register 1.21 is filled with the correct values, indicating 2.5G and 5G support. PHYs 88E2110 do have their 1.11.14 bit set, as it should. Signed-off-by: Maxime Chevallier <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-24net: phy: marvell10g: Use a #define for 88X3310 family idMaxime Chevallier1-2/+2
The PHY ID corresponding to the 88X3310 is also used for other PHYs in the same family, such as the 88E2010. Use a #define for the PHY id, that ignores the last nibble. Signed-off-by: Maxime Chevallier <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-24net: phy: marvell10g: Use 2500BASEX when using 2.5GBASETMaxime Chevallier1-7/+19
The Marvell Alaska family of PHYs supports 2.5GBaseT and 5GBaseT modes, as defined in the 802.3bz specification. Upon establishing a 2.5GBASET link, the PHY will reconfigure it's MII interface to 2500BASEX. At 5G, the PHY will reconfigure it's interface to 5GBASE-R, but this mode isn't supported by any MAC for now. This was tested with : - The 88X3310, which is on the MacchiatoBin - The 88E2010, an Alaska PHY that has no fiber interfaces, and is limited to 5G maximum speed. Signed-off-by: Maxime Chevallier <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-24net: phy: marvell10g: Use linkmode_set_bit helper instead of __set_bitMaxime Chevallier1-2/+2
Cosmetic patch making use of helpers dedicated to linkmodes handling. Signed-off-by: Maxime Chevallier <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2019-02-24net: phy: marvell10g: Use get_features to get the PHY abilitiesMaxime Chevallier1-3/+8
The Alaska family of 10G PHYs has more abilities than the ones listed in PHY_10GBIT_FULL_FEATURES, the exact list depending on the model. Make use of the newly introduced .get_features call to build this list, using genphy_c45_pma_read_abilities to build the list of supported linkmodes, and adding autoneg ability based on what's reported by the AN MMD. .config_init is still used to validate the interface_mode. Signed-off-by: Maxime Chevallier <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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