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2021-01-09net: dsa: bcm_sf2: support BCM4908's integrated switchRafał Miłecki4-3/+49
BCM4908 family SoCs come with integrated Starfighter 2 switch. Its registers layout it a mix of BCM7278 and BCM7445. It has 5 integrated PHYs and 8 ports. It also supports RGMII and SerDes. Signed-off-by: Rafał Miłecki <[email protected]> Acked-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2021-01-08Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski2-3/+5
Trivial conflict in CAN on file rename. Conflicts: drivers/net/can/m_can/tcan4x5x-core.c Signed-off-by: Jakub Kicinski <[email protected]>
2021-01-07net: dsa: lantiq_gswip: Exclude RMII from modes that report 1 GbEAleksander Jan Bajkowski1-3/+4
Exclude RMII from modes that report 1 GbE support. Reduced MII supports up to 100 MbE. Fixes: 14fceff4771e ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Signed-off-by: Aleksander Jan Bajkowski <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2021-01-07net: dsa: ocelot: request DSA to fix up lack of address learning on CPU portVladimir Oltean1-0/+1
Given the following setup: ip link add br0 type bridge ip link set eno0 master br0 ip link set swp0 master br0 ip link set swp1 master br0 ip link set swp2 master br0 ip link set swp3 master br0 Currently, packets received on a DSA slave interface (such as swp0) which should be routed by the software bridge towards a non-switch port (such as eno0) are also flooded towards the other switch ports (swp1, swp2, swp3) because the destination is unknown to the hardware switch. This patch addresses the issue by monitoring the addresses learnt by the software bridge on eno0, and adding/deleting them as static FDB entries on the CPU port accordingly. Signed-off-by: Vladimir Oltean <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2021-01-06net: dsa: fix led_classdev build errorsRandy Dunlap1-0/+1
Fix build errors when LEDS_CLASS=m and NET_DSA_HIRSCHMANN_HELLCREEK=y. This limits the latter to =m when LEDS_CLASS=m. microblaze-linux-ld: drivers/net/dsa/hirschmann/hellcreek_ptp.o: in function `hellcreek_ptp_setup': (.text+0xf80): undefined reference to `led_classdev_register_ext' microblaze-linux-ld: (.text+0xf94): undefined reference to `led_classdev_register_ext' microblaze-linux-ld: drivers/net/dsa/hirschmann/hellcreek_ptp.o: in function `hellcreek_ptp_free': (.text+0x1018): undefined reference to `led_classdev_unregister' microblaze-linux-ld: (.text+0x1024): undefined reference to `led_classdev_unregister' Signed-off-by: Randy Dunlap <[email protected]> Reported-by: kernel test robot <[email protected]> Link: lore.kernel.org/r/[email protected] Cc: Kurt Kanzenbach <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2021-01-05net: dsa: sja1105: Use kzalloc for allocating only one thingZheng Yongjun1-1/+1
Use kzalloc rather than kcalloc(1,...) The semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ @@ - kcalloc(1, + kzalloc( ...) // </smpl> Signed-off-by: Zheng Yongjun <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2021-01-04net: dsa: lantiq_gswip: Fix GSWIP_MII_CFG(p) register accessMartin Blumenstingl1-17/+6
There is one GSWIP_MII_CFG register for each switch-port except the CPU port. The register offset for the first port is 0x0, 0x02 for the second, 0x04 for the third and so on. Update the driver to not only restrict the GSWIP_MII_CFG registers to ports 0, 1 and 5. Handle ports 0..5 instead but skip the CPU port. This means we are not overwriting the configuration for the third port (port two since we start counting from zero) with the settings for the sixth port (with number five) anymore. The GSWIP_MII_PCDU(p) registers are not updated because there's really only three (one for each of the following ports: 0, 1, 5). Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Signed-off-by: Martin Blumenstingl <[email protected]> Acked-by: Hauke Mehrtens <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2021-01-04net: dsa: lantiq_gswip: Enable GSWIP_MII_CFG_EN also for internal PHYsMartin Blumenstingl1-3/+1
Enable GSWIP_MII_CFG_EN also for internal PHYs to make traffic flow. Without this the PHY link is detected properly and ethtool statistics for TX are increasing but there's no RX traffic coming in. Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Suggested-by: Hauke Mehrtens <[email protected]> Signed-off-by: Martin Blumenstingl <[email protected]> Acked-by: Hauke Mehrtens <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-16net: dsa: qca: ar9331: fix sleeping function called from invalid context bugOleksij Rempel1-9/+24
With lockdep enabled, we will get following warning: ar9331_switch ethernet.1:10 lan0 (uninitialized): PHY [!ahb!ethernet@1a000000!mdio!switch@10:00] driver [Qualcomm Atheros AR9331 built-in PHY] (irq=13) BUG: sleeping function called from invalid context at kernel/locking/mutex.c:935 in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: 18, name: kworker/0:1 INFO: lockdep is turned off. irq event stamp: 602 hardirqs last enabled at (601): [<8073fde0>] _raw_spin_unlock_irq+0x3c/0x80 hardirqs last disabled at (602): [<8073a4f4>] __schedule+0x184/0x800 softirqs last enabled at (0): [<80080f60>] copy_process+0x578/0x14c8 softirqs last disabled at (0): [<00000000>] 0x0 CPU: 0 PID: 18 Comm: kworker/0:1 Not tainted 5.10.0-rc3-ar9331-00734-g7d644991df0c #31 Workqueue: events deferred_probe_work_func Stack : 80980000 80980000 8089ef70 80890000 804b5414 80980000 00000002 80b53728 00000000 800d1268 804b5414 ffffffde 00000017 800afe08 81943860 0f5bfc32 00000000 00000000 8089ef70 819436c0 ffffffea 00000000 00000000 00000000 8194390c 808e353c 0000000f 66657272 80980000 00000000 00000000 80890000 804b5414 80980000 00000002 80b53728 00000000 00000000 00000000 80d40000 ... Call Trace: [<80069ce0>] show_stack+0x9c/0x140 [<800afe08>] ___might_sleep+0x220/0x244 [<8073bfb0>] __mutex_lock+0x70/0x374 [<8073c2e0>] mutex_lock_nested+0x2c/0x38 [<804b5414>] regmap_update_bits_base+0x38/0x8c [<804ee584>] regmap_update_bits+0x1c/0x28 [<804ee714>] ar9331_sw_unmask_irq+0x34/0x60 [<800d91f0>] unmask_irq+0x48/0x70 [<800d93d4>] irq_startup+0x114/0x11c [<800d65b4>] __setup_irq+0x4f4/0x6d0 [<800d68a0>] request_threaded_irq+0x110/0x190 [<804e3ef0>] phy_request_interrupt+0x4c/0xe4 [<804df508>] phylink_bringup_phy+0x2c0/0x37c [<804df7bc>] phylink_of_phy_connect+0x118/0x130 [<806c1a64>] dsa_slave_create+0x3d0/0x578 [<806bc4ec>] dsa_register_switch+0x934/0xa20 [<804eef98>] ar9331_sw_probe+0x34c/0x364 [<804eb48c>] mdio_probe+0x44/0x70 [<8049e3b4>] really_probe+0x30c/0x4f4 [<8049ea10>] driver_probe_device+0x264/0x26c [<8049bc10>] bus_for_each_drv+0xb4/0xd8 [<8049e684>] __device_attach+0xe8/0x18c [<8049ce58>] bus_probe_device+0x48/0xc4 [<8049db70>] deferred_probe_work_func+0xdc/0xf8 [<8009ff64>] process_one_work+0x2e4/0x4a0 [<800a0770>] worker_thread+0x2a8/0x354 [<800a774c>] kthread+0x16c/0x174 [<8006306c>] ret_from_kernel_thread+0x14/0x1c ar9331_switch ethernet.1:10 lan1 (uninitialized): PHY [!ahb!ethernet@1a000000!mdio!switch@10:02] driver [Qualcomm Atheros AR9331 built-in PHY] (irq=13) DSA: tree 0 setup To fix it, it is better to move access to MDIO register to the .irq_bus_sync_unlock call back. Fixes: ec6698c272de ("net: dsa: add support for Atheros AR9331 built-in switch") Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-14net: dsa: mv88e6xxx: don't set non-existing learn2all bit for 6220/6250Rasmus Villemoes1-3/+10
The 6220 and 6250 switches do not have a learn2all bit in global1, ATU control register; bit 3 is reserverd. On the switches that do have that bit, it is used to control whether learning frames are sent out the ports that have the message_port bit set. So rather than adding yet another chip method, use the existence of the ->port_setup_message_port method as a proxy for determining whether the learn2all bit exists (and should be set). Signed-off-by: Rasmus Villemoes <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-12net: dsa: mt7530: enable MTU normalizationDENG Qingfang1-0/+2
MT7530 has a global RX length register, so we are actually changing its MRU. Enable MTU normalization for this reason. Signed-off-by: DENG Qingfang <[email protected]> Acked-by: Landen Chao <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-11Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski3-7/+2
xdp_return_frame_bulk() needs to pass a xdp_buff to __xdp_return(). strlcpy got converted to strscpy but here it makes no functional difference, so just keep the right code. Conflicts: net/netfilter/nf_tables_api.c Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-09net: dsa: simplify the return rtl8366_vlan_prepare()Zheng Yongjun1-6/+1
Simplify the return expression. Signed-off-by: Zheng Yongjun <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-12-09net: mv88e6xxx: convert comma to semicolonZheng Yongjun1-1/+1
Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-12-08net: dsa: mt7530: support setting ageing timeDENG Qingfang2-0/+54
MT7530 has a global address age control register, so use it to set ageing time. The applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds Signed-off-by: DENG Qingfang <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2020-12-05net: mscc: ocelot: fix dropping of unknown IPv4 multicast on SevilleVladimir Oltean3-7/+2
The current assumption is that the felix DSA driver has flooding knobs per traffic class, while ocelot switchdev has a single flooding knob. This was correct for felix VSC9959 and ocelot VSC7514, but with the introduction of seville VSC9953, we see a switch driven by felix.c which has a single flooding knob. So it is clear that we must do what should have been done from the beginning, which is not to overwrite the configuration done by ocelot.c in felix, but instead to teach the common ocelot library about the differences in our switches, and set up the flooding PGIDs centrally. The effect that the bogus iteration through FELIX_NUM_TC has upon seville is quite dramatic. ANA_FLOODING is located at 0x00b548, and ANA_FLOODING_IPMC is located at 0x00b54c. So the bogus iteration will actually overwrite ANA_FLOODING_IPMC when attempting to write ANA_FLOODING[1]. There is no ANA_FLOODING[1] in sevile, just ANA_FLOODING. And when ANA_FLOODING_IPMC is overwritten with a bogus value, the effect is that ANA_FLOODING_IPMC gets the value of 0x0003CF7D: MC6_DATA = 61, MC6_CTRL = 61, MC4_DATA = 60, MC4_CTRL = 0. Because MC4_CTRL is zero, this means that IPv4 multicast control packets are not flooded, but dropped. An invalid configuration, and this is how the issue was actually spotted. Reported-by: Eldar Gasanov <[email protected]> Reported-by: Maxim Kochetkov <[email protected]> Tested-by: Eldar Gasanov <[email protected]> Fixes: 84705fc16552 ("net: dsa: felix: introduce support for Seville VSC9953 switch") Fixes: 3c7b51bd39b2 ("net: dsa: felix: allow flooding for all traffic classes") Signed-off-by: Vladimir Oltean <[email protected]> Reviewed-by: Alexandre Belloni <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: ksz8795: use num_vlans where possibleMichael Grzeschik2-2/+1
The value of the define VLAN_TABLE_ENTRIES can be derived from num_vlans. This patch is using the variable num_vlans instead and removes the extra define. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: ksz8795: use port_cnt instead of TOTOAL_PORT_NUMMichael Grzeschik2-4/+2
To get the driver working with other chips using different port counts the dyn_mac_table should be flushed depending on the amount of available ports. This patch remove the extra define TOTOAL_PORT_NUM and is making use of the dynamic port_cnt variable instead. Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: remove usage of mib_port_countMichael Grzeschik4-16/+12
The variable mib_port_cnt has the same meaning as port_cnt. This driver removes the extra variable and is using port_cnt everywhere instead. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: ksz8795: align port_cnt usage with other microchip driversMichael Grzeschik1-5/+5
The ksz8795 driver is using port_cnt differently to the other microchip DSA drivers. It sets it to the external physical port count, than the whole port count (including the cpu port). This patch is aligning the variables purpose with the other microchip drivers. Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: remove superfluous num_ports assignmentMichael Grzeschik2-4/+0
The variable num_ports is already assigned in the init function. The drivers individual init function already handles the different purpose of port_cnt vs port_cnt + 1. This patch removes the extra assignment of the variable. Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: ksz8795: use phy_port_cnt where possibleMichael Grzeschik2-13/+10
The driver is currently hard coded to SWITCH_PORT_NUM being (TOTAL_PORT_NUM - 1) which is limited to 4 user ports for the ksz8795. The phy_port_cnt is referring to its user ports. The patch removes the extra define and use the assigned variable phy_port_cnt instead so the driver can be used on different switches. Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: ksz8795: use mib_cnt where possibleMichael Grzeschik2-7/+5
The variable mib_cnt is assigned with TOTAL_SWITCH_COUNTER_NUM. This value can also be derived from the array size of mib_names. This patch uses this calculated value instead, removes the extra define and uses mib_cnt everywhere possible instead of the static define TOTAL_SWITCH_COUNTER_NUM. Keeping it in a separate variable instead of using ARRAY_SIZE everywhere instead makes the driver more flexible for future use of devices with different amount of counters. Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: ksz8795: use reg_mib_cnt where possibleMichael Grzeschik2-4/+3
The extra define SWITCH_COUNTER_NUM is a copy of the KSZ8795_COUNTER_NUM define. This patch initializes reg_mib_cnt with KSZ8795_COUNTER_NUM, makes use of reg_mib_cnt everywhere instead and removes the extra define. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: ksz8795: move variable assignments from detect to initMichael Grzeschik1-6/+6
This patch moves all variable assignments to the init function. It leaves the detect function for its single purpose to detect which chip version is found. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: ksz8795: remove superfluous port_cnt assignmentMichael Grzeschik1-2/+0
The port_cnt assignment will be done again in the init function. This patch removes the previous assignment in the detect function. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-12-02net: dsa: microchip: ksz8795: remove unused last_port variableMichael Grzeschik2-2/+0
The variable last_port is not used anywhere, this patch removes it. Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-25net: dsa: mv88e6xxx: Handle error in serdes_get_regsChris Packham1-5/+9
If the underlying read operation failed we would end up writing stale data to the supplied buffer. This would end up with the last successfully read value repeating. Fix this by only writing the data when we know the read was good. This will mean that failed values will return 0xffff. Signed-off-by: Chris Packham <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-25net: dsa: mv88e6xxx: Add serdes interrupt support for MV88E6097Chris Packham3-0/+54
The MV88E6097 presents the serdes interrupts for ports 8 and 9 via the Switch Global 2 registers. There is no additional layer of enablinh/disabling the serdes interrupts like other mv88e6xxx switches. Even though most of the serdes behaviour is the same as the MV88E6185 that chip does not provide interrupts for serdes events so unlike earlier commits the functions added here are specific to the MV88E6097. Signed-off-by: Chris Packham <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-25net: dsa: mv88e6xxx: Support serdes ports on MV88E6097/6095/6185Chris Packham3-0/+76
Implement serdes_power, serdes_get_lane and serdes_pcs_get_state ops for the MV88E6097/6095/6185 so that ports 8 & 9 can be supported as serdes ports and directly connected to other network interfaces or to SFPs without a PHY. Signed-off-by: Chris Packham <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-25net: dsa: mv88e6xxx: Don't force link when using in-band-statusChris Packham4-4/+74
When a port is configured with 'managed = "in-band-status"' switch chips like the 88E6390 need to propagate the SERDES link state to the MAC because the link state is not correctly detected. This causes problems on the 88E6185/88E6097 where the link partner won't see link state changes because we're forcing the link. To address this introduce a new device specific op port_sync_link() and push the logic from mv88e6xxx_mac_link_up() into that. Provide an implementation for the 88E6185 like devices which doesn't force the link. Signed-off-by: Chris Packham <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-25net: dsa: microchip: ksz8795: setup SPI modeChristian Eggers1-0/+6
This should be done in the device driver instead of the device tree. Signed-off-by: Christian Eggers <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-25net: dsa: microchip: ksz9477: setup SPI modeChristian Eggers1-0/+6
This should be done in the device driver instead of the device tree. Signed-off-by: Christian Eggers <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-25net: dsa: microchip: support for "ethernet-ports" nodeChristian Eggers1-1/+3
The dsa.yaml device tree binding allows "ethernet-ports" (preferred) and "ports". Signed-off-by: Christian Eggers <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-23net: dsa: hellcreek: Don't print error message on deferKurt Kanzenbach1-1/+1
When DSA is not loaded when the driver is probed an error message is printed. But, that's not really an error, just a defer. Use dev_err_probe() instead. Signed-off-by: Kurt Kanzenbach <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-19Merge https://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski5-10/+94
Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-18net: dsa: mv88e6xxx: Wait for EEPROM done after HW resetAndrew Lunn3-0/+34
When the switch is hardware reset, it reads the contents of the EEPROM. This can contain instructions for programming values into registers and to perform waits between such programming. Reading the EEPROM can take longer than the 100ms mv88e6xxx_hardware_reset() waits after deasserting the reset GPIO. So poll the EEPROM done bit to ensure it is complete. Signed-off-by: Andrew Lunn <[email protected]> Signed-off-by: Ruslan Sushko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-16net: lantiq: Wait for the GPHY firmware to be readyMartin Blumenstingl1-0/+11
A user reports (slightly shortened from the original message): libphy: lantiq,xrx200-mdio: probed mdio_bus 1e108000.switch-mii: MDIO device at address 17 is missing. gswip 1e108000.switch lan: no phy at 2 gswip 1e108000.switch lan: failed to connect to port 2: -19 lantiq,xrx200-net 1e10b308.eth eth0: error -19 setting up slave phy This is a single-port board using the internal Fast Ethernet PHY. The user reports that switching to PHY scanning instead of configuring the PHY within device-tree works around this issue. The documentation for the standalone variant of the PHY11G (which is probably very similar to what is used inside the xRX200 SoCs but having the firmware burnt onto that standalone chip in the factory) states that the PHY needs 300ms to be ready for MDIO communication after releasing the reset. Add a 300ms delay after initializing all GPHYs to ensure that the GPHY firmware had enough time to initialize and to appear on the MDIO bus. Unfortunately there is no (known) documentation on what the minimum time to wait after releasing the reset on an internal PHY so play safe and take the one for the external variant. Only wait after the last GPHY firmware is loaded to not slow down the initialization too much ( xRX200 has two GPHYs but newer SoCs have at least three GPHYs). Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Martin Blumenstingl <[email protected]> Acked-by: Hauke Mehrtens <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-14net: dsa: mv88e6xxx: Avoid VTU corruption on 6097Tobias Waldekranz1-10/+49
As soon as you add the second port to a VLAN, all other port membership configuration is overwritten with zeroes. The HW interprets this as all ports being "unmodified members" of the VLAN. In the simple case when all ports belong to the same VLAN, switching will still work. But using multiple VLANs or trying to set multiple ports as tagged members will not work. On the 6352, doing a VTU GetNext op, followed by an STU GetNext op will leave you with both the member- and state- data in the VTU/STU data registers. But on the 6097 (which uses the same implementation), the STU GetNext will override the information gathered from the VTU GetNext. Separate the two stages, parsing the result of the VTU GetNext before doing the STU GetNext. We opt to update the existing implementation for all applicable chips, as opposed to creating a separate callback for 6097, because although the previous implementation did work for (at least) 6352, the datasheet does not mention the masking behavior. Fixes: ef6fcea37f01 ("net: dsa: mv88e6xxx: get STU entry on VTU GetNext") Signed-off-by: Tobias Waldekranz <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-12Merge https://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-1/+3
Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-11net: dsa: mv88e6xxx: Add helper to get a chip's max_vidTobias Waldekranz3-13/+18
Most of the other chip info constants have helpers to get at them; add one for max_vid to keep things consistent. Suggested-by: Andrew Lunn <[email protected]> Signed-off-by: Tobias Waldekranz <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-10net: dsa: mv88e6xxx: Fix memleak in mv88e6xxx_region_atu_snapshotzhangxiaoxu1-1/+3
When mv88e6xxx_fid_map return error, we lost free the table. Fix it. Fixes: bfb255428966 ("net: dsa: mv88e6xxx: Add devlink regions") Reported-by: Hulk Robot <[email protected]> Signed-off-by: zhangxiaoxu <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-10net: dsa: fix unintended sign extension on a u16 left shiftColin Ian King1-2/+2
The left shift of u16 variable high is promoted to the type int and then sign extended to a 64 bit u64 value. If the top bit of high is set then the upper 32 bits of the result end up being set by the sign extension. Fix this by explicitly casting the value in high to a u64 before left shifting by 16 places. Also, remove the initialisation of variable value to 0 at the start of each loop iteration as the value is never read and hence the assignment it is redundant. Addresses-Coverity: ("Unintended sign extension") Fixes: e4b27ebc780f ("net: dsa: Add DSA driver for Hirschmann Hellcreek switches") Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Kurt Kanzenbach <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-09net: dsa: mv88e6xxx: Export VTU as devlink regionTobias Waldekranz4-3/+109
Export the raw VTU data and related registers in a devlink region so that it can be inspected from userspace and compared to the current bridge configuration. Signed-off-by: Tobias Waldekranz <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-06Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-2/+2
Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-05net: dsa: hellcreek: Add PTP status LEDsKurt Kanzenbach3-0/+156
The switch has two controllable I/Os which are usually connected to LEDs. This is useful to immediately visually see the PTP status. These provide two signals: * is_gm This LED can be activated if the current device is the grand master in that PTP domain. * sync_good This LED can be activated if the current device is in sync with the network time. Expose these via the LED framework to be controlled via user space e.g. linuxptp. Signed-off-by: Kurt Kanzenbach <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-05net: dsa: hellcreek: Add support for hardware timestampingKamil Alkhouri7-14/+616
The switch has the ability to take hardware generated time stamps per port for PTPv2 event messages in Rx and Tx direction. That is useful for achieving needed time synchronization precision for TSN devices/switches. So add support for it. There are two directions: * RX The switch has a single register per port to capture a timestamp. That mechanism is not used due to correlation problems. If the software processing is too slow and a PTPv2 event message is received before the previous one has been processed, false timestamps will be captured. Therefore, the switch can do "inline" timestamping which means it can insert the nanoseconds part of the timestamp directly into the PTPv2 event message. The reserved field (4 bytes) is leveraged for that. This might not be in accordance with (older) PTP standards, but is the only way to get reliable results. * TX In Tx direction there is no correlation problem, because the software and the driver has to ensure that only one event message is "on the fly". However, the switch provides also a mechanism to check whether a timestamp is lost. That can only happen when a timestamp is read and at this point another message is timestamped. So, that lost bit is checked just in case to indicate to the user that the driver or the software is somewhat buggy. Signed-off-by: Kamil Alkhouri <[email protected]> Signed-off-by: Kurt Kanzenbach <[email protected]> Acked-by: Richard Cochran <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-05net: dsa: hellcreek: Add PTP clock supportKamil Alkhouri6-1/+435
The switch has internal PTP hardware clocks. Add support for it. There are three clocks: * Synchronized * Syntonized * Free running Currently the synchronized clock is exported to user space which is a good default for the beginning. The free running clock might be exported later e.g. for implementing 802.1AS-2011/2020 Time Aware Bridges (TAB). The switch also supports cross time stamping for that purpose. The implementation adds support setting/getting the time as well as offset and frequency adjustments. However, the clock only holds a partial timeofday timestamp. This is why we track the seconds completely in software (see overflow work and last_ts). Furthermore, add the PTP multicast addresses into the FDB to forward that packages only to the CPU port where they are processed by a PTP program. Signed-off-by: Kamil Alkhouri <[email protected]> Signed-off-by: Kurt Kanzenbach <[email protected]> Acked-by: Richard Cochran <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-05net: dsa: Add DSA driver for Hirschmann Hellcreek switchesKurt Kanzenbach6-0/+1515
Add a basic DSA driver for Hirschmann Hellcreek switches. Those switches are implementing features needed for Time Sensitive Networking (TSN) such as support for the Time Precision Protocol and various shapers like the Time Aware Shaper. This driver includes basic support for networking: * VLAN handling * FDB handling * Port statistics * STP * Phylink Signed-off-by: Kurt Kanzenbach <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2020-11-04net: dsa: mt7530: support setting MTUDENG Qingfang2-0/+61
MT7530/7531 has a global RX packet length register, which can be used to set MTU. Supported packet length values are 1522 (1518 if untagged), 1536, 1552, and multiple of 1024 (from 2048 to 15360). Signed-off-by: DENG Qingfang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
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