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path: root/drivers/net/dsa/rzn1_a5psw.c
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2022-06-30net: dsa: rzn1-a5psw: add missing of_node_put() in a5psw_pcs_get()Yang Yingliang1-0/+2
of_parse_phandle() will increase the refcount of 'pcs_node', so add of_node_put() before return from a5psw_pcs_get(). Fixes: 888cdb892b61 ("net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driver") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Link: https://lore.kernel.org/r/20220630014153.1888811-1-yangyingliang@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-29net: dsa: rzn1-a5psw: fix a NULL vs IS_ERR() check in a5psw_probe()Peng Wu1-2/+2
The devm_platform_ioremap_resource() function never returns NULL. It returns error pointers. Signed-off-by: Peng Wu <wupeng58@huawei.com> Reported-by: Hulk Robot <hulkci@huawei.com> Reviewed-by: Clément Léger <clement.leger@bootlin.com> Link: https://lore.kernel.org/r/20220628130920.49493-1-wupeng58@huawei.com Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2022-06-27net: dsa: rzn1-a5psw: add FDB supportClément Léger1-0/+168
This commits add forwarding database support to the driver. It implements fdb_add(), fdb_del() and fdb_dump(). Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-27net: dsa: rzn1-a5psw: add statistics supportClément Léger1-0/+174
Add statistics support to the rzn1-a5psw driver by implementing the following dsa_switch_ops callbacks: - get_sset_count() - get_strings() - get_ethtool_stats() - get_eth_mac_stats() - get_eth_ctrl_stats() - get_rmon_stats() Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
2022-06-27net: dsa: rzn1-a5psw: add Renesas RZ/N1 advanced 5 port switch driverClément Léger1-0/+720
Add Renesas RZ/N1 advanced 5 port switch driver. This switch handles 5 ports including 1 CPU management port. A MDIO bus is also exposed by this switch and allows to communicate with PHYs connected to the ports. Each switch port (except for the CPU management ports) is connected to the MII converter. This driver includes basic bridging support, more support will be added later (vlan, etc). Suggested-by: Jean-Pierre Geslin <jean-pierre.geslin@non.se.com> Suggested-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> Reviewed-by: Vladimir Oltean <olteanv@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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