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2022-08-31net: dsa: microchip: add regmap_range for KSZ9477 chipOleksij Rempel1-0/+272
Add register validation for KSZ9477 Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: ksz9477: remove MII_CTRL1000 check from ksz9477_w_phy()Oleksij Rempel1-4/+0
The reason why PHYlib may access MII_CTRL1000 on the chip without GBit support is only if chip provides wrong information about extended caps register. This issue is now handled by ksz9477_r_phy_quirks() With proper regmap_ranges provided for all chips we will be able to catch this kind of bugs any way. So, remove this sanity check. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: add regmap_range for KSZ8563 chipOleksij Rempel1-0/+121
Add register validation for KSZ8563. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: add support for regmap_access_tablesOleksij Rempel2-4/+45
This is complex driver with support for different chips with different layouts. To detect at least some bugs earlier, we should validate register accesses by using regmap_access_table support. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: KSZ9893: do not write to not supported Output Clock ↵Oleksij Rempel1-0/+5
Control Register This issue was detected after adding regmap register access validation. KSZ9893 compatible chips do not have "Output Clock Control Register 0x0103". So, avoid writing to it. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: ksz8795: add error handling to ksz8_r/w_phyOleksij Rempel1-21/+81
Now ksz_pread/ksz_pwrite can return error value. So, make use of it. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: ksz9477: add error handling to ksz9477_r/w_phyOleksij Rempel1-5/+7
Now ksz_pread/ksz_pwrite can return error value. So, make use of it. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: forward error value on all ksz_pread/ksz_pwrite functionsOleksij Rempel1-18/+20
ksz_read*/ksz_write* are able to return errors, so forward it. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: allow to pass return values for PHY read/write accessesOleksij Rempel8-20/+34
PHY access may end with errors on different levels. So, allow to forward return values where possible. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: don't announce extended register support on non Gbit chipsOleksij Rempel1-0/+11
This issue was detected after adding support of regmap_ranges for KSZ8563R chip. This chip is reporting extended registers support without having actual extended registers. This made PHYlib request not existing registers. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: do per-port Gbit detection instead of per-chipOleksij Rempel3-18/+9
KSZ8563 has two 100Mbit PHYs and CPU port with RGMII support. Since 1000Mbit configuration for the RGMII capable MAC is present, we should use per port validation. As main part of migration to per-port validation we need to rework ksz9477_switch_init() function. Which is using undocumented REG_GLOBAL_OPTIONS register to detect per-chip Gbit support. So, it is related to some sort of risk for regressions. To reduce this risk I compared the code with publicly available documentations. This function will executed on following currently supported chips: struct ksz_chip_data OF compatible KSZ9477 KSZ9477 KSZ9897 KSZ9897 KSZ9893 KSZ9893, KSZ9563 KSZ8563 KSZ8563 KSZ9567 KSZ9567 Only KSZ9893, KSZ9563, KSZ8563 document existence of 0xf == REG_GLOBAL_OPTIONS register with bit field description "SKU ID": KSZ9893 0x0C KSZ9563 0x1C KSZ8563 0x3C The existence of hidden flags is not documented. KSZ9477, KSZ9897, KSZ9567 do not document this register at all. Only KSZ8563 is documented as non Gbit chip: 100Mbit PHYs and RGMII CPU port. So, this change should not introduce a regression for configurations with properly used OF compatibles. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-31net: dsa: microchip: add separate struct ksz_chip_data for KSZ8563 chipOleksij Rempel3-3/+44
Add separate entry for the KSZ8563 chip. According to the documentation it can support Gbit only on RGMII port. So, we will need to be able to describe in the followup patch. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-08-23net: dsa: microchip: make learning configurable and keep it off while standaloneVladimir Oltean2-1/+45
Address learning should initially be turned off by the driver for port operation in standalone mode, then the DSA core handles changes to it via ds->ops->port_bridge_flags(). Leaving address learning enabled while ports are standalone breaks any kind of communication which involves port B receiving what port A has sent. Notably it breaks the ksz9477 driver used with a (non offloaded, ports act as if standalone) bonding interface in active-backup mode, when the ports are connected together through external switches, for redundancy purposes. This fixes a major design flaw in the ksz9477 and ksz8795 drivers, which unconditionally leave address learning enabled even while ports operate as standalone. Fixes: b987e98e50ab ("dsa: add DSA switch driver for Microchip KSZ9477") Link: https://lore.kernel.org/netdev/CAFZh4h-JVWt80CrQWkFji7tZJahMfOToUJQgKS5s0_=9zzpvYQ@mail.gmail.com/ Reported-by: Brian Hutchinson <[email protected]> Signed-off-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2022-08-22net: dsa: microchip: keep compatibility with device tree blobs with no phy-modeVladimir Oltean1-1/+7
DSA has multiple ways of specifying a MAC connection to an internal PHY. One requires a DT description like this: port@0 { reg = <0>; phy-handle = <&internal_phy>; phy-mode = "internal"; }; (which is IMO the recommended approach, as it is the clearest description) but it is also possible to leave the specification as just: port@0 { reg = <0>; } and if the driver implements ds->ops->phy_read and ds->ops->phy_write, the DSA framework "knows" it should create a ds->slave_mii_bus, and it should connect to a non-OF-based internal PHY on this MDIO bus, at an MDIO address equal to the port address. There is also an intermediary way of describing things: port@0 { reg = <0>; phy-handle = <&internal_phy>; }; In case 2, DSA calls phylink_connect_phy() and in case 3, it calls phylink_of_phy_connect(). In both cases, phylink_create() has been called with a phy_interface_t of PHY_INTERFACE_MODE_NA, and in both cases, PHY_INTERFACE_MODE_NA is translated into phy->interface. It is important to note that phy_device_create() initializes dev->interface = PHY_INTERFACE_MODE_GMII, and so, when we use phylink_create(PHY_INTERFACE_MODE_NA), no one will override this, and we will end up with a PHY_INTERFACE_MODE_GMII interface inherited from the PHY. All this means that in order to maintain compatibility with device tree blobs where the phy-mode property is missing, we need to allow the "gmii" phy-mode and treat it as "internal". Fixes: 2c709e0bdad4 ("net: dsa: microchip: ksz8795: add phylink support") Link: https://bugzilla.kernel.org/show_bug.cgi?id=216320 Reported-by: Craig McQueen <[email protected]> Signed-off-by: Vladimir Oltean <[email protected]> Reviewed-by: Alvin Šipraga <[email protected]> Tested-by: Rasmus Villemoes <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2022-08-17net: dsa: microchip: ksz9477: fix fdb_dump last invalid entryArun Ramadoss1-0/+3
In the ksz9477_fdb_dump function it reads the ALU control register and exit from the timeout loop if there is valid entry or search is complete. After exiting the loop, it reads the alu entry and report to the user space irrespective of entry is valid. It works till the valid entry. If the loop exited when search is complete, it reads the alu table. The table returns all ones and it is reported to user space. So bridge fdb show gives ff:ff:ff:ff:ff:ff as last entry for every port. To fix it, after exiting the loop the entry is reported only if it is valid one. Fixes: b987e98e50ab ("dsa: add DSA switch driver for Microchip KSZ9477") Signed-off-by: Arun Ramadoss <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2022-08-16i2c: Make remove callback return voidUwe Kleine-König1-3/+1
The value returned by an i2c driver's remove function is mostly ignored. (Only an error message is printed if the value is non-zero that the error is ignored.) So change the prototype of the remove function to return no value. This way driver authors are not tempted to assume that passing an error to the upper layer is a good idea. All drivers are adapted accordingly. There is no intended change of behaviour, all callbacks were prepared to return 0 before. Reviewed-by: Peter Senna Tschudin <[email protected]> Reviewed-by: Jeremy Kerr <[email protected]> Reviewed-by: Benjamin Mugnier <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Reviewed-by: Crt Mori <[email protected]> Reviewed-by: Heikki Krogerus <[email protected]> Acked-by: Greg Kroah-Hartman <[email protected]> Acked-by: Marek Behún <[email protected]> # for leds-turris-omnia Acked-by: Andy Shevchenko <[email protected]> Reviewed-by: Petr Machata <[email protected]> # for mlxsw Reviewed-by: Maximilian Luz <[email protected]> # for surface3_power Acked-by: Srinivas Pandruvada <[email protected]> # for bmc150-accel-i2c + kxcjk-1013 Reviewed-by: Hans Verkuil <[email protected]> # for media/* + staging/media/* Acked-by: Miguel Ojeda <[email protected]> # for auxdisplay/ht16k33 + auxdisplay/lcd2s Reviewed-by: Luca Ceresoli <[email protected]> # for versaclock5 Reviewed-by: Ajay Gupta <[email protected]> # for ucsi_ccg Acked-by: Jonathan Cameron <[email protected]> # for iio Acked-by: Peter Rosin <[email protected]> # for i2c-mux-*, max9860 Acked-by: Adrien Grassein <[email protected]> # for lontium-lt8912b Reviewed-by: Jean Delvare <[email protected]> # for hwmon, i2c-core and i2c/muxes Acked-by: Corey Minyard <[email protected]> # for IPMI Reviewed-by: Vladimir Oltean <[email protected]> Acked-by: Dmitry Torokhov <[email protected]> Acked-by: Sebastian Reichel <[email protected]> # for drivers/power Acked-by: Krzysztof Hałasa <[email protected]> Signed-off-by: Uwe Kleine-König <[email protected]> Signed-off-by: Wolfram Sang <[email protected]>
2022-07-27net: dsa: microchip: add support for phylink mac configArun Ramadoss6-33/+21
This patch add support for phylink mac config for ksz series of switches. All the files ksz8795, ksz9477 and lan937x uses the ksz common xmii function. Instead of calling from the individual files, it is moved to the ksz common phylink mac config function. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-27net: dsa: microchip: ksz8795: use common xmii functionArun Ramadoss2-42/+1
This patch updates the ksz8795 cpu configuration to use the ksz common xmii set functions. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-27net: dsa: microchip: ksz9477: use common xmii functionArun Ramadoss4-167/+49
In ksz9477.c file, configuring the xmii register is performed based on the flag NEW_XMII. The flag is reset for ksz9893 switch and set for other switch. This patch uses the ksz common xmii set and get function. The bit values are configured based on the chip id. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-27net: dsa: microchip: apply rgmii tx and rx delay in phylink mac configArun Ramadoss5-1/+130
This patch read the rgmii tx and rx delay from device tree and stored it in the ksz_port. It applies the rgmii delay to the xmii tune adjust register based on the interface selected in phylink mac config. There are two rgmii port in LAN937x and value to be loaded in the register vary depends on the port selected. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-27net: dsa: microchip: lan937x: add support for configuing xMII registerArun Ramadoss4-40/+53
This patch add the common ksz_set_xmii function for ksz series switch and update the lan937x code phylink mac config. The register address for the ksz8795 is Port 5 Interface control 6 and for all other switch is xMII Control 1. The bit value for selecting the interface is same for KSZ8795 and KSZ9893 are same. The bit values for KSZ9477 and lan973x are same. So, this patch add the bit value for each switches in ksz_chip_data and configure the registers based on the chip id. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-27net: dsa: microchip: add support for common phylink mac link upArun Ramadoss4-33/+16
This patch add the support for common phylink mac link up for the ksz series switch. The register address, bit position and values are configured based on the chip id to the dev->info structure. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-27net: dsa: microchip: add common duplex and flow control functionArun Ramadoss5-23/+57
This patch add common function for configuring the Full/Half duplex and transmit/receive flow control. KSZ8795 uses the Global control register 4 for configuring the duplex and flow control, whereas all other KSZ9477 based switch uses the xMII Control 0 register. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-27net: dsa: microchip: add common ksz port xmii speed selection functionArun Ramadoss5-15/+69
This patch adds the function for configuring the 100/10Mbps speed selection for the ksz switches. KSZ8795 switch uses Global control 4 register 0x06 bit 4 for choosing 100/10Mpbs. Other switches uses xMII control 1 0xN300 for it. For KSZ8795, if the bit is set then 10Mbps is chosen and if bit is clear then 100Mbps chosen. For all other switches it is other way around, if the bit is set then 100Mbps is chosen. So, this patch add the generic function for ksz switch to select the 100/10Mbps speed selection. While configuring, first it disables the gigabit functionality and then configure the respective speed. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-27net: dsa: microchip: add common gigabit set and get functionArun Ramadoss6-48/+82
This patch add helper function for setting and getting the gigabit enable for the ksz series switch. KSZ8795 switch has different register address compared to all other ksz switches. KSZ8795 series uses the Port 5 Interface control 6 Bit 6 for configuring the 1Gbps or 100/10Mbps speed selection. All other switches uses the xMII control 1 0xN301 register Bit6 for gigabit. Further, for KSZ8795 & KSZ9893 switches if bit 1 then 1Gbps is chosen and if bit 0 then 100/10Mbps is chosen. It is other way around for other switches bit 0 is for 1Gbps. So, this patch implements the common function for configuring the gigabit set and get capability. Signed-off-by: Arun Ramadoss <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-21Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/netJakub Kicinski1-1/+4
No conflicts. Signed-off-by: Jakub Kicinski <[email protected]>
2022-07-19net: dsa: microchip: fix the missing ksz8_r_mib_cntArun Ramadoss1-0/+1
During the refactoring for the ksz8_dev_ops from ksz8795.c to ksz_common.c, the ksz8_r_mib_cnt has been missed. So this patch adds the missing one. Fixes: 6ec23aaaac43 ("net: dsa: microchip: move ksz_dev_ops to ksz_common.c") Signed-off-by: Arun Ramadoss <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Paolo Abeni <[email protected]>
2022-07-18net: dsa: microchip: fix Clang -Wunused-const-variable warning on 'ksz_dt_ids'Arun Ramadoss1-1/+1
This patch removes the of_match_ptr() pointer when dereferencing the ksz_dt_ids which produce the unused variable warning. Reported-by: kernel test robot <[email protected]> Suggested-by: Arnd Bergmann <[email protected]> Signed-off-by: Arun Ramadoss <[email protected]> Reviewed-by: Arnd Bergmann <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-15net: dsa: microchip: ksz_common: Fix refcount leak bugLiang He1-1/+4
In ksz_switch_register(), we should call of_node_put() for the reference returned by of_get_child_by_name() which has increased the refcount. Fixes: 912aae27c6af ("net: dsa: microchip: really look for phy-mode in port nodes") Signed-off-by: Liang He <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2022-07-02net: dsa: microchip: add LAN937x in the ksz spi probeArun Ramadoss1-0/+26
This patch add the LAN937x part support in the existing ksz_spi_probe. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-02net: dsa: microchip: lan937x: add phylink_mac_config supportArun Ramadoss4-2/+74
This patch add support for phylink_mac_config dsa hook. It configures the mac for MII/RMII modes. The RGMII mode will be added in the future patches. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-02net: dsa: microchip: lan937x: add phylink_mac_link_up supportArun Ramadoss5-0/+82
This patch add support for phylink_mac_link_up. It configures the mac for the speed, flow control and duplex mode. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-02net: dsa: microchip: lan937x: add phylink_get_caps supportArun Ramadoss3-0/+15
The internal phy of the LAN937x are capable of 100Mbps Full duplex. The xMII port of switch is capable of 10Mbps Full & Half Duplex, 100Mbps Full & Half Duplex and 1000Mbps Half duplex. xMII port also supports Tx and Rx Flow control. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-02net: dsa: microchip: lan937x: add MTU and fast_age supportArun Ramadoss4-0/+36
This patch add the support for port_max_mtu, port_change_mtu and port_fast_age dsa functionality. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-02net: dsa: microchip: lan937x: register mdio-busArun Ramadoss1-0/+74
This patch register mdio-bus for the lan937x series switch. mdio read and write uses the vphy for accessing the phy register. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-02net: dsa: microchip: lan937x: add phy read and write supportArun Ramadoss4-0/+156
This patch add support for the writing and reading of the phy registers. LAN937x uses the Vphy indirect addressing method for accessing the phys. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-02net: dsa: microchip: lan937x: add dsa_tag_protocolArun Ramadoss2-0/+12
This patch update the ksz_get_tag_protocol to return LAN937x specific tag if the chip id matches one of LAN937x series switch Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-02net: dsa: microchip: add DSA support for microchip LAN937xArun Ramadoss6-1/+333
Basic DSA driver support for lan937x and the device will be configured through SPI interface. It adds the lan937x_dev_ops in ksz_common.c file and tries to reuse the functionality of ksz9477 series switch. drivers/net/dsa/microchip/ path is already part of MAINTAINERS & the new files come under this path. Hence no update needed to the MAINTAINERS Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-07-02net: dsa: microchip: generic access to ksz9477 static and reserved tableArun Ramadoss4-10/+58
The ksz9477 and lan937x has few difference in the static and reserved table register 0x041C. For the ksz9477 if the bit 0 is 1 - read operation and 0 - write operation. But for lan937x bit 1:0 used for selecting the read/write operation, 01 - write and 10 - read. To use ksz9477 mdb add/del and enable_stp_addr for the lan937x, masks & shifts are introduced for ksz9477 & lan937x in ksz_common.c. Then updated the function with masks & shifts based on the switch instead of hard coding it. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-06-29net: dsa: microchip: count pause packets together will all other packetsOleksij Rempel1-2/+4
This switch is calculating tx/rx_bytes for all packets including pause. So, include rx/tx_pause counter to rx/tx_packets to make tx/rx_bytes fit to rx/tx_packets. Link: https://lore.kernel.org/all/20220624220317.ckhx6z7cmzegvoqi@skbuf/ Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2022-06-29net: dsa: microchip: add pause stats supportOleksij Rempel2-0/+20
Add support for pause specific stats. Tested on ksz9477. Signed-off-by: Oleksij Rempel <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: Jakub Kicinski <[email protected]>
2022-06-29net: dsa: microchip: move remaining register offset to ksz_chip_regArun Ramadoss2-42/+18
This patch moves the broadcast ctrl, multicast ctrl and start control registers from ksz_chip_dat to ksz_chip_reg. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-06-29net: dsa: microchip: add P_STP_CTRL to ksz_chip_regArun Ramadoss6-29/+35
This patch moves the stp_ctrl_reg from the ksz_chip_data to ksz_chip_reg structure. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-06-29net: dsa: microchip: change the size of reg from u8 to u16Arun Ramadoss3-14/+14
The register size for the ksz8 switches is u8 and for ksz9477 series is u16. To have common struct for ksz series switches the size of reg is increased from u8 to u16. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-06-29net: dsa: microchip: remove the struct ksz8Arun Ramadoss3-27/+4
This patch removes the struct ksz8 from ksz8.h which is no longer needed. The platform bus specific details are now deferenced through dev->priv. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-06-29net: dsa: microchip: move ksz8->shifts to ksz_commonArun Ramadoss4-56/+46
This patch moves ksz8->shifts from ksz8795.c to ksz_common.c. The shifts are dereferenced using dev->info->shifts. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-06-29net: dsa: microchip: move ksz8->masks to ksz_commonArun Ramadoss5-86/+81
This patch moves the ksz8->masks from ksz8795.c to ksz_common.c. The mask will be dereferenced using dev->info->masks. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-06-29net: dsa: microchip: move ksz8->regs to ksz_commonArun Ramadoss5-73/+79
This patch moves the ksz8->regs from ksz8795.c to the ksz_common.c. And the regs is dereferrenced using dev->info->regs. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-06-24net: dsa: microchip: common ksz_spi_probe for ksz switchesArun Ramadoss4-183/+69
As of now, there are two spi probes, one ksz8795_spi.c and other ksz9477_spi.c. This patch combines two files into single ksz_spi.c. The difference between the two are regmap config and struct ksz8. The regmap config is assigned based on the platform data. And struct ksz8 is left untouched, as it is used only ksz8795.c. It can be used for all other switches also in future. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2022-06-24net: dsa: microchip: remove the ksz8/ksz9477_switch_registerArun Ramadoss7-19/+4
This patch delete the ksz8_switch_register and ksz9477_switch_register since both are calling the ksz_switch_register function. Instead the ksz_switch_register is called from the probe function. Signed-off-by: Arun Ramadoss <[email protected]> Signed-off-by: David S. Miller <[email protected]>
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