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2019-04-18mtd: rawnand: meson: only initialize the RB completion onceMartin Blumenstingl1-1/+2
Documentation/scheduler/completion.txt states: Calling init_completion() on the same completion object twice is most likely a bug as it re-initializes the queue to an empty queue and enqueued tasks could get "lost" - use reinit_completion() in that case, but be aware of other races. Initialize nfc->completion in meson_nfc_probe using init_completion and change the call in meson_nfc_queue_rb to reinit_completion so the logic matches what the documentation suggests. Signed-off-by: Martin Blumenstingl <[email protected]> Tested-by:Liang Yang <[email protected]> Acked-by: Liang Yang <[email protected]> Tested-by:Liang Yang <[email protected]> Acked-by: Liang Yang <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: meson: use a void pointer for meson_nfc_dma_buffer_setupMartin Blumenstingl1-5/+5
This simplifies the code because it gets rid of the casts to an u8-pointer when passing "info_buf" from struct meson_nfc_nand_chip. Also it gets rid of the cast of the u8 databuf pointer to a void pointer. The logic inside meson_nfc_dma_buffer_setup() doesn't care about the pointer types themselves because it only passes them to dma_map_single which accepts a void pointer. No functional changes. Signed-off-by: Martin Blumenstingl <[email protected]> Tested-by:Liang Yang <[email protected]> Acked-by: Liang Yang <[email protected]> Tested-by:Liang Yang <[email protected]> Acked-by: Liang Yang <[email protected]> Tested-by:Liang Yang <[email protected]> Acked-by: Liang Yang <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: meson: use of_property_count_elems_of_size helperMartin Blumenstingl1-4/+1
Use the of_property_count_elems_of_size() helper instead of open-coding it's logic. As a bonus this will now error out if the "reg" property values use an incorrect size (anything other than sizeof(u32)). Signed-off-by: Martin Blumenstingl <[email protected]> Tested-by:Liang Yang <[email protected]> Acked-by: Liang Yang <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: meson: use struct_size macroMartin Blumenstingl1-2/+1
Use the recently introduced struct_size macro instead of open-coding it's logic. No functional changes. Signed-off-by: Martin Blumenstingl <[email protected]> Tested-by:Liang Yang <[email protected]> Acked-by: Liang Yang <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: marvell: Fix helper name in commentMiquel Raynal1-1/+1
Since the migration of the driver to stop using the legacy ->select_chip() hook, the marvell_nfc_select_chip() helper has been 'renamed' to marvell_nfc_select_target(). Update a left-over reference to this helper in a comment in the ->resume() path. Fixes: b25251414f6e00 ("mtd: rawnand: marvell: Stop implementing ->select_chip()") Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Boris Brezillon <[email protected]>
2019-04-18mtd: rawnand: sunxi: Add A23/A33 DMA supportMiquel Raynal1-2/+36
Allwinner NAND controllers can make use of DMA to enhance the I/O throughput thanks to ECC pipelining. DMA handling with A23/A33 NAND IP is a bit different than with the older SoCs, hence the introduction of a new compatible to handle: * the differences between register offsets, * the burst length change from 4 to minimum 8, * drive SRAM accesses through the AHB bus instead of the MBUS. Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: sunxi: Add a platform data structureMiquel Raynal1-5/+32
Before the introduction of A33 NAND DMA support, let's use a platform data structure for parameters that will differ. Right now, there is only one compatible with one data structure. Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: ingenic: Make jz4725b_ooblayout_ops staticYueHaibing1-1/+1
Fix sparse warning: drivers/mtd/nand/raw/ingenic/ingenic_nand.c:140:32: warning: symbol 'jz4725b_ooblayout_ops' was not declared. Should it be static? Reported-by: Hulk Robot <[email protected]> Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: ingenic: Add missing MODULE_* informationYueHaibing1-0/+3
gcc warning this: WARNING: modpost: missing MODULE_LICENSE() in drivers/mtd/nand/raw/ingenic/ingenic_ecc.o Add MODULE_LICENSE,MODULE_AUTHOR and MODULE_DESCRIPTION. Reported-by: Hulk Robot <[email protected]> Fixes: 9df5741a577e ("mtd: rawnand: ingenic: Separate top-level and SoC specific code") Signed-off-by: YueHaibing <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: denali: clean up coding styleMasahiro Yamada1-28/+26
Eliminate the following reports from 'scripts/checkpatch.pl --strict'. CHECK: Prefer kernel type 'u8' over 'uint8_t' CHECK: Prefer kernel type 'u32' over 'uint32_t' CHECK: Alignment should match open parenthesis I slightly changed denali_check_erased_page() to shorten it. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: denali: remove DENALI_NR_BANKS macroMasahiro Yamada1-5/+4
Use the runtime-detected denali->nbanks instead of hard-coded DENALI_NR_BANKS (=4). The actual number of banks depends on the IP configuration, and can be less than DENALI_NR_BANKS. It is pointless to touch registers of unsupported banks. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: denali: decouple controller and NAND chipsMasahiro Yamada4-217/+455
Currently, this driver sticks to the legacy NAND model because it was upstreamed before commit 2d472aba15ff ("mtd: nand: document the NAND controller/NAND chip DT representation"). However, relying on the dummy_controller is already deprecated. Switch over to the new controller/chip representation. The struct denali_nand_info has been split into denali_controller and denali_chip, to contain the controller data, per-chip data, respectively. One problem is, this commit changes the DT binding. So, as always, the backward compatibility must be taken into consideration. In the new binding, the controller node expects #address-cells = <1>; #size-cells = <0>; ... since the child nodes represent NAND chips. In the old binding, the controller node may have subnodes, but they are MTD partitions. The denali_dt_is_legacy_binding() exploits it to distinguish old/new platforms. Going forward, the old binding is only allowed for existing DT files. I updated the binding document. Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: denali_pci: rename goto labelsMasahiro Yamada1-4/+4
As Documentation/process/coding-style.rst says, choose label names which say what the goto does. The out_<action> label style is already used in denali_dt.c. Rename likewise for denali_pci.c Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: denali: use bool type instead of int where appropriateMasahiro Yamada2-13/+14
Use 'bool' type for the following boolean parameters. - write (write or read?) - dma_avail (DMA engine available or not?) Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: denali: switch over to ->exec_op() from legacy hooksMasahiro Yamada1-108/+143
Implement ->exec_op(), and remove the deprecated hooks. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: denali: remove unneeded casts in denali_{read, write}_pioMasahiro Yamada1-7/+5
Since (u32 *) can accept an opaque pointer, the explicit casting from (void *) to (u32 *) is redundant. Change the function argument type to remove the casts. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: denali: refactor raw page accessorsMasahiro Yamada2-265/+182
The Denali IP adopts the syndrome page layout (payload and ECC are interleaved). The *_page_raw() and *_oob() callbacks are complicated because they must hide the underlying layout used by the hardware, and always return contiguous in-band and out-of-band data. The Denali IP cannot reuse nand_{read,write}_page_raw_syndrome() in nand_base.c because its hardware ECC engine skips some of first bytes in OOB. That is why this driver implements specially-crafted *_page_raw() and *_oob() hooks. Currently, similar code is duplicated to reorganize the data layout. For example, denali_read_page_raw() and denali_write_page_raw() look almost the same. The complexity is partly due to the DMA transfer used for better performance of *_page_raw() accessors. On second thought, we do not need to care about their performance because MTD_OPS_RAW is rarely used. Let's focus on code cleanups rather than the performance. This commit removes the internal buffer for DMA, and factors out as much code as possible. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: denali: use more nand_chip pointers for internal functionsMasahiro Yamada1-27/+34
With the recent refactoring, the NAND driver hooks now take a pointer to nand_chip. Add to_denali() in order to convert (struct nand_chip *) to (struct denali_nand_info *) directly. It is more useful than the current mtd_to_denali(). I changed some helper functions to take (struct nand_chip *). This will avoid pointer conversion back and forth, and ease further development. Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: atmel: Fix spelling mistake in error messageMiquel Raynal1-1/+1
Wrong copy/paste from the previous block, the error message should refer to #size-cells instead of #address-cells. Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver") Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Tudor Ambarus <[email protected]>
2019-04-18mtd: rawnand: fsl_elbc: Make SW ECC workMarek Behún1-18/+34
Move the code that choses ECC into _attach_chip, which is executed only after the chip->ecc.* properties were loaded from device-tree. This way we know which ECC method was chosen by the device-tree and can set methods appropriately. The chip->ecc.*page methods should be set to fsl_elbc_*page only in HW ECC mode. Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: fsl_elbc: Implement RNDOUT commandMarek Behún1-0/+9
This is needed for SW ECC. Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: fsl_elbc: Cosmetic moveMarek Behún1-73/+73
Move the fsl_elbc_attach_chip function after the definitions of fsl_elbc_read_page and friends in preparation for the next patch. Signed-off-by: Marek Behún <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: fix build dependencyAnders Roxell2-2/+2
When enabling CONFIG_MTD_NAND_ECC_SW_BCH as a module, the MTD_NAND_ECC_SW_BCH depends on MTD_NAND, but the module controlled by MTD_NAND links against the module controlled by MTD_NAND_ECC_SW_BCH. This leads to the following link failure. aarch64-linux-gnu-ld: drivers/mtd/nand/raw/nand_base.o: in function `nand_cleanup': ../drivers/mtd/nand/raw/nand_base.c:5886: undefined reference to `nand_bch_free' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5886:(.text+0x9928): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `nand_bch_free' aarch64-linux-gnu-ld: drivers/mtd/nand/raw/nand_base.o: in function `nand_set_ecc_soft_ops': ../drivers/mtd/nand/raw/nand_base.c:5093: undefined reference to `nand_bch_calculate_ecc' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5093:(.text+0xe914): relocation truncated to fit: R_AARCH64_ADR_PREL_PG_HI21 against undefined symbol `nand_bch_calculate_ecc' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5093: undefined reference to `nand_bch_calculate_ecc' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5094: undefined reference to `nand_bch_correct_data' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5094:(.text+0xe934): relocation truncated to fit: R_AARCH64_ADR_PREL_PG_HI21 against undefined symbol `nand_bch_correct_data' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5094: undefined reference to `nand_bch_correct_data' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5148: undefined reference to `nand_bch_init' aarch64-linux-gnu-ld: ../drivers/mtd/nand/raw/nand_base.c:5148:(.text+0xebbc): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `nand_bch_init' Rework CONFIG_MTD_NAND_ECC_SW_BCH from tristate to bool, and then link the nand_bch.o file into nand.ko if its enabled. Fixes: 51ef1d0b2095 ("mtd: nand: Clarify Kconfig entry for software BCH ECC algorithm") Signed-off-by: Anders Roxell <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: nand: Remove useless line in KconfigMiquel Raynal1-1/+0
Prepare changes that will lay in this file to better express what is NAND related and what is not in menuconfig. Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: Clarify Kconfig entry MTD_NANDMiquel Raynal3-5/+5
MTD_NAND is large and encloses much more than what the symbol is actually used for: raw NAND. Clarify the symbol by naming it MTD_RAW_NAND instead. Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: Change Kconfig titles and re-order a bit the listMiquel Raynal2-177/+181
This list is a mess, while some items should probably not be in the raw/ sub-directory, others are definitely at the right place but not with the right description. Write uniform titles and group IPs by vendor. NAND controllers will appear under the list named "Raw/parallel NAND flash controllers" while the other drivers will appear under "Misc". Software ECC engines will later be moved out of the raw/ directory. Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: nand: Clarify Kconfig entry for software Hamming ECC entriesMiquel Raynal6-23/+21
The software Hamming ECC correction implementation is referred as MTD_NAND_ECC which is too generic. Rename it MTD_NAND_ECC_SW_HAMMING. Also rename MTD_NAND_ECC_SMC which is an SMC quirk in the Hamming implementation as MTD_NAND_ECC_SW_HAMMING_SMC. Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: nand: Clarify Kconfig entry for software BCH ECC algorithmMiquel Raynal5-12/+7
There is no point in having two distinct entries, merge them and rename the symbol for more clarity: MTD_NAND_ECC_SW_BCH Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08drivers: Remove explicit invocations of mmiowb()Will Deacon2-3/+0
mmiowb() is now implied by spin_unlock() on architectures that require it, so there is no reason to call it from driver code. This patch was generated using coccinelle: @mmiowb@ @@ - mmiowb(); and invoked as: $ for d in drivers include/linux/qed sound; do \ spatch --include-headers --sp-file mmiowb.cocci --dir $d --in-place; done NOTE: mmiowb() has only ever guaranteed ordering in conjunction with spin_unlock(). However, pairing each mmiowb() removal in this patch with the corresponding call to spin_unlock() is not at all trivial, so there is a small chance that this change may regress any drivers incorrectly relying on mmiowb() to order MMIO writes between CPUs using lock-free synchronisation. If you've ended up bisecting to this commit, you can reintroduce the mmiowb() calls using wmb() instead, which should restore the old behaviour on all architectures other than some esoteric ia64 systems. Acked-by: Linus Torvalds <[email protected]> Signed-off-by: Will Deacon <[email protected]>
2019-04-08mtd: rawnand: Get rid of chip->ecc_{strength,step}_dsBoris Brezillon14-77/+81
nand_device embeds a nand_ecc_req object which contains the minimum strength and step-size required by the NAND device. Drop the chip->ecc_{strength,step}_ds fields and use chip->base.eccreq.{strength,step_size} instead. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Get rid of chip->numchipsBoris Brezillon8-25/+17
The same information is provided by nanddev_ntargets(). Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Get rid of chip->chipsizeBoris Brezillon12-34/+38
The target size can now be returned by nanddev_get_targetsize(). Get rid of the chip->chipsize field and use this helper instead. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: rawnand: Get rid of chip->bits_per_cellBoris Brezillon5-8/+2
Now that we inherit from nand_device, we can use nand_device->memorg.bits_per_cell instead of having our own field at the nand_chip level. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Use nanddev_mtd_max_bad_blocks()Boris Brezillon2-40/+1
nanddev_mtd_max_bad_blocks() is implemented by the generic NAND layer and is already doing what we need. Reuse this function instead of having our own implementation. While at it, get rid of the ->max_bb_per_die and ->blocks_per_die fields which are now unused. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Move all page cache related fields to a sub-structBoris Brezillon1-14/+14
Looking at the field names it's hard to tell what ->data_buf, ->pagebuf and ->pagebuf_bitflips are for. Clarify that by moving those fields in a sub-struct named pagecache. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Provide a helper to get chip->data_bufBoris Brezillon7-49/+35
We plan to move cache related fields to a pagecache struct in nand_chip but some drivers access ->pagebuf directly to invalidate the cache before they start using ->data_buf. Let's provide an helper that returns a pointer to ->data_buf after invalidating the cache. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Initialize the nand_device objectBoris Brezillon2-7/+59
In order to use some of the nanddev_xxx() helpers, we need to initialize the nand_device object embedded in nand_chip using nanddev_init(). This requires implementing nand_ops. We also drop useless mtd->xxx initialization when they're already taken case of by nanddev_init(). Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Fill memorg during detectionBoris Brezillon11-44/+175
If we want to use the generic NAND layer, we need to have the memorg struct appropriately filled. Patch the detection code to fill this struct. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: spinand: Implement mtd->_max_bad_blocksBoris Brezillon1-0/+1
We just have to use nanddev_mtd_max_bad_blocks(). Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: nand: Add max_bad_eraseblocks_per_lun info to memorgBoris Brezillon6-15/+49
NAND datasheets usually give the maximum number of bad blocks per LUN and this number can be used to help upper layers decide how much blocks they should reserve for bad block handling. Add a max_bad_eraseblocks_per_lun to the nand_memory_organization struct and update the NAND_MEMORG() macro (and its users) accordingly. We also provide a default mtd->_max_bad_blocks() implementation. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: meson: set oob layout opsLiang Yang1-0/+2
Specify the oob layout operation to avoid no oob scheme defined for some nand flash. Fixes: 8fae856c5350 ("mtd: rawnand: meson: add support for Amlogic NAND flash controller") Signed-off-by: Liang Yang <[email protected]> Tested-by: Martin Blumenstingl <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: rawnand: vf610: Avoid a potential NULL pointer dereferenceAditya Pakki1-0/+3
of_match_device can return NULL if there is no matching device. Avoid a potential NULL pointer dereference by checking for the return value and passing the error upstream. Signed-off-by: Aditya Pakki <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: rawnand: ingenic: Move BBTs out of ECC areaPaul Cercueil1-0/+7
The generic layout for BBT markers will most likely overlap with our ECC bytes in the OOB, so move the BBT markers outside the OOB area. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: rawnand: ingenic: Add ooblayout for the Qi Ben NanonotePaul Cercueil1-1/+40
The Ben Nanonote from Qi Hardware expects a specific OOB layout on its NAND. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: rawnand: ingenic: Add support for the JZ4725BPaul Cercueil4-1/+353
The boot ROM of the JZ4725B SoC expects a specific OOB layout on the NAND, so we use it unconditionally in the ingenic-nand driver. Also add the jz4725b-bch driver to support the JZ4725B-specific BCH hardware. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: rawnand: ingenic: Add support for the JZ4740Paul Cercueil4-11/+245
Add support for probing the ingenic-nand driver on the JZ4740 SoC from Ingenic, and the jz4740-ecc driver to support the JZ4740-specific ECC hardware. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: rawnand: ingenic: Make use of ecc-engine propertyPaul Cercueil1-3/+10
Use the 'ecc-engine' standard property instead of the custom 'ingenic,bch-controller' custom property, which is now deprecated. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: rawnand: ingenic: Separate top-level and SoC specific codePaul Cercueil7-203/+310
The ingenic-nand driver uses an API provided by the jz4780-bch driver. This makes it difficult to support other SoCs in the jz4780-bch driver. To work around this, we separate the API functions from the SoC-specific code, so that these API functions are SoC-agnostic. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-05mtd: cfi: fix deadloop in cfi_cmdset_0002.c do_write_bufferLiu Jian1-1/+5
In function do_write_buffer(), in the for loop, there is a case chip_ready() returns 1 while chip_good() returns 0, so it never break the loop. To fix this, chip_good() is enough and it should timeout if it stay bad for a while. Fixes: dfeae1073583("mtd: cfi_cmdset_0002: Change write buffer to check correct value") Signed-off-by: Yi Huaijie <[email protected]> Signed-off-by: Liu Jian <[email protected]> Reviewed-by: Tokunori Ikegami <[email protected]> Signed-off-by: Richard Weinberger <[email protected]>
2019-04-01spi-nor: s25fl512s supports region lockingJonas Bonn1-1/+3
Both the BP[0-2] bits and the TBPROT bit are supported on this chip. Tested and verified on a Cypress s25fl512s. Signed-off-by: Jonas Bonn <[email protected]> Reviewed-by: Tudor Ambarus <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
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