| Age | Commit message (Collapse) | Author | Files | Lines |
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Add initial support for the Amlogic NAND flash controller which is
available on Meson SoCs.
Signed-off-by: Liang Yang <[email protected]>
Signed-off-by: Yixun Lan <[email protected]>
Signed-off-by: Jianxin Pan <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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nand_get_device() was complex for apparently no good reason. Let's
replace this locking scheme with 2 mutexes: one attached to the
controller and another one attached to the chip.
Every time the core calls nand_get_device(), it will first lock the
chip and if the chip is not suspended, will then lock the controller.
nand_release_device() will release both lock in the reverse order.
nand_get_device() can sleep, just like the previous implementation,
which means you should never call that from an atomic context.
We also get rid of
- the chip->state field, since all it was used for was flagging the
chip as suspended. We replace it by a field called chip->suspended
and directly set it from nand_suspend/resume()
- the controller->wq and controller->active fields which are no longer
needed since the new controller->lock (now a mutex) guarantees that
all operations are serialized at the controller level
- panic_nand_get_device() which would anyway be a no-op. Talking about
panic write, I keep thinking the rawnand implementation is unsafe
because there's not negotiation with the controller to know when it's
actually done with it's previous operation. I don't intend to fix
that here, but that's probably something we should look at, or maybe
we should consider dropping the ->_panic_write() implementation
Last important change to mention: we now return -EBUSY when someone
tries to access a device that as been suspended, and propagate this
error to the upper layer.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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We are about to simplify the locking in the rawnand framework, and part
of this simplication is about getting rid of chip->state, so let's
first patch drivers that check the state.
All of them do that to get a timeout value based on the operation that
is being executed. Since a timeout is, by definition, something that
is here to prevent hanging on an event that might never happen,
picking the maximum timeout value no matter the operation should be
harmless.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Stop initializing omap_gpmc_controller fields are declaration time and
replace that by a call to nand_controller_init(). Since the same object
might be shared by several NAND chips and the NAND controller driver
expects a ->probe() per-chip, we need to keep track of the
omap_gpmc_controller state (whether it's already been initialized or
not).
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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nand_controller->wq has never been meant to be used by NAND controller
drivers. This waitqueue is used by the framework to serialize accesses
to a NAND controller, and messing up with its state is a really bad
idea.
Declare a completion object in tmio_nand and use it to wait for RB
transitions.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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nand_controller_init() has been added to simplify nand_controller
struct initialization. Use this function instead of duplicating the
logic.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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One of the more common cases of allocation size calculations is finding
the size of a structure that has a zero-sized array at the end, along
with memory for some number of elements for that array. For example:
struct foo {
int stuff;
void *entry[];
};
instance = devm_kzalloc(dev, sizeof(struct foo) + sizeof(void *) * count, GFP_KERNEL);
Instead of leaving these open-coded and prone to type mistakes, we can
now use the new struct_size() helper:
instance = devm_kzalloc(dev, struct_size(instance, entry, count), GFP_KERNEL);
This code was detected with the help of Coccinelle.
Signed-off-by: Gustavo A. R. Silva <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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In non-EDO, tREA should be less than tRP to guarantee that the
controller does not sample the IO lines too early. Unfortunately, the
sunxi NAND controller does not allow us to have different values for
tRP and tREH (tRP = tREH = tRW / 2).
We have 2 options to overcome this limitation:
1/ Extend tRC to fulfil the tREA <= tRC / 2 constraint
2/ Use EDO mode (only works if timings->tRLOH > 0)
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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The datasheet specifies the upper four bits are reserved.
Testing on real hardware shows that these bits can indeed be nonzero.
Signed-off-by: Emil Lenngren <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Fix the struct description and use standard kernel-doc header format
(even if the file is not parsed by the doc generator).
We also replace tabs by a single space.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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And get rif of all legacy hooks and unused fields.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Replace the license text by an SPDX tag and fix MODULE_LICENSE() to
match GPL-2.0+.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Replace them by nand_chip pointers.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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nand_chip objects are sometimes called chip and sometimes nand. Rename
all of them into nand to make things consistent.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Use struct_size() to calculate sunxi_nand object size.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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sunxi_nand_chip objects are sometimes called chip and other times
called sunxi_nand. Make that consistent and name all occurrences
sunxi_nand.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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This patch adds the polling mode, a basic mode that do not need
any DMA channels. This mode is also useful for debug purpose.
Signed-off-by: Christophe Kerello <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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The driver adds the support for the STMicroelectronics FMC2 NAND
Controller found on STM32MP SOCs.
This patch is based on FMC2 command sequencer.
The purpose of the command sequencer is to facilitate the programming
and the reading of NAND flash pages with the ECC and to free the CPU
of sequencing tasks.
It requires one DMA channel for write and two DMA channels for read
operations.
Only NAND_ECC_HW mode is actually supported.
The driver supports a maximum 8k page size.
The following ECC strength and step size are currently supported:
- nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8)
- nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4)
- nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC
based on Hamming)
This patch has been tested on Micron MT29F8G08ABACAH4 and
MT29F8G16ABACAH4
Signed-off-by: Christophe Kerello <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Fix kernel-doc warnings in drivers/mtd/nand/raw:
../drivers/mtd/nand/raw/nand_base.c:420: warning: Function parameter or member 'chip' not described in 'nand_fill_oob'
../drivers/mtd/nand/raw/nand_bbt.c:173: warning: Function parameter or member 'this' not described in 'read_bbt'
../drivers/mtd/nand/raw/nand_bbt.c:173: warning: Excess function parameter 'chip' description in 'read_bbt'
Fixes: 0813621ba898a ("mtd: rawnand: Stop passing mtd_info objects to internal functions")
Signed-off-by: Randy Dunlap <[email protected]>
Cc: Boris Brezillon <[email protected]>
Cc: Miquel Raynal <[email protected]>
Cc: Richard Weinberger <[email protected]>
Cc: [email protected]
Acked-by: Miquel Raynal <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
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The manufacturer specific initialization has already been done when
block unlocking takes place, and if anything goes wrong during this
procedure we should call spinand_manufacturer_cleanup().
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Cc: <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Miquel Raynal <[email protected]>
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Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
the cache content to 0xFF (depends on vendor implementation), so we
must fill the page cache entirely even if we only want to program the
data portion of the page, otherwise we might corrupt the BBM or user
data previously programmed in OOB area.
Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
Reported-by: Stefan Roese <[email protected]>
Cc: <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Tested-by: Stefan Roese <[email protected]>
Reviewed-by: Stefan Roese <[email protected]>
Acked-by: Miquel Raynal <[email protected]>
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Commit 7a08dbaedd36 ("mtd: rawnand: Move ->setup_data_interface() to
nand_controller_ops") missed to invert the if-conditonal for denali.
Since then, the Denali NAND driver cannnot invoke setup_data_interface.
Fixes: 7a08dbaedd36 ("mtd: rawnand: Move ->setup_data_interface() to nand_controller_ops")
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Miquel Raynal <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
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The function jz_nand_ioremap_resource() needs a pointer to an __iomem
pointer as its last argument but this argument is declared as:
void * __iomem *base
Fix this by using the correct declaration:
void __iomem **base
which then also removes the following Sparse's warnings:
282:15: warning: incorrect type in assignment (different address spaces)
282:15: expected void *[noderef] <asn:2>
282:15: got void [noderef] <asn:2> *
322:57: warning: incorrect type in argument 4 (different address spaces)
322:57: expected void *[noderef] <asn:2> *base
322:57: got void [noderef] <asn:2> **
402:67: warning: incorrect type in argument 4 (different address spaces)
402:67: expected void *[noderef] <asn:2> *base
402:67: got void [noderef] <asn:2> **
Signed-off-by: Luc Van Oostenryck <[email protected]>
Acked-by: Miquel Raynal <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
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Hammering the "bank enable" (PBKEN) bit on and off between
every command crashes the Nomadik NHK15 with this message:
Scanning device for bad blocks
Unhandled fault: external abort on non-linefetch (0x008) at 0xcc95e000
pgd = (ptrval)
[cc95e000] *pgd=0b808811, *pte=40000653, *ppte=40000552
Internal error: : 8 [#1] PREEMPT ARM
Modules linked in:
CPU: 0 PID: 1 Comm: swapper Not tainted 4.20.0-rc2+ #72
Hardware name: Nomadik STn8815
PC is at fsmc_exec_op+0x194/0x204
(...)
After a discussion we (me and Boris Brezillon) start to suspect
that this bit does not immediately control the chip select line
at all, it rather enables access to the bank and the hardware
will drive the CS autonomously. If there is a NAND chip connected,
we should keep this enabled.
As fsmc_nand_setup() sets this bit, we can simply remove the
offending code.
Fixes: 550b9fc4e3af ("mtd: rawnand: fsmc: Stop implementing ->select_chip()")
Signed-off-by: Linus Walleij <[email protected]>
Acked-by: Miquel Raynal <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
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This patch fixes a memory corruption that occurred in the
qcom-nandc driver since it was converted to nand_scan().
On boot, an affected device will panic from a NPE at a weird place:
| Unable to handle kernel NULL pointer dereference at virtual address 0
| pgd = (ptrval)
| [00000000] *pgd=00000000
| Internal error: Oops: 80000005 [#1] SMP ARM
| CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.19.9 #0
| Hardware name: Generic DT based system
| PC is at (null)
| LR is at nand_block_isbad+0x90/0xa4
| pc : [<00000000>] lr : [<c0592240>] psr: 80000013
| sp : cf839d40 ip : 00000000 fp : cfae9e20
| r10: cf815810 r9 : 00000000 r8 : 00000000
| r7 : 00000000 r6 : 00000000 r5 : 00000001 r4 : cf815810
| r3 : 00000000 r2 : cfae9810 r1 : ffffffff r0 : cf815810
| Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
| Control: 10c5387d Table: 8020406a DAC: 00000051
| Process swapper/0 (pid: 1, stack limit = 0x(ptrval))
| [<c0592240>] (nand_block_isbad) from [<c0580a94>]
| [<c0580a94>] (allocate_partition) from [<c05811e4>]
| [<c05811e4>] (add_mtd_partitions) from [<c0581164>]
| [<c0581164>] (parse_mtd_partitions) from [<c057def4>]
| [<c057def4>] (mtd_device_parse_register) from [<c059d274>]
| [<c059d274>] (qcom_nandc_probe) from [<c0567f00>]
The problem is that the nand_scan()'s qcom_nand_attach_chip callback
is updating the nandc->max_cwperpage from 1 to 4. This causes the
sg_init_table of clear_bam_transaction() in the driver's
qcom_nandc_block_bad() to memset much more than what was initially
allocated by alloc_bam_transaction().
This patch restores the old behavior by reallocating the shared bam
transaction alloc_bam_transaction() after the chip was identified,
but before mtd_device_parse_register() (which is an alias for
mtd_device_register() - see panic) gets called. This fixes the
corruption and the driver is working again.
Cc: [email protected]
Fixes: 6a3cec64f18c ("mtd: rawnand: qcom: convert driver to nand_scan()")
Signed-off-by: Christian Lamparter <[email protected]>
Acked-by: Miquel Raynal <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
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Core changes:
- Parse the 4BAIT SFDP section
- Add a bunch of SPI NOR entries to the flash_info table
- Add the concept of SFDP fixups and use it to fix a bug on MX25L25635F
- A bunch of minor cleanups/comestic changes
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NAND core changes:
- kernel-doc miscellaneous fixes.
- Third batch of fixes/cleanup to the raw NAND core impacting various
controller drivers (ams-delta, marvell, fsmc, denali, tegra, vf610):
* Stopping to pass mtd_info objects to internal functions
* Reorganizing code to avoid forward declarations
* Dropping useless test in nand_legacy_set_defaults()
* Moving nand_exec_op() to internal.h
* Adding nand_[de]select_target() helpers
* Passing the CS line to be selected in struct nand_operation
* Making ->select_chip() optional when ->exec_op() is implemented
* Deprecating the ->select_chip() hook
* Moving the ->exec_op() method to nand_controller_ops
* Moving ->setup_data_interface() to nand_controller_ops
* Deprecating the dummy_controller field
* Fixing JEDEC detection
* Providing a helper for polling GPIO R/B pin
Raw NAND chip drivers changes:
- Macronix:
* Flagging 1.8V AC chips with a broken GET_FEATURES(TIMINGS)
Raw NAND controllers drivers changes:
- Ams-delta:
* Fixing the error path
* SPDX tag added
* May be compiled with COMPILE_TEST=y
* Conversion to ->exec_op() interface
* Dropping .IOADDR_R/W use
* Use GPIO API for data I/O
- Denali:
* Removing denali_reset_banks()
* Removing ->dev_ready() hook
* Including <linux/bits.h> instead of <linux/bitops.h>
* Changes to comply with the above fixes/cleanup done in the core.
- FSMC:
* Adding an SPDX tag to replace the license text
* Making conversion from chip to fsmc consistent
* Fixing unchecked return value in fsmc_read_page_hwecc
* Changes to comply with the above fixes/cleanup done in the core.
- Marvell:
* Preventing timeouts on a loaded machine (fix)
* Changes to comply with the above fixes/cleanup done in the core.
- OMAP2:
* Pass the parent of pdev to dma_request_chan() (fix)
- R852:
* Use generic DMA API
- sh_flctl:
* Converting to SPDX identifiers
- Sunxi:
* Write pageprog related opcodes to the right register: WCMD_SET (fix)
- Tegra:
* Stop implementing ->select_chip()
- VF610:
* Adding an SPDX tag to replace the license text
* Changes to comply with the above fixes/cleanup done in the core.
- Various trivial/spelling/coding style fixes.
SPI-NAND drivers changes:
- Removing the depreacated mt29f_spinand driver from staging.
- Adding support for:
* Toshiba TC58CVG2S0H
* GigaDevice GD5FxGQ4xA
* Winbond W25N01GV
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The opcodes used by the controller when doing batched page prog should
be written in NFC_REG_WCMD_SET not FC_REG_RCMD_SET. Luckily, the
default NFC_REG_WCMD_SET value matches the one we set in the driver
which explains why we didn't notice the problem.
Fixes: 614049a8d904 ("mtd: nand: sunxi: add support for DMA assisted operations")
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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marvell_nfc_wait_op() waits for completion during 'timeout_ms'
milliseconds before throwing an error. While the logic is fine, the
value of 'timeout_ms' is given by the core and actually correspond to
the maximum time the NAND chip will take to complete the
operation. Assuming there is no overhead in the propagation of the
interrupt signal to the the NAND controller (through the Ready/Busy
line), this delay does not take into account the latency of the
operating system. For instance, for a page write, the delay given by
the core is rounded up to 1ms. Hence, when the machine is over loaded,
there is chances that this timeout will be reached.
There are two ways to solve this issue that are not incompatible:
1/ Enlarge the timeout value (if so, how much?).
2/ Check after the waiting method if we did not miss any interrupt
because of the OS latency (an interrupt is still pending). In this
case, we assume the operation exited successfully.
We choose the second approach that is a must in all cases, with the
possibility to also modify the timeout value to be, e.g. at least 1
second in all cases.
Fixes: 02f26ecf8c77 ("mtd: nand: add reworked Marvell NAND controller driver")
Cc: [email protected]
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
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Commit e1e6255c311b ("mtd: rawnand: omap2: convert driver to
nand_scan()") moved part of the init code in the ->attach_chip hook
and at the same time changed the struct device object passed to
dma_request_chan() (&pdev->dev instead of pdev->dev.parent).
Fixes: e1e6255c311b ("mtd: rawnand: omap2: convert driver to nand_scan()")
Reported-by: Alexander Sverdlin <[email protected]>
Cc: <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Tested-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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nand_jedec_detect() should return 1 when the PARAM page parsing
succeeds, otherwise the core considers JEDEC detection failed and falls
back to ID-based detection.
Fixes: 480139d9229e ("mtd: rawnand: get rid of the JEDEC parameter page in nand_chip")
Cc: <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Acked-by: Miquel Raynal <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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There is a plan to build the kernel with -Wimplicit-fallthrough and
these places in the code produced warnings. Fix them up.
Signed-off-by: Mathieu Malaterre <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Add support for GigaDevice GD5F1G/2G/4GQ4xA SPI NAND.
Signed-off-by: Chuanhong Guo <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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We try to force NAND controller drivers to properly separate the NAND
controller object from the NAND chip one, so let's deprecate the dummy
controller object embedded in nand_chip to encourage them to create
their own instance.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Replace the license text by an SPDX tag.
Signed-off-by: Boris Brezillon <[email protected]>
Reviewed-by: Stefan Agner <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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The dummy controller is kept around to support old drivers. Let's
patch this one and declare our own nand_controller instance.
Signed-off-by: Boris Brezillon <[email protected]>
Reviewed-by: Stefan Agner <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Mimic what has been done in the core and avoid passing mtd_info object
internally.
Signed-off-by: Boris Brezillon <[email protected]>
Reviewed-by: Stefan Agner <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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checkpatch reports a bunch of coding style issues. Let's fix them
all in one step.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Add an SPDX GPL-2.0 tag and update MODULE_LICENSE() to match the
license text.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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The dummy controller is kept around to support old drivers. Let's
patch this one and declare our own nand_controller instance.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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nand_to_fsmc() is used almost everywhere except in
fsmc_setup_data_interface() where nand_get_controller_data() is used
instead. Make that consistent and drop the nand_set_controller_data()
call in the probe path.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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The kernel-doc describing struct fsmc_nand_data is not in sync with
the struct itself. Add missing entries and drop invalid ones.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Mimic what has been done in the core and stop passing mtd_info
objects to internal functions.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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In nand_scan_ident(), the controller driver resets every NAND chip.
This is done by sending NAND_CMD_RESET. The Denali IP provides
another way to do the equivalent thing; if a bit is set in the
DEVICE_RESET register, the controller sends the RESET command to
the corresponding device. denali_reset_banks() uses it to reset
all devices beforehand.
This redundant reset sequence was needed to know the actual number
of chips before calling nand_scan_ident(); if DEVICE_RESET fails,
there is no chip in that chip select. Then, denali_reset_banks()
sets denali->max_banks to the number of detected chips.
As commit f486287d2372 ("mtd: nand: denali: fix bank reset function
to detect the number of chips") explained, nand_scan_ident() issued
Set Features (0xEF) command to all CS lines, some of which may not be
connected with a chip. Then, the driver would wait for R/B# response,
which never happens.
This problem was solved by commit 107b7d6a7ad4 ("mtd: rawnand: avoid
setting again the timings to mode 0 after a reset"). In the current
code, nand_setup_data_interface() is called from nand_scan_tail(),
which is invoked after the chip detection.
Now, we can really remove the redundant denali_nand_banks() by simply
passing the maximum number of chip selects supported by this IP
(typically 4 or 8) to nand_scan(). Let's leave all the chip detection
process to nand_scan_ident().
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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The Denali NAND IP has no way to read out the current signal level
of the R/B# pin. Instead, denali_dev_ready() checks if the R/B#
transition has already happened. (The INTR__INT_ACT interrupt is
asserted at the rising edge of the R/B# pin.) It is not a correct
way to implement the ->dev_ready() hook.
In fact, it has a drawback; in the nand_scan_ident phase, the chip
detection iterates over maxchips until it fails to find a homogeneous
chip. For the last loop, nand_reset() fails if no chip is there.
If ->dev_ready hook exists, nand_command(_lp) calls nand_wait_ready()
after NAND_CMD_RESET. However, we know denali_dev_ready() never
returns 1 unless there exists a chip that toggles R/B# in that chip
select. Then, nand_wait_ready() just ends up with wasting 400 msec,
in the end, shows the "timeout while waiting for chip to become ready"
warning.
Let's remove the mis-implemented dev_ready hook, and fallback to
sending the NAND_CMD_STATUS and nand_wait_status_ready(), which
bails out more quickly.
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Correct the spelling mistake 'Regiters' -> 'Registers'.
Fixes: 961ba15c48dd ("mtd: rawnand: marvell: Fix clock resource by adding a register clock")
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
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Don't readw()/writew() data directly from/to GPIO port which is under
control of gpio-omap driver, use GPIO consumer API instead.
The driver should now work with any 8-bit bidirectional GPIO port, not
only OMAP.
Signed-off-by: Janusz Krzysztofik <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Data port used by the driver is actually an OMAP MPUIO device, already
under control of gpio-omap driver. For that reason we used to not
request the memory region of the port as that would fail because the
region is already busy. Despite that, we are still accessing the port
by just ioremapping it and performing read/write operations. Moreover,
we are doing that without any proteciton from other users legally
manipulating the port pins over GPIO API.
The plan is to convert the driver to access the port over GPIO consumer
API. Before that happens, already prevent from other users accessing
the port pins by requesting an array of its GPIO descriptors.
Signed-off-by: Janusz Krzysztofik <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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->setup_data_interface() is a controller specific method and should
thus be placed in nand_controller_ops.
In order to make that work with controllers that support keeping
pre-configured timings we need to add a new NAND_KEEP_TIMINGS flag to
inform the core it should skip the timings selection step.
Signed-off-by: Boris Brezillon <[email protected]>
Tested-by: Janusz Krzysztofik <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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->exec_op() is a controller method and has nothing to do in the
nand_chip struct. Let's move it to the nand_controller_ops struct and
adjust the core and drivers accordingly.
Signed-off-by: Boris Brezillon <[email protected]>
Tested-by: Janusz Krzysztofik <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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