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Signed-off-by: Joern Engel <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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ARM is the only known user of this at the moment.
Prevent allyes builds for other archs from failing
Signed-off-by: Thomas Gleixner <[email protected]>
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Move the architecture dependend code into include/asm/mtd-xip.h
Signed-off-by: Thomas Gleixner <[email protected]>
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Including asm/hardware.h has to be done in linux/mtd/xip.h. Otherwise
it breaks allyes compiles.
Signed-off-by: Thomas Gleixner <[email protected]>
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Author: Vitaly Wool <[email protected]>
Signed-off-by: Todd Poynor <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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Signed-off-by: Thomas Gleixner <[email protected]>
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Check for errors besides infinite loops when writing and erasing.
Signed-off-by: Eric W. Biederman <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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This reworks the XIP locking to make sure no lock primitive is ever
called from XIP disabled paths even if in theory they should not
cause any reschedule. Relying on the current spinlock implementation
is rather fragile and not especially clean from an abstraction pov.
The recent RT work makes it even more obvious.
Signed-off-by: Nicolas Pitre <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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adjust chip-relative offsets to
block address, write to block address + 2 per recent datasheets.
Signed-off-by: Todd Poynor <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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Signed-off-by: Nicolas Pitre <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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to make sure the flash is in array mode whenever we're about to
reboot. This is especially useful to allow "soft" reboot to work
which consists of branching back into the bootloader.
Signed-off-by: Nicolas Pitre <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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Signed-off-by: Todd Poynor <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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Skip jiffy delay after each block lock/unlock for Intel CFI flash
with the "Instant Individual Block Locking" feature bit set.
Signed-off-by: Todd Poynor <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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Signed-off-by: Thomas Gleixner <[email protected]>
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oldstate has to be reset to FL_READY after sync completion.
Signed-off-by: Nicolas Pitre <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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The change makes the code endianess aware and replaces the bogus
nested loop to or the status flags together.
Signed-off-by: Thomas Gleixner <[email protected]>
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The OTP code is rather broken without this.
Signed-off-by: Nicolas Pitre <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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Signed-off-by: Ben Dooks <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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The change to the generic probe to look for the
smallest width of chip first is causing some problems
on boards with a single 16bit device.
The problem seems to be the jedec_match() is truncating
the device-id read from the table to match against the
one read from the hardware, causing a match against the
partial id of some chips with 16bit IDs (such as the
SST39LF160)
This fixes things for my own board, but something may
need to be done if the same problem is exhibited for
chips with an 8bit ID
Signed-off-by: Ben Dooks <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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This enables support for reading, writing and locking so called
"Protection Registers" present on some flash chips.
A subset of them are pre-programmed at the factory with a
unique set of values. The rest is user-programmable.
Signed-off-by: Nicolas Pitre <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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add structure definition for OTP region info
Signed-off-by: Nicolas Pitre <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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* Removed table entry for AM29BDS643D, since device ID clashes with AM29DL640G
and both chips support CFI.
Signed-off-by: Jonas Holmberg <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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Try larger numbers of chips before smaller
numbers of chips across the bus width.
This means we'll avoid misdetecting a 2 x16 array as 1 x32 if the
high 16-bits happen to read as zeros in the QRY area.
Signed-off-by: Russell King <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
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Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
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