| Age | Commit message (Collapse) | Author | Files | Lines |
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Get rid of boilerplate code by using module_platform_driver macro.
Signed-off-by: Axel Lin <[email protected]>
Acked-by: Jan Glauber <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The new lockdep annotations for completions cause a warning in the
mmc test module, in a function that now has four 150 byte structures
on the stack:
drivers/mmc/core/mmc_test.c: In function 'mmc_test_nonblock_transfer.constprop':
drivers/mmc/core/mmc_test.c:892:1: error: the frame size of 1360 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]
The mmc_test_ongoing_transfer function evidently had a similar problem,
and worked around it by using dynamic allocation.
This generalizes the approach used by mmc_test_ongoing_transfer() and
applies it to mmc_test_nonblock_transfer() as well.
Fixes: cd8084f91c02 ("locking/lockdep: Apply crossrelease to completions")
Signed-off-by: Arnd Bergmann <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Tested-by: Adrian Hunter <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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eSDHC is not a standard SD host controller. SDHCI_CAPABILITIES_1
register address is 0x44 while it's 0x114 (ESDHC_CAPABILITIES_1)
for eSDHC.
Signed-off-by: Yangbo Lu <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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SD controller with SDHCI_QUIRK_NO_HISPD_BIT quirk probably
use high speed enable bit for other purpose. So this bit
shouldn't be changed for high speed enabling for this type of
SD controller.
Signed-off-by: Yangbo Lu <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Now that sdhci_set_bus_width() supports 8-bit bus widths based on the
MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-s3c version with
the generic sdhci version.
Signed-off-by: Michał Mirosław <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Acked-by: Jaehoon Chung <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Now that sdhci_set_bus_width() supports 8-bit bus widths based on the
MMC_CAP_8_BIT_DATA capability flag, replace the sdhci-pci version with
the generic sdhci version.
Signed-off-by: Michał Mirosław <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Now that sdhci_set_bus_width() supports 8-bit bus widths based on the
MMC_CAP_8_BIT_DATA capability flag, replace the tegra version with the
generic sdhci version.
Signed-off-by: Michał Mirosław <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Hosts supporting 8-bit bus are marked accordingly. If MMC_CAP_8_BIT_DATA
is not among host capabilities, 8BITBUS bit will never be set and it
is not cleared in case some non-SDHCI3 host uses it for something else.
Signed-off-by: Michał Mirosław <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Tested-by: Thierry Reding <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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CQE needs to be off for the host controller to accept non-CQ commands. Turn
off the CQE before sending commands, and ensure it is off in any reset or
power management paths, or re-tuning.
Signed-off-by: Adrian Hunter <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Xenon sdh controller requests proper SD bus voltage select
bits programmed even with vmmc power supply. Any reserved
value(100b-000b) programmed in this field will lead to controller
ignore SD bus power bit and keep its value at zero.
Add set_power callback to handle this.
Signed-off-by: Zhoujie Wu <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Tested-by: Gregory CLEMENT <[email protected]>
Fixes: 3a3748dba881 ("mmc: sdhci-xenon: Add Marvell Xenon SDHC core functionality")
Cc: <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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mmc_return_hold() / mmc_retune_release() are used around a group of
commands to prevent re-tuning between the commands. Re-tuning can still
happen before the first command. In some cases, re-tuning must be
prevented entirely. Add mmc_retune_hold_now() for that purpose. It is
added in preparation for CQE support where it will be used by CQE recovery.
Signed-off-by: Adrian Hunter <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Packed commands support was removed but some bits got left behind. Remove
them.
Signed-off-by: Adrian Hunter <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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sunxi_mmc_clk_set_phase expects the actual card clock rate to be passed
to it. When the internal divider code was reworked in change ("mmc: sunxi:
Support MMC DDR52 transfer mode with new timing mode"), this requirement
was missed, and the module clock rate was passed in instead. This broke 8
bit DDR MMC on old controllers, as the module clock rate is double the
card clock rate, for which we have no valid delay settings.
Fix this by applying the internal divider to the clock rate right after
we configure it in hardware.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Make use of the 64 bit sdbuf width on Renesas R-Car Gen3. If the
registers are 8 byte apart, the width is also 64 bit. For all others,
the width is 32 bit, even if the registers are only 16 bit apart.
Signed-off-by: Wolfram Sang <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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We don't use this new define yet, but it is helpful to document which
versions we know of.
Signed-off-by: Wolfram Sang <[email protected]>
Tested-by: Chris Brandt <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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It is documented, so enable it to follow the recommendation in the docs
and also save a few cycles.
Signed-off-by: Wolfram Sang <[email protected]>
Tested-by: Chris Brandt <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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There is one SDHI instance on Gen2 which does not have the CBSY bit.
So, turn CBSY usage into an extra flag and set it accordingly. This has
the additional advantage that we can also set it for other incarnations
later.
Signed-off-by: Wolfram Sang <[email protected]>
Tested-by: Chris Brandt <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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usb_device_id are not supposed to change at runtime. All functions
working with usb_device_id provided by <linux/usb.h> work with
const usb_device_id. So mark the non-const structs as const.
Signed-off-by: Arvind Yadav <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Add Xenon specific system-level suspend and resume support.
Especially during resume, re-configure Xenon specific registers
since registers setting will be lost in suspend if Xenon is power off.
Signed-off-by: Hu Ziji <[email protected]>
Signed-off-by: Zhoujie Wu <[email protected]>
Tested-by: Jisheng Zhang <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Per the databook of designware mmc controller 2.70a, table 3-2, cmd
done interrupt should be fired as soon as the the cmd is sent via
cmd line. And the response timeout interrupt should be generated
unconditioinally as well if the controller doesn't receive the resp.
However that doesn't seem to meet the fact of rockchip specified Soc
platforms using dwmmc. We have continuously found the the cmd done or
response timeout interrupt missed somehow which took us a long time to
understand what was happening. Finally we narrow down the root to
the reconstruction of sample circuit for dwmmc IP introduced by
rockchip and the buggy design sweeps over all the existing rockchip
Socs using dwmmc disastrously.
It seems no way to work around this bug without the proper break-out
mechanism so that we seek for a parallel pair the same as the handling
for missing data response timeout, namely dto timer. Adding this cto
timer seems easily to handle this bug but it's hard to restrict the code
under the rockchip specified context. So after merging this patch, it
sets up the cto timer for all the platforms using dwmmc IP which isn't
ideal but at least we don't advertise new quirk here. Fortunately, no
obvious performance regression was found by test and the pre-existing
similar catch-all timer for sdhci has proved it's an acceptant way to
make the code as robust as possible.
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=196321
Signed-off-by: Addy Ke <[email protected]>
Signed-off-by: Ziyuan Xu <[email protected]>
[shawn.lin: rewrite the code and the commit msg throughout]
Signed-off-by: Shawn Lin <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Add sd card support for hi3660 soc
Signed-off-by: Li Wei <[email protected]>
Signed-off-by: Chen Jun <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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This commit modifies dw_mci_probe(), it moves reset assertion before
drv_data->init(host)
Some driver needs to access controller registers in its .init() ops. So,
in order to make such access safe, we should do controller reset before
.init() being called.
Signed-off-by: Wei Li <[email protected]>
Signed-off-by: Guodong Xu <[email protected]>
Signed-off-by: Chen Jun <[email protected]>
Reviewed-by: Shawn Lin <[email protected]>
Signed-off-by: Jaehoon Chung <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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clk_prepare_enable() can fail here and we must check its return value.
Signed-off-by: Arvind Yadav <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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clk_prepare_enable() can fail here and we must check its return value.
Signed-off-by: Arvind Yadav <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Programming legacy HOST SDMA Buffer Boundary bits in Block Size Register
(0x04) is not supported in Qualcomm sdhci controllers. Writing to this
would cause the controller not to transfer last block in case block size
is 4 bytes or less.
This issue was noticed while testing sdio wlan card on Qcom DB410c board.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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This patch adds sdma_boundary member to struct sdhci_host to give more
flexibility to drivers to control the sdma boundary buffer value and
also to fix issue on some sdhci controllers which are broken when
HOST SDMA Buffer Boundary is programmed in Block Size Register (0x04)
when using ADMA. Qualcomm sdhci controller is one of such type, writing
to this bits is un-supported.
Default value of sdma_boundary is set to SDHCI_DEFAULT_BOUNDARY_ARG.
Signed-off-by: Srinivas Kandagatla <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The structure renesas_sdhi_internal_dmac_dma_ops is only passed as
the second argument to renesas_sdhi_probe, which is const, so
renesas_sdhi_internal_dmac_dma_ops can be const too.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The sdhci_pltfm_data structure is only passed as the second argument
of sdhci_pltfm_init, which is const, so the sdhci_pltfm_data structure
can be const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The sdhci_pltfm_data structure is only passed as the second argument
of sdhci_pltfm_init, which is const, while the sdhci_ops structure
is only stored in the ops field of a sdhci_pltfm_data structure,
which is also const. Thus both kinds of structures can be const as
well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <[email protected]>
Acked-by: Michal Simek <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The sdhci_pltfm_data structure is only passed as the second argument
of sdhci_pltfm_init, which is const, while the sdhci_ops structure
is only stored in the ops field of a sdhci_pltfm_data structure,
which is also const. Thus both kinds of structures can be const as
well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The sdhci_pltfm_data structure is only passed as the second argument
of sdhci_pltfm_init, which is const, while the sdhci_ops structure
is only stored in the ops field of a sdhci_pltfm_data structure,
which is also const. Thus both kinds of structures can be const as
well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The sdhci_pltfm_data structure is only passed as the second argument
of sdhci_pltfm_init, which is const, so the sdhci_pltfm_data structure can
be const as well.
Done with the help of Coccinelle.
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Per the SD physical layer simplified specification V4.10,
section 4.6.2, CSD version 1.0 SD card should use taac, nsac
and r2w_factor for calculating the data access time. But the
taac and nsac for SDHC(CSD version 2.0) are always fixed and
the software should use the recommended value for timeout. When
parsing the CSD, we sanely set them to zero for SDHC(CSD version
2.0), all the calculation for timeout_ns and timeout_clk is zero
as well. So what we actually want to limit here is either SDHC
case or unreasonable timeout reported by the cards. In principle
we should at least be able to remove the bogus check for the
mmc_card_blockaddr.
Signed-off-by: Shawn Lin <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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One issue was found on a removable high speed sd card with
runtime pm enabled.
When SD card is unplugged, it keep printing "Switching to 3.3V
signalling voltage failed".
And found below sequence triggers the error.
mmc_rescan
-> mmc_sd_detect
-> mmc_power_off -- mmc->ios.vdd is updated to 0.
-> mmc_claim_host
-> sdhci_runtime_resume_host
-> sdhci_start_signal_voltage_switch
-> mmc_regulator_set_vqmmc
-> mmc_ocrbitnum_to_vdd
When mmc_ocrbitnum_to_vdd is called, the mmc->ios.vdd is 0, so it
always return -EINVAL. The signal switch will always fail and
print out warning.
Ignore restoring the I/O state when runtime resume if MMC_POWER_OFF.
Signed-off-by: Zhoujie Wu <[email protected]>
Signed-off-by: Adrian Hunter <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The A83T MMC support code introduces the timings mode switch, however
such a switch doesn't exist on new SoCs with only new timings mode.
Only execute the switch if the SoC really have the timings mode switch,
to fix the regression shown on new timings mode only SoCs (A64, H5,
etc).
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Some SoCs do not support clk delays for MMC in the clock control unit.
These include the old controllers in A10/A10s/A13/R8, and the new eMMC
controller in A64. The config structure for these controllers do not
specify clk_delays, but the check for this was replaced in change
"mmc: sunxi: Support controllers that can use both old and new timings".
This patch adds back the check for clk_delays, and also adds comments
for both checks in sunxi_mmc_clk_set_phase().
Signed-off-by: Chen-Yu Tsai <[email protected]>
Tested-by: Icenowy Zheng <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The third MMC controller (MMC2) on the Allwinner A83T SoC is slightly
different. It supports a wider 8-bit bus, has a dedicated controllable
reset pin for eMMC, and a "new timing mode" which is supposed to deliver
better signals and thus better performance.
Add a compatible for this one to use the new timing mode not found in the
other controllers.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The MMC controller can support DDR52 transfers under the new timing
mode. According to the BSP kernel, the module clock has to be double
the card clock, regardless of the bus width. The default timings in
the hardware can be used.
This also reworks the code setting the internal divider, getting rid
of a extra conditional.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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On the SoCs that introduced the new timing mode for MMC controllers,
both the old (where the clock delays are set in the CCU) and new
(where the clock delays are set in the MMC controller) timing modes
are available, and we have to support them both. However there are
two bits that control which mode is active. One is in the CCU, the
other is in the MMC controller. The settings on both sides must be
the same, or nothing will work.
The sunxi-ng clock driver provides an API to query and set the
active timing mode. At probe time, we try to set the active mode
to the "new timing mode". If it succeeds, we can then use the MMC
controller in the new mode. If not, we fall back to the old mode.
Signed-off-by: Chen-Yu Tsai <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Provide a whitelist for Gen3 SoC ES versions for both the SYS DMAC and
internal DMAC variants of the SDHI driver. This is to allow drivers to
only initialise for Gen3 SoC ES versions for which they are the appropriate
DMAC implementation. Currently internal DMAC is the appropriate
implementation for all supported Gen3 SoC ES versions.
Signed-off-by: Simon Horman <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Per the spec of JESD84-B51, section 7.3, replace tacc with taac to
fix the obvious typo.
Signed-off-by: Shawn Lin <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Detected by sparse.
Signed-off-by: Masahiro Yamada <[email protected]>
Acked-by: Adrian Hunter <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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Sparse reports "warning: cast to restricted __be32".
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The mmc_host_ops structure is only stored in the ops field of an
mmc_host structure, which is declared as const. Thus the mmc_host_ops
structure itself can be const.
Done with the help of Coccinelle.
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct mmc_host_ops i@p = { ... };
@ok1@
struct mmc_host *mmc;
identifier r.i;
position p;
@@
mmc->ops = &i@p
@bad@
position p != {r.p,ok1.p};
identifier r.i;
struct mmc_host_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct mmc_host_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <[email protected]>
Acked-by: Stefan Wahren <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The mmc_host_ops structure is only stored in the ops field of an
mmc_host structure, which is declared as const. Thus the mmc_host_ops
structure itself can be const.
Done with the help of Coccinelle.
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct mmc_host_ops i@p = { ... };
@ok1@
struct mmc_host *mmc;
identifier r.i;
position p;
@@
mmc->ops = &i@p
@bad@
position p != {r.p,ok1.p};
identifier r.i;
struct mmc_host_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct mmc_host_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The mmc_host_ops structure is only stored in the ops field of an
mmc_host structure, which is declared as const. Thus the mmc_host_ops
structure itself can be const.
Done with the help of Coccinelle.
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct mmc_host_ops i@p = { ... };
@ok1@
struct mmc_host *mmc;
identifier r.i;
position p;
@@
mmc->ops = &i@p
@bad@
position p != {r.p,ok1.p};
identifier r.i;
struct mmc_host_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct mmc_host_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The mmc_host_ops structure is only stored in the ops field of an
mmc_host structure, which is declared as const. Thus the mmc_host_ops
structure itself can be const.
Done with the help of Coccinelle.
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct mmc_host_ops i@p = { ... };
@ok1@
struct mmc_host *mmc;
identifier r.i;
position p;
@@
mmc->ops = &i@p
@bad@
position p != {r.p,ok1.p};
identifier r.i;
struct mmc_host_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct mmc_host_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The mmc_host_ops structure is only stored in the ops field of an
mmc_host structure, which is declared as const. Thus the mmc_host_ops
structure itself can be const.
Done with the help of Coccinelle.
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct mmc_host_ops i@p = { ... };
@ok1@
struct mmc_host *mmc;
identifier r.i;
position p;
@@
mmc->ops = &i@p
@bad@
position p != {r.p,ok1.p};
identifier r.i;
struct mmc_host_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct mmc_host_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The mmc_host_ops structure is only stored in the ops field of an
mmc_host structure, which is declared as const. Thus the mmc_host_ops
structure itself can be const.
Done with the help of Coccinelle.
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct mmc_host_ops i@p = { ... };
@ok1@
struct mmc_host *mmc;
identifier r.i;
position p;
@@
mmc->ops = &i@p
@bad@
position p != {r.p,ok1.p};
identifier r.i;
struct mmc_host_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct mmc_host_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
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The mmc_host_ops structure is only stored in the ops field of an
mmc_host structure, which is declared as const. Thus the mmc_host_ops
structure itself can be const.
Done with the help of Coccinelle.
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct mmc_host_ops i@p = { ... };
@ok1@
struct mmc_host *mmc;
identifier r.i;
position p;
@@
mmc->ops = &i@p
@bad@
position p != {r.p,ok1.p};
identifier r.i;
struct mmc_host_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct mmc_host_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <[email protected]>
Signed-off-by: Ulf Hansson <[email protected]>
|