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2021-02-01Merge branch 'fixes' into nextUlf Hansson2-1/+12
2021-02-01mmc: core: Exclude unnecessary header fileChanWoo Lee1-1/+0
From the 4.19 kernel, thread related code has been removed in queue.c. So we can exclude unnecessary header file. Signed-off-by: ChanWoo Lee <[email protected]> Acked-by: Coly Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: mmci: Add support for probing bus voltage level translatorMarek Vasut1-5/+65
Add support for testing whether bus voltage level translator is present and operational. This is useful on systems where the bus voltage level translator is optional, as the translator can be auto-detected by the driver and the feedback clock functionality can be disabled if it is not present. This requires additional pinmux state, "init", where the CMD, CK, CKIN lines are not configured, so they can be claimed as GPIOs early on in probe(). The translator test sets CMD high to avoid interfering with a card, and then verifies whether signal set on CK is detected on CKIN. If the signal is detected, translator is present, otherwise the CKIN feedback clock are disabled. Cc: Alexandre Torgue <[email protected]> Cc: Ludovic Barre <[email protected]> Tested-by: Yann Gautier <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Marek Vasut <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-msm: add Inline Crypto Engine supportEric Biggers2-4/+273
Add support for Qualcomm Inline Crypto Engine (ICE) to sdhci-msm. The standard-compliant parts, such as querying the crypto capabilities and enabling crypto for individual MMC requests, are already handled by cqhci-crypto.c, which itself is wired into the blk-crypto framework. However, ICE requires vendor-specific init, enable, and resume logic, and it requires that keys be programmed and evicted by vendor-specific SMC calls. Make the sdhci-msm driver handle these details. This is heavily inspired by the similar changes made for UFS, since the UFS and eMMC ICE instances are very similar. See commit df4ec2fa7a4d ("scsi: ufs-qcom: Add Inline Crypto Engine support"). I tested this on a Sony Xperia 10, which uses the Snapdragon 630 SoC, which has basic upstream support. Mainly, I used android-xfstests (https://github.com/tytso/xfstests-bld/blob/master/Documentation/android-xfstests.md) to run the ext4 and f2fs encryption tests in a Debian chroot: android-xfstests -c ext4,f2fs -g encrypt -m inlinecrypt These tests included tests which verify that the on-disk ciphertext is identical to that produced by a software implementation. I also verified that ICE was actually being used. Acked-by: Adrian Hunter <[email protected]> Reviewed-by: Satya Tangirala <[email protected]> Signed-off-by: Eric Biggers <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: cqhci: add cqhci_host_ops::program_keyEric Biggers2-9/+17
On Snapdragon SoCs, the Linux kernel isn't permitted to directly access the standard CQHCI crypto configuration registers. Instead, programming and evicting keys must be done through vendor-specific SMC calls. To support this hardware, add a ->program_key() method to 'struct cqhci_host_ops'. This allows overriding the standard CQHCI crypto key programming / eviction procedure. This is inspired by the corresponding UFS crypto support, which uses these same SMC calls. See commit 1bc726e26ef3 ("scsi: ufs: Add program_key() variant op"). Acked-by: Adrian Hunter <[email protected]> Reviewed-by: Satya Tangirala <[email protected]> Reviewed-and-tested-by: Peng Zhou <[email protected]> Signed-off-by: Eric Biggers <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: cqhci: add support for inline encryptionEric Biggers5-3/+404
Add support for eMMC inline encryption using the blk-crypto framework (Documentation/block/inline-encryption.rst). eMMC inline encryption support is specified by the upcoming JEDEC eMMC v5.2 specification. It is only specified for the CQ interface, not the non-CQ interface. Although the eMMC v5.2 specification hasn't been officially released yet, the crypto support was already agreed on several years ago, and it was already implemented by at least two major hardware vendors. Lots of hardware in the field already supports and uses it, e.g. Snapdragon 630 to give one example. eMMC inline encryption support is very similar to the UFS inline encryption support which was standardized in the UFS v2.1 specification and was already upstreamed. The only major difference is that eMMC limits data unit numbers to 32 bits, unlike UFS's 64 bits. Like we did with UFS, make the crypto support opt-in by individual drivers; don't enable it automatically whenever the hardware declares crypto support. This is necessary because in every case we've seen, some extra vendor-specific logic is needed to use the crypto support. Co-developed-by: Satya Tangirala <[email protected]> Signed-off-by: Satya Tangirala <[email protected]> Acked-by: Adrian Hunter <[email protected]> Reviewed-by: Satya Tangirala <[email protected]> Reviewed-and-tested-by: Peng Zhou <[email protected]> Signed-off-by: Eric Biggers <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: cqhci: initialize upper 64 bits of 128-bit task descriptorsEric Biggers1-10/+20
Move the task descriptor initialization into cqhci_prep_task_desc(). In addition, make it explicitly initialize all 128 bits of the task descriptor if the host controller is using 128-bit task descriptors, rather than relying on the implicit zeroing from dmam_alloc_coherent(). This is needed to prepare for CQHCI inline encryption support, which requires 128-bit task descriptors and uses the upper 64 bits. Acked-by: Adrian Hunter <[email protected]> Reviewed-by: Satya Tangirala <[email protected]> Reviewed-and-tested-by: Peng Zhou <[email protected]> Signed-off-by: Eric Biggers <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: cqhci: rename cqhci.c to cqhci-core.cEric Biggers2-0/+1
Rename cqhci.c to cqhci-core.c so that another source file can be added to the cqhci module without having to rename the module. Acked-by: Adrian Hunter <[email protected]> Reviewed-and-tested-by: Peng Zhou <[email protected]> Signed-off-by: Eric Biggers <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: core: Add basic support for inline encryptionEric Biggers8-0/+107
In preparation for adding CQHCI crypto engine (inline encryption) support, add the code required to make mmc_core and mmc_block aware of inline encryption. Specifically: - Add a capability flag MMC_CAP2_CRYPTO to struct mmc_host. Drivers will set this if the host and driver support inline encryption. - Embed a blk_keyslot_manager in struct mmc_host. Drivers will initialize this (as a device-managed resource) if the host and driver support inline encryption. mmc_block registers this keyslot manager with the request_queue of any MMC card attached to the host. - Make mmc_block copy the crypto keyslot and crypto data unit number from struct request to struct mmc_request, so that drivers will have access to them. - If the MMC host is reset, reprogram all the keyslots to ensure that the software state stays in sync with the hardware state. Co-developed-by: Satya Tangirala <[email protected]> Signed-off-by: Satya Tangirala <[email protected]> Acked-by: Adrian Hunter <[email protected]> Reviewed-by: Satya Tangirala <[email protected]> Reviewed-and-tested-by: Peng Zhou <[email protected]> Signed-off-by: Eric Biggers <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-aspeed: Fix kunit-related build errorAndrew Jeffery2-6/+45
Randy found that with the following Kconfig settings we have duplicate definitions (e.g. __inittest()) in sdhci-of-aspeed due to competing module_init()/module_exit() calls from kunit and driver the itself. ``` CONFIG_MMC_SDHCI_OF_ASPEED=m CONFIG_MMC_SDHCI_OF_ASPEED_TEST=y ``` Conditionally open-code the kunit initialisation to avoid the error. Fixes: 7efa02a981d6 ("mmc: sdhci-of-aspeed: Add KUnit tests for phase calculations") Reported-by: Randy Dunlap <[email protected]> Signed-off-by: Andrew Jeffery <[email protected]> Acked-by: Randy Dunlap <[email protected]> # build-tested Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: remove sirf prima/atlas driverArnd Bergmann3-248/+0
The CSR SiRF prima2/atlas platforms are getting removed, so this driver is no longer needed. Cc: Barry Song <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]> Acked-by: Barry Song <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: remove dw_mmc-zx driverArnd Bergmann4-276/+0
The zte zx platform is getting removed, so this driver is no longer needed. Cc: Jun Nie <[email protected]> Cc: Shawn Guo <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: atmel-mci: Assign boolean values to a bool variableJiapeng Zhong1-23/+23
Fix the following coccicheck warnings: ./drivers/mmc/host/atmel-mci.c:2436:2-34: WARNING: Assignment of 0/1 to bool variable. ./drivers/mmc/host/atmel-mci.c:2425:2-20: WARNING: Assignment of 0/1 to bool variable. Reported-by: Abaci Robot <[email protected]> Signed-off-by: Jiapeng Zhong <[email protected]> Acked-by: Ludovic Desroches <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-iproc: Add ACPI bindings for the RPiJeremy Linton1-0/+18
The RPi4 has an Arasan controller it carries over from the RPi3 and a newer eMMC2 controller. Because of a couple of quirks, it seems wiser to bind these controllers to the same driver that DT is using on this platform rather than the generic sdhci_acpi driver with PNP0D40. So, BCM2847 describes the older Arasan and BRCME88C describes the newer eMMC2. The older Arasan is reusing an existing ACPI _HID used by other OSes booting these tables on the RPi. With this change, Linux is capable of utilizing the SD card slot, and the Wi-Fi when booted with UEFI+ACPI on the RPi4. Signed-off-by: Jeremy Linton <[email protected]> Acked-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: test: clean up mmc_test_cleanup()Yue Hu1-19/+5
mmc_test_cleanup() has same body as __mmc_test_prepare() with write except the character to memset(). Signed-off-by: Yue Hu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: test: remove the shutdown functionYue Hu1-5/+0
Since it's doing nothing for shutdown behavior. And the callback will be checked firstly in mmc_bus_shutdown(). Signed-off-by: Yue Hu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: core: remove unused host parameter of mmc_sd_get_csd()Yue Hu3-4/+4
The host parameter is not used in the body of mmc_sd_get_csd(), so let's remove it. Update related code at the same time. Signed-off-by: Yue Hu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-aspeed: Add KUnit tests for phase calculationsAndrew Jeffery3-0/+116
Converting degrees of phase to logic delays is irritating to test on hardware, so lets exercise the function using KUnit. Signed-off-by: Andrew Jeffery <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-aspeed: Add AST2600 bus clock supportAndrew Jeffery1-4/+33
The AST2600 can achieve HS200 speeds with a change to the bus clock divisor behaviour. The divisor can also be more accurate with respect to the requested clock rate, but keep the one-hot behaviour for backwards compatibility with the AST2400 and AST2500. Signed-off-by: Andrew Jeffery <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-aspeed: Expose clock phase controlsAndrew Jeffery1-8/+208
The Aspeed SD/eMMC controllers expose configurable clock phase correction by inserting delays of up to 15 logic elements in length into the bus clock path. The hardware supports independent configuration for both bus directions on a per-slot basis. The timing delay per element encoded in the driver was experimentally determined by scope measurements. The phase controls for both slots are grouped together in a single register of the global register block of the SD/MMC controller(s), which drives the use of a locking scheme between the SDHCIs and the global register set. Signed-off-by: Andrew Jeffery <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: core: Add helper for parsing clock phase propertiesAndrew Jeffery1-0/+44
Drivers for MMC hosts that accept phase corrections can take advantage of the helper by embedding an instance of struct mmc_clk_phase_map in their private data and invoking mmc_of_parse_clk_phase() to extract phase parameters. It is the responsibility of the host driver to translate and apply the extracted values to hardware as required. Signed-off-by: Andrew Jeffery <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: omap_hsmmc: Simplify bool comparison and conversionYang Li1-9/+9
Fix the following coccicheck warning: ./drivers/mmc/host/omap_hsmmc.c:297:6-25: WARNING: Comparison of 0/1 to bool variable According to the context, vqmmc_enabled is more suitable for bool type. Reported-by: Abaci Robot<[email protected]> Signed-off-by: Yang Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: core: convert comma to semicolonZheng Yongjun1-4/+4
Replace a comma between expression statements by a semicolon. Signed-off-by: Zheng Yongjun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-pci-gli: Finetune HS400 RX delay for GL9763ERenius Chen1-0/+9
To improve the compatibility of GL9763E with HS400 eMMC cards, finetune the RX delay of HS400 mode. Signed-off-by: Renius Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-arasan: Use dev_err_probe() to avoid spamming logsMuhammad Husaini Zulkifli1-8/+6
Using dev_err_probe() can avoid spamming logs when probe is deferred. This function can also help to reduce code the size, uniform error handling and simplify the code. Signed-off-by: Muhammad Husaini Zulkifli <[email protected]> Acked-by: Adrian Hunter <[email protected]> Acked-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-arasan: Add structure device pointer in probe functionMuhammad Husaini Zulkifli1-17/+17
Add struct device *dev in probe func() so that it can widely use in probe to make code more readable. Signed-off-by: Muhammad Husaini Zulkifli <[email protected]> Acked-by: Adrian Hunter <[email protected]> Acked-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-arasan: Convert to use np instead of pdev->dev.of_nodeMuhammad Husaini Zulkifli1-5/+3
Use np pointer to simplify code and improve readability. Signed-off-by: Muhammad Husaini Zulkifli <[email protected]> Suggested-by: Andy Shevchenko <[email protected]> Acked-by: Adrian Hunter <[email protected]> Acked-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-arasan: use of_device_get_match_data()Muhammad Husaini Zulkifli1-3/+1
Use of_device_get_match_data() helper to get the match-data. Signed-off-by: Muhammad Husaini Zulkifli <[email protected]> Suggested-by: Andy Shevchenko <[email protected]> Acked-by: Adrian Hunter <[email protected]> Acked-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-pci-gli: Enlarge ASPM L1 entry delay of GL9763ERenius Chen1-0/+10
GL9763E enters ASPM L1 state after a very short idle in default, even during a burst of request. So the R/W performance of GL9763E is low with some platforms, which support ASPM mechanism, due to entering ASPM L1 state very frequently in R/W process. Set the L1 entry delay bits in vendor-specific register to 0x3FF to enlarge the idle period to 260us for improving the R/W performance of GL9763E. Signed-off-by: Renius Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: core: remove redundant card null check to mmc_can_sleep()Yue Hu1-1/+1
Note that only _mmc_suspend() will call mmc_can_sleep(). And card is checked before in mmc_can_poweroff_notify(). Signed-off-by: Yue Hu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: core: remove needless err = 0 in mmc_init_card()Yue Hu1-4/+0
Since they will always being in successful path to return 0 directly, no need to set err = 0. Signed-off-by: Yue Hu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci_am654: Add Support for TI's AM64 SoCFaiz Abbas1-0/+28
Add support for the controller present on the AM64x SoC. There are instances: sdhci0: 8bit bus width, max 400 MBps sdhci1: 4bit bus width, max 100 MBps Signed-off-by: Faiz Abbas <[email protected]> Signed-off-by: Vignesh Raghavendra <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Aswath Govindraju <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: rtsx: add delay before power onRicky Wu1-0/+2
To make sure voltage is below 0.5V before power on during a power cycle, add a delay of at least 100ms. The delays in the mmc core is not sufficient for the rtsx pci device. Signed-off-by: Ricky Wu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sunxi-mmc: Ensure host is suspended during system sleepSamuel Holland1-0/+2
If the device suspend process begins before the mmc host's autosuspend timeout, the host will continue running during system sleep. Avoid this by forcing runtime suspend during a global suspend transition. Signed-off-by: Samuel Holland <[email protected]> Acked-by: Maxime Ripard <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: xenon: add AP807 compatible stringMarcin Wojtas1-0/+1
This patch adds new compatible string to differentiate between the controllers versions included in the AP807 north bridge. Thanks to this change, the SoCs which use AP807 will not run unintentionally in the 'slow mode' with disabled UHS modes. Signed-off-by: Marcin Wojtas <[email protected]> Signed-off-by: Konstantin Porotchkin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-arasan: Change code style of mapping the syscon fieldMuhammad Husaini Zulkifli1-2/+2
Change code style of mapping the syscon in sdhci_arasan_update_support64b() for readability and consistency. Signed-off-by: Muhammad Husaini Zulkifli <[email protected]> Acked-by: Andy Shevchenko <[email protected]> Acked-by: Adrian Hunter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-arasan: Fixed kernel-doc format warningMuhammad Husaini Zulkifli1-6/+5
Commit 36c6aadaae86 ("mmc: sdhci-of-arasan: Add support for Intel Keem Bay") introduces syscon map sdhci_arasan_update_support64b(). Unfortunately, kernel-doc format script tool has not been run before and causing warning on the documentation style. Below is the output when running the kernel-doc script tool: drivers/mmc/host/sdhci-of-arasan.c:1388: warning: contents before sections Let's fix this by using standard conventions kernel-doc format. Fixes: 36c6aadaae86 ("mmc: sdhci-of-arasan: Add support for Intel Keem Bay") Signed-off-by: Muhammad Husaini Zulkifli <[email protected]> Acked-by: Andy Shevchenko <[email protected]> Acked-by: Adrian Hunter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-pci-gli: Add a switch to enable/disable CQHCI supportRenius Chen1-1/+3
Add a vendor-specific bit named GLI_9763E_MB_ERP_ON at the bit7 of register 888h to decide whether to enhance random R/W performance of GL9763E. CQHCI support will be enabled if and only if the bit is set and the GLI_9763E_MB_CMQ_OFF bit is not set. Signed-off-by: Renius Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: rtsx: Add MMC_CAP2_NO_SDIO flagRicky Wu1-1/+2
Added flag MMC_CAP2_NO_SDIO to mmc->caps2 Card Reader not support SDIO Signed-off-by: Ricky Wu <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: jz4740: remove unused struct component card_detect_irqH. Nikolaus Schaller1-1/+0
I have not found any user for this struct component. Signed-off-by: H. Nikolaus Schaller <[email protected]> Reviewed-by: Paul Cercueil <[email protected]> Link: https://lore.kernel.org/r/415ea1cb85eedc12f0c2f70da9a1ae3885bdd091.1608714110.git.hns@goldelico.com Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: renesas_sdhi: Add a condition of cmd/data timeout for retuneYoshihiro Shimoda3-5/+15
According to the datasheet, this controller needs retune when cmd or data timeout happens. So, add a condition into .check_retune(). Signed-off-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/1608708622-29668-3-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: tmio: Add data timeout error detectionMasaharu Hayakawa1-2/+4
Currently, busy timeout is not checked for data transfer command. But, if the temperature condition changes, the data cannot be acquired correctly and timeout may occur. Also, we could reproduce an issue by using mmc_test driver (e.g. "Correct xfer_size at write (start failure)"). Therefore, this adds timeout error check. Signed-off-by: Masaharu Hayakawa <[email protected]> [saito: rework commit message.] Signed-off-by: Takeshi Saito <[email protected]> [shimoda: rebase, add commit description] Signed-off-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Tested-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/1608708622-29668-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: meson-gx: check for scatterlist size alignment in block modeDmitry Lebed1-15/+22
Enable SGDMA support for SD_IO_RW_EXTENDED and add proper check for scatterlist size alignment in block mode. According to documentation, in SDIO block mode meson-gx DMA could only handle buffers with sizes that are multiples of SDIO block size. Some SDIO drivers like brcmfmac use scatterlist API, but do not enforce proper scatterlist buffer size alignemnt, this looks like a root cause of non-working CMD53. Some minor style fixes. Signed-off-by: Dmitry Lebed <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: mediatek: fix race condition between msdc_request_timeout and irqChaotian Jing1-8/+10
when get request SW timeout, if CMD/DAT xfer done irq coming right now, then there is race between the msdc_request_timeout work and irq handler, and the host->cmd and host->data may set to NULL in irq handler. also, current flow ensure that only one path can go to msdc_request_done(), so no need check the return value of cancel_delayed_work(). Signed-off-by: Chaotian Jing <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: renesas_internal_dmac: add pre_req and post_req supportYoshihiro Shimoda1-8/+83
Add pre_req and post_req support to improve performance. Inspired by a patch in the BSP by Masaharu Hayakawa. Signed-off-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Tested-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/1608114572-1892-3-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: renesas_sdhi_internal_dmac: Fix DMA buffer alignment from 8 to 128-bytesTakeshi Saito1-2/+2
According to the latest datasheet, the internal DMAC buffer alignment R-Car Gen3 SDHI HW should be 128-bytes. So, fix it. Signed-off-by: Takeshi Saito <[email protected]> [shimoda: revise commit description, rebase] Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Signed-off-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Tested-by: Wolfram Sang <[email protected]> Link: https://lore.kernel.org/r/1608114572-1892-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-msm: Actually set the actual clockDouglas Anderson1-19/+16
The MSM SDHCI driver always set the "actual_clock" field to 0. It had a comment about it not being needed because we weren't using the standard SDHCI divider mechanism and we'd just fallback to "host->clock". However, it's still better to provide the actual clock. Why? 1. It will make timeout calculations slightly better. On one system I have, the eMMC requets 200 MHz (for HS400-ES) but actually gets 192 MHz. These are close, but why not get the more accurate one. 2. If things are seriously off in the clock driver and it's missing rates or picking the wrong rate (maybe it's rounding up instead of down), this will make it much more obvious what's going on. NOTE: we have to be a little careful here because the "actual_clock" field shouldn't include the multiplier that sdhci-msm needs internally. Suggested-by: Adrian Hunter <[email protected]> Signed-off-by: Douglas Anderson <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Acked-by: Adrian Hunter <[email protected]> Reviewed-by: Veerabhadrarao Badiganti <[email protected]> Link: https://lore.kernel.org/r/20201214092048.v5.2.I7564620993acd4baa63fa0e3925ca879a86d3ee3@changeid Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-msm: Warn about overclocking SD/MMCDouglas Anderson1-2/+13
As talked about in commit 5e4b7e82d497 ("clk: qcom: gcc-sdm845: Use floor ops for sdcc clks"), most clocks handled by the Qualcomm clock drivers are rounded _up_ by default instead of down. We should make sure SD/MMC clocks are always rounded down in the clock drivers. Let's add a warning in the Qualcomm SDHCI driver to help catch the problem. This would have saved a bunch of time [1]. NOTE: this doesn't actually fix any problems, it just makes it obvious to devs that there is a problem and that should be an indication to fix the clock driver. [1] http://lore.kernel.org/r/20201210102234.1.I096779f219625148900fc984dd0084ed1ba87c7f@changeid Suggested-by: Stephen Boyd <[email protected]> Signed-off-by: Douglas Anderson <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Acked-by: Adrian Hunter <[email protected]> Link: https://lore.kernel.org/r/20201214092048.v5.1.Iec3430c7d3c2a29262695edef7b82a14aaa567e5@changeid Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sunxi: add support for A100 mmc controllerYangtao Li1-3/+25
This patch adds support for A100 MMC controller, which use word address for internal dma. Signed-off-by: Yangtao Li <[email protected]> Signed-off-by: Andre Przywara <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
2021-02-01mmc: sdhci-of-dwcmshc: set SDHCI_QUIRK2_PRESET_VALUE_BROKENJisheng Zhang1-0/+1
The SDHCI_PRESET_FOR_* registers are not set(all read as zeros), so set the quirk. Signed-off-by: Jisheng Zhang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ulf Hansson <[email protected]>
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