aboutsummaryrefslogtreecommitdiff
path: root/drivers/mmc
AgeCommit message (Collapse)AuthorFilesLines
2019-09-11mmc: sdhci: Fix incorrect switch to HS modeAl Cooper1-1/+3
When switching from any MMC speed mode that requires 1.8v (HS200, HS400 and HS400ES) to High Speed (HS) mode, the system ends up configured for SDR12 with a 50MHz clock which is an illegal mode. This happens because the SDHCI_CTRL_VDD_180 bit in the SDHCI_HOST_CONTROL2 register is left set and when this bit is set, the speed mode is controlled by the SDHCI_CTRL_UHS field in the SDHCI_HOST_CONTROL2 register. The SDHCI_CTRL_UHS field will end up being set to 0 (SDR12) by sdhci_set_uhs_signaling() because there is no UHS mode being set. The fix is to change sdhci_set_uhs_signaling() to set the SDHCI_CTRL_UHS field to SDR25 (which is the same as HS) for any switch to HS mode. This was found on a new eMMC controller that does strict checking of the speed mode and the corresponding clock rate. It caused the switch to HS400 mode to fail because part of the sequence to switch to HS400 requires a switch from HS200 to HS before going to HS400. Suggested-by: Adrian Hunter <[email protected]> Signed-off-by: Al Cooper <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Depend on CONFIG_OF_ADDRESSAndrew Jeffery1-1/+1
Resolves the following build error reported by the 0-day bot: ERROR: "of_platform_device_create" [drivers/mmc/host/sdhci-of-aspeed.ko] undefined! SPARC does not set CONFIG_OF_ADDRESS so the symbol is missing. Depend on CONFIG_OF_ADDRESS to ensure the driver is only built for supported configurations. Fixes: 2d28dbe042f4 ("mmc: sdhci-of-aspeed: Add support for the ASPEED SD controller") Reported-by: kbuild test robot <[email protected]> Signed-off-by: Andrew Jeffery <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLKAndrew Jeffery1-2/+18
Add a get_max_clock() handler to sdhci-of-aspeed to report f_max as the maximum clock rate if it is set. This enables artificial limitation of the bus speed via max-frequency in the devicetree for e.g. the AST2600 evaluation board where I was seeing errors at 200MHz. Signed-off-by: Andrew Jeffery <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()Andrew Jeffery1-3/+0
The early-exit didn't seem to matter on the AST2500, but on the AST2600 the SD clock genuinely may not be running on entry to aspeed_sdhci_set_clock(). Remove the early exit to ensure we always run sdhci_enable_clk(). Signed-off-by: Andrew Jeffery <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Drop redundant assignment to host->clockAndrew Jeffery1-4/+1
host->clock is already managed by sdhci_set_ios(). Suggested-by: Ulf Hansson <[email protected]> Signed-off-by: Andrew Jeffery <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mmc_spi: Convert to use for_each_sg()Andy Shevchenko1-1/+1
Use for_each_sg() macro instead of open coded variant. No functional change intended. Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhi: fill in actual_clockTamás Szűcs1-5/+8
Save set clock in mmc_host actual_clock enabling exporting it via debugfs. This will indicate the precise SD clock in I/O settings rather than only the sometimes misleading requested clock. Signed-off-by: Tamás Szűcs <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: use lower/upper_32_bits() macros for DMA addressesMasahiro Yamada1-14/+13
Currently, the DMA addresses are casted to (u64) for the upper 32bits to avoid "right shift count >= width of type" warning. <linux/kernel.h> provides macros to address this, and I like the macro names are self-documenting. I introduced a new helper, sdhci_set_adma_addr() to avoid the code duplication. Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-cadence: override spec versionMasahiro Yamada1-0/+2
The datasheet of the IP (sd4hc) says it is compiatible with SDHCI v4, but the spec version field in the version register is read as 2 (i.e. SDHCI_SPEC_300) based on the RTL provided by Cadence. Socionext did not fix it up when it integrated the IP into the SoCs. So, it is working as SDHCI v3. It is not a real problem because there is no difference in the program flow in sdhci.c between SDHCI_SPEC_300/400, but set the real version just in case. Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: constify references of parameters to __sdhci_read_caps()Masahiro Yamada2-3/+4
__sdhci_read_caps() does not modify *ver, *caps, or *caps1. Probably, the caller of this function will want to constifythe parameters passed in. Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mediatek: enable SDIO IRQ low level trigger functionyong mao1-0/+2
SDIO IRQ is not defaultly triggered by low level, but by falling edge. It needs to set related register to enable SDIO IRQ low level trigger function. Otherwise the SDIO IRQ may be lost in some specail condition. Signed-off-by: Yong Mao <[email protected]> Signed-off-by: Chaotian Jing <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: Export sdhci_abort_tuning function symbolBen Chuang2-1/+3
Export sdhci_abort_tuning() function symbols which are used by other SD Host controller driver modules. Signed-off-by: Ben Chuang <[email protected]> Co-developed-by: Michael K Johnson <[email protected]> Signed-off-by: Michael K Johnson <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: Add PLL Enable support to internal clock setupBen Chuang2-0/+24
The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. Signed-off-by: Ben Chuang <[email protected]> Co-developed-by: Michael K Johnson <[email protected]> Signed-off-by: Michael K Johnson <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: Change timeout of loop for checking internal clock stableBen Chuang1-2/+2
According to section 3.2.1 internal clock setup in SD Host Controller Simplified Specifications 4.20, the timeout of loop for checking internal clock stable is defined as 150ms. Signed-off-by: Ben Chuang <[email protected]> Co-developed-by: Michael K Johnson <[email protected]> Signed-off-by: Michael K Johnson <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-arasan: Add Support for Intel LGM eMMCRamuthevar Vadivel Muruganx1-0/+15
The current arasan sdhci PHY configuration isn't compatible with the PHY on Intel's LGM(Lightning Mountain) SoC devices. Therefore, add a new compatible, to adapt the Intel's LGM eMMC PHY with arasan-sdhc controller to configure the PHY. Signed-off-by: Ramuthevar Vadivel Muruganx <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Fix return value check in aspeed_sdc_probe()Wei Yongjun1-2/+2
In case of error, the function of_platform_device_create() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <[email protected]> Reviewed-by: Andrew Jeffery <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: bcm2835: Take SWIOTLB memory size limitation into accountStefan Wahren1-1/+1
Make sure the sdhost driver doesn't use requests bigger than SWIOTLB can handle. Signed-off-by: Stefan Wahren <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Add support for the ASPEED SD controllerAndrew Jeffery3-0/+345
Add a minimal driver for ASPEED's SD controller, which exposes two SDHCIs. The ASPEED design implements a common register set for the SDHCIs, and moves some of the standard configuration elements out to this common area (e.g. 8-bit mode, and card detect configuration which is not currently supported). The SD controller has a dedicated hardware interrupt that is shared between the slots. The common register set exposes information on which slot triggered the interrupt; early revisions of the patch introduced an irqchip for the register, but reality is it doesn't behave as an irqchip, and the result fits awkwardly into the irqchip APIs. Instead I've taken the simple approach of using the IRQ as a shared IRQ with some minor performance impact for the second slot. Ryan was the original author of the patch - I've taken his work and massaged it to drop the irqchip support and rework the devicetree integration. The driver has been smoke tested under qemu against a minimal SD controller model and lightly tested on an ast2500-evb. Signed-off-by: Ryan Chen <[email protected]> Signed-off-by: Andrew Jeffery <[email protected]> Acked-by: Adrian Hunter <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mediatek: support 24bits segment sizeChaotian Jing1-3/+13
MSDC IP which support 64G DRAM will support 24bits BDMA buffer length, so add support it. Signed-off-by: Chaotian Jing <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mediatek: fix controller busy when plug out SDChaotian Jing1-3/+5
when plug out SD card, may get data CRC error, the MMC core will issue CMD13 to get card status, then CMD13 timeout(due to card plug out) will trigger CMD19 tuning, first CMD19 timeout has not call msdc_reset_hw() and cause the next CMD19 gets controller busy. Signed-off-by: Chaotian Jing <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: renesas_sdhi_sys_dmac: Remove all R-Car Gen3 SoCsYoshihiro Shimoda1-36/+0
All R-Car Gen3 SoCs with any ES version cannot use this DMAC actually. So, this patch removes the compatibles of R-Car Gen3 SoCs from renesas_sdhi_sys_dmac_of_match. Since the previous code has an empty whitelist to prevent probing of R-Car Gen3 SoCs, no behavior changes. Signed-off-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Tested-by: Wolfram Sang <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: jz4740: Drop dependency on arch headerPaul Cercueil1-4/+0
We don't need to set the 'slave_id' anymore - that field is never read by the DMA driver. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: jz4740: Code cleanupPaul Cercueil1-7/+7
Fix wrong code indentation which made the code hard to read, and fix return with value in void function. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-cadence: use struct_size() helperGustavo A. R. Silva1-3/+2
One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct sdhci_cdns_priv { ... struct sdhci_cdns_phy_param phy_params[0]; }; Make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. So, replace the following form: sizeof(*priv) + sizeof(priv->phy_params[0]) * nr_phy_params with: struct_size(priv, phy_params, nr_phy_params) Also, notice that, in this case, variable priv_size is not necessary, hence it is removed. This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-esdhc: add erratum A011334 support in ls1028a 1.0 SoCYinbo Zhu1-0/+1
This patch is to add erratum A011334 support in ls1028a 1.0 SoC Signed-off-by: Yinbo Zhu <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: Remove dev_err() usage after platform_get_irq()Stephen Boyd10-19/+4
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Ulf Hansson <[email protected]> Cc: [email protected] Cc: Greg Kroah-Hartman <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-pci: Add another Id for Intel CMLAdrian Hunter2-0/+2
Add another PCI Id for Intel CML. Signed-off-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-s3c: Mark expected switch fall-throughGustavo A. R. Silva1-0/+1
Mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mmc/host/sdhci-s3c.c: In function 'sdhci_s3c_probe': drivers/mmc/host/sdhci-s3c.c:613:19: warning: this statement may fall through [-Wimplicit-fallthrough=] host->mmc->caps |= MMC_CAP_8_BIT_DATA; drivers/mmc/host/sdhci-s3c.c:614:2: note: here case 4: ^~~~ Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: atmel-mci: Mark expected switch fall-throughsGustavo A. R. Silva1-0/+4
Mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mmc/host/atmel-mci.c: In function 'atmci_get_cap': drivers/mmc/host/atmel-mci.c:2415:30: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.has_odd_clk_div = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2416:2: note: here case 0x400: ^~~~ drivers/mmc/host/atmel-mci.c:2422:28: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.has_highspeed = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2423:2: note: here case 0x200: ^~~~ drivers/mmc/host/atmel-mci.c:2426:40: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.need_notbusy_for_read_ops = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2427:2: note: here case 0x100: ^~~~ Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]> Reviewed-by: Kees Cook <[email protected]> Acked-by: Ludovic Desroches <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-pltfm: Use devm_platform_ioremap_resource() to simplify codeJisheng Zhang1-3/+1
devm_platform_ioremap_resource() wraps platform_get_resource() and devm_ioremap_resource() in a single helper, let's use that helper to simplify the code. Signed-off-by: Jisheng Zhang <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mmci: Clarify comments and some code for busy detectionUlf Hansson1-32/+37
The code dealing with busy detection is somewhat complicated. In a way to make it a bit clearer, let's try to clarify the comments in the code about it. Additionally, move the part for clearing the so called busy start IRQ, to the place where the IRQ is actually delivered. Ideally, this should make the code a bit more robust. Finally, to improve understanding of the code and the sequence of the busy detection, move the corresponding code around a bit in mmci_cmd_irq(). Signed-off-by: Ulf Hansson <[email protected]> Tested-by: Jean Nicolas GRAUX <[email protected]> Reviewed-by: Jean Nicolas GRAUX <[email protected]>
2019-09-11mmc: sdhci-pci: Use dev_get_drvdataChuhong Yuan1-8/+4
Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-iproc: Add support for emmc2 of the BCM2711Stefan Wahren1-0/+9
The additional emmc2 interface of the BCM2711 is an improved version of the old emmc controller, which is able to provide DDR50 mode on the Raspberry Pi 4. Except 32 bit only register access no other quirks are known yet. Signed-off-by: Stefan Wahren <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mxs: use devm_platform_ioremap_resource() to simplify codeAnson Huang1-3/+1
Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11Revert "mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host controller"Daniel Drake1-1/+1
This reverts commit 414126f9e5abf1973c661d24229543a9458fa8ce. This commit broke eMMC storage access on a new consumer MiniPC based on AMD SoC, which has eMMC connected to: 02:00.0 SD Host controller: O2 Micro, Inc. Device 8620 (rev 01) (prog-if 01) Subsystem: O2 Micro, Inc. Device 0002 During probe, several errors are seen including: mmc1: Got data interrupt 0x02000000 even though no data operation was in progress. mmc1: Timeout waiting for hardware interrupt. mmc1: error -110 whilst initialising MMC card Reverting this commit allows the eMMC storage to be detected & usable again. Signed-off-by: Daniel Drake <[email protected]> Fixes: 414126f9e5ab ("mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host controller") Cc: [email protected] # v5.1+ Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11Revert "mmc: bcm2835: Terminate timeout work synchronously"Stefan Wahren1-1/+1
The commit 37fefadee8bb ("mmc: bcm2835: Terminate timeout work synchronously") causes lockups in case of hardware timeouts due the timeout work also calling cancel_delayed_work_sync() on its own. So revert it. Fixes: 37fefadee8bb ("mmc: bcm2835: Terminate timeout work synchronously") Cc: [email protected] Signed-off-by: Stefan Wahren <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-03Revert "mmc: core: do not retry CMD6 in __mmc_switch()"Jan Kaisrlik1-1/+1
Turns out the commit 3a0681c7448b ("mmc: core: do not retry CMD6 in __mmc_switch()") breaks initialization of a Toshiba THGBMNG5 eMMC card, when using the meson-gx-mmc.c driver on a custom board based on Amlogic A113D. The CMD6 that switches the card into HS200 mode is then one that fails and according to the below printed messages from the log: [ 1.648951] mmc0: mmc_select_hs200 failed, error -84 [ 1.648988] mmc0: error -84 whilst initialising MMC card After some analyze, it turns out that adding a delay of ~5ms inside mmc_select_bus_width() but after mmc_compare_ext_csds() has been executed, also fixes the problem. Adding yet some more debug code, trying to figure out if potentially the card could be in a busy state, both by using CMD13 and ->card_busy() ops concluded that this was not the case. Therefore, let's simply revert the commit that dropped support for retrying of CMD6, as this also fixes the problem. Fixes: 3a0681c7448b ("mmc: core: do not retry CMD6 in __mmc_switch()") Cc: [email protected] Signed-off-by: Jan Kaisrlik <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-03mmc: queue: use bigger segments if DMA MAP layer can merge the segmentsYoshihiro Shimoda1-3/+32
When the max_segs of a mmc host is smaller than 512, the mmc subsystem tries to use 512 segments if DMA MAP layer can merge the segments, and then the mmc subsystem exposes such information to the block layer by using blk_queue_can_use_dma_map_merging(). Signed-off-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Ulf Hansson <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Christoph Hellwig <[email protected]>
2019-08-30mmc: sdhci-cadence: enable v4_mode to fix ADMA 64-bit addressingMasahiro Yamada1-0/+1
The IP datasheet says this controller is compatible with SD Host Specification Version v4.00. As it turned out, the ADMA of this IP does not work with 64-bit mode when it is in the Version 3.00 compatible mode; it understands the old 64-bit descriptor table (as defined in SDHCI v2), but the ADMA System Address Register (SDHCI_ADMA_ADDRESS) cannot point to the 64-bit address. I noticed this issue only after commit bd2e75633c80 ("dma-contiguous: use fallback alloc_pages for single pages"). Prior to that commit, dma_set_mask_and_coherent() returned the dma address that fits in 32-bit range, at least for the default arm64 configuration (arch/arm64/configs/defconfig). Now the host->adma_addr exceeds the 32-bit limit, causing the real problem for the Socionext SoCs. (As a side-note, I was also able to reproduce the issue for older kernels by turning off CONFIG_DMA_CMA.) Call sdhci_enable_v4_mode() to fix this. Cc: <[email protected]> # v4.20+ Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-08-30mmc: sdhci-sprd: clear the UHS-I modes read from registersChunyan Zhang1-1/+12
sprd's sd host controller supports SDR50/SDR104/DDR50 though, the UHS-I mode used by the specific card can be selected via devicetree only. Fixes: fb8bd90f83c4 ("mmc: sdhci-sprd: Add Spreadtrum's initial host controller") Signed-off-by: Chunyan Zhang <[email protected]> Signed-off-by: Chunyan Zhang <[email protected]> Reviewed-by: Baolin Wang <[email protected]> Tested-by: Baolin Wang <[email protected]> Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-08-30mms: sdhci-sprd: add SDHCI_QUIRK_BROKEN_CARD_DETECTIONChunyan Zhang1-1/+2
sprd's sd host controller doesn't support detection to card insert or remove. Fixes: fb8bd90f83c4 ("mmc: sdhci-sprd: Add Spreadtrum's initial host controller") Signed-off-by: Chunyan Zhang <[email protected]> Signed-off-by: Chunyan Zhang <[email protected]> Reviewed-by: Baolin Wang <[email protected]> Tested-by: Baolin Wang <[email protected]> Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-08-30mmc: sdhci-sprd: add SDHCI_QUIRK2_PRESET_VALUE_BROKENChunyan Zhang1-1/+2
The bit of PRESET_VAL_ENABLE in HOST_CONTROL2 register is reserved on sprd's sd host controller, set quirk2 to disable configuring this. Fixes: fb8bd90f83c4 ("mmc: sdhci-sprd: Add Spreadtrum's initial host controller") Signed-off-by: Chunyan Zhang <[email protected]> Signed-off-by: Chunyan Zhang <[email protected]> Reviewed-by: Baolin Wang <[email protected]> Tested-by: Baolin Wang <[email protected]> Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-08-30mmc: sdhci-sprd: add get_ro hook functionChunyan Zhang1-0/+6
sprd's sd host controller doesn't support write protect to sd card. Fixes: fb8bd90f83c4 ("mmc: sdhci-sprd: Add Spreadtrum's initial host controller") Signed-off-by: Chunyan Zhang <[email protected]> Signed-off-by: Chunyan Zhang <[email protected]> Reviewed-by: Baolin Wang <[email protected]> Tested-by: Baolin Wang <[email protected]> Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-08-30mmc: sdhci-sprd: fixed incorrect clock dividerChunyan Zhang1-3/+4
The register SDHCI_CLOCK_CONTROL should be cleared before config clock divider, otherwise the frequency configured maybe lower than we expected. Fixes: fb8bd90f83c4 ("mmc: sdhci-sprd: Add Spreadtrum's initial host controller") Signed-off-by: Chunyan Zhang <[email protected]> Signed-off-by: Chunyan Zhang <[email protected]> Reviewed-by: Baolin Wang <[email protected]> Tested-by: Baolin Wang <[email protected]> Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-08-30mmc: core: Fix init of SD cards reporting an invalid VDD rangeUlf Hansson1-0/+6
The OCR register defines the supported range of VDD voltages for SD cards. However, it has turned out that some SD cards reports an invalid voltage range, for example having bit7 set. When a host supports MMC_CAP2_FULL_PWR_CYCLE and some of the voltages from the invalid VDD range, this triggers the core to run a power cycle of the card to try to initialize it at the lowest common supported voltage. Obviously this fails, since the card can't support it. Let's fix this problem, by clearing invalid bits from the read OCR register for SD cards, before proceeding with the VDD voltage negotiation. Cc: [email protected] Reported-by: Philip Langdale <[email protected]> Signed-off-by: Ulf Hansson <[email protected]> Reviewed-by: Philip Langdale <[email protected]> Tested-by: Philip Langdale <[email protected]> Tested-by: Manuel Presnitz <[email protected]>
2019-08-22mmc: sdhci-of-at91: add quirk for broken HS200Eugen Hristev1-0/+3
HS200 is not implemented in the driver, but the controller claims it through caps. Remove it via a quirk, to make sure the mmc core do not try to enable HS200, as it causes the eMMC initialization to fail. Signed-off-by: Eugen Hristev <[email protected]> Acked-by: Ludovic Desroches <[email protected]> Acked-by: Adrian Hunter <[email protected]> Fixes: bb5f8ea4d514 ("mmc: sdhci-of-at91: introduce driver for the Atmel SDMMC") Cc: [email protected] # v4.4+ Signed-off-by: Ulf Hansson <[email protected]>
2019-08-21Revert "mmc: sdhci-tegra: drop ->get_ro() implementation"Dmitry Osipenko1-0/+14
The WRITE_PROTECT bit is always in a "protected mode" on Tegra and WP-GPIO state need to be used instead. In a case of the GPIO absence, write-enable should be assumed. External SD is writable once again as a result of this patch because the offending commit changed behaviour for the case of a missing WP-GPIO to fall back to WRITE_PROTECT bit-checking, which is incorrect for Tegra. Cc: [email protected] # v5.1+ Fixes: e8391453e27f ("mmc: sdhci-tegra: drop ->get_ro() implementation") Signed-off-by: Dmitry Osipenko <[email protected]> Acked-by: Thierry Reding <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-08-06mmc: cavium: Add the missing dma unmap when the dma has finished.Kevin Hao1-0/+1
This fixes the below calltrace when the CONFIG_DMA_API_DEBUG is enabled. DMA-API: thunderx_mmc 0000:01:01.4: cpu touching an active dma mapped cacheline [cln=0x000000002fdf9800] WARNING: CPU: 21 PID: 1 at kernel/dma/debug.c:596 debug_dma_assert_idle+0x1f8/0x270 Modules linked in: CPU: 21 PID: 1 Comm: init Not tainted 5.3.0-rc1-next-20190725-yocto-standard+ #64 Hardware name: Marvell OcteonTX CN96XX board (DT) pstate: 80400009 (Nzcv daif +PAN -UAO) pc : debug_dma_assert_idle+0x1f8/0x270 lr : debug_dma_assert_idle+0x1f8/0x270 sp : ffff0000113cfc10 x29: ffff0000113cfc10 x28: 0000ffff8c880000 x27: ffff800bc72a0000 x26: ffff000010ff8000 x25: ffff000010ff8940 x24: ffff000010ff8968 x23: 0000000000000000 x22: ffff000010e83700 x21: ffff000010ea2000 x20: ffff000010e835c8 x19: ffff800bc2c73300 x18: ffffffffffffffff x17: 0000000000000000 x16: 0000000000000000 x15: ffff000010e835c8 x14: 6d20616d64206576 x13: 69746361206e6120 x12: 676e696863756f74 x11: 20757063203a342e x10: 31303a31303a3030 x9 : 303020636d6d5f78 x8 : 3230303030303030 x7 : 00000000000002fd x6 : ffff000010fd57d0 x5 : 0000000000000000 x4 : ffff0000106c5210 x3 : 00000000ffffffff x2 : 0000800bee9c0000 x1 : 57d5843f4aa62800 x0 : 0000000000000000 Call trace: debug_dma_assert_idle+0x1f8/0x270 wp_page_copy+0xb0/0x688 do_wp_page+0xa8/0x5b8 __handle_mm_fault+0x600/0xd00 handle_mm_fault+0x118/0x1e8 do_page_fault+0x200/0x500 do_mem_abort+0x50/0xb0 el0_da+0x20/0x24 ---[ end trace a005534bd23e109f ]--- DMA-API: Mapped at: debug_dma_map_sg+0x94/0x350 cvm_mmc_request+0x3c4/0x988 __mmc_start_request+0x9c/0x1f8 mmc_start_request+0x7c/0xb0 mmc_blk_mq_issue_rq+0x5c4/0x7b8 Signed-off-by: Kevin Hao <[email protected]> Fixes: ba3869ff32e4 ("mmc: cavium: Add core MMC driver for Cavium SOCs") Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-08-06mmc: cavium: Set the correct dma max segment size for mmc_hostKevin Hao1-1/+2
We have set the mmc_host.max_seg_size to 8M, but the dma max segment size of PCI device is set to 64K by default in function pci_device_add(). The mmc_host.max_seg_size is used to set the max segment size of the blk queue. Then this mismatch will trigger a calltrace like below when a bigger than 64K segment request arrives at mmc dev. So we should consider the limitation of the cvm_mmc_host when setting the mmc_host.max_seg_size. DMA-API: thunderx_mmc 0000:01:01.4: mapping sg segment longer than device claims to support [len=131072] [max=65536] WARNING: CPU: 6 PID: 238 at kernel/dma/debug.c:1221 debug_dma_map_sg+0x2b8/0x350 Modules linked in: CPU: 6 PID: 238 Comm: kworker/6:1H Not tainted 5.3.0-rc1-next-20190724-yocto-standard+ #62 Hardware name: Marvell OcteonTX CN96XX board (DT) Workqueue: kblockd blk_mq_run_work_fn pstate: 80c00009 (Nzcv daif +PAN +UAO) pc : debug_dma_map_sg+0x2b8/0x350 lr : debug_dma_map_sg+0x2b8/0x350 sp : ffff00001770f9e0 x29: ffff00001770f9e0 x28: ffffffff00000000 x27: 00000000ffffffff x26: ffff800bc2c73180 x25: ffff000010e83700 x24: 0000000000000002 x23: 0000000000000001 x22: 0000000000000001 x21: 0000000000000000 x20: ffff800bc48ba0b0 x19: ffff800bc97e8c00 x18: ffffffffffffffff x17: 0000000000000000 x16: 0000000000000000 x15: ffff000010e835c8 x14: 6874207265676e6f x13: 6c20746e656d6765 x12: 7320677320676e69 x11: 7070616d203a342e x10: 31303a31303a3030 x9 : 303020636d6d5f78 x8 : 35363d78616d5b20 x7 : 00000000000002fd x6 : ffff000010fd57dc x5 : 0000000000000000 x4 : ffff0000106c61f0 x3 : 00000000ffffffff x2 : 0000800bee060000 x1 : 7010678df3041a00 x0 : 0000000000000000 Call trace: debug_dma_map_sg+0x2b8/0x350 cvm_mmc_request+0x3c4/0x988 __mmc_start_request+0x9c/0x1f8 mmc_start_request+0x7c/0xb0 mmc_blk_mq_issue_rq+0x5c4/0x7b8 mmc_mq_queue_rq+0x11c/0x278 blk_mq_dispatch_rq_list+0xb0/0x568 blk_mq_do_dispatch_sched+0x6c/0x108 blk_mq_sched_dispatch_requests+0x110/0x1b8 __blk_mq_run_hw_queue+0xb0/0x118 blk_mq_run_work_fn+0x28/0x38 process_one_work+0x210/0x490 worker_thread+0x48/0x458 kthread+0x130/0x138 ret_from_fork+0x10/0x1c Signed-off-by: Kevin Hao <[email protected]> Fixes: ba3869ff32e4 ("mmc: cavium: Add core MMC driver for Cavium SOCs") Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-08-06mmc: sdhci-sprd: Fix the incorrect soft reset operation when runtime resumingBaolin Wang10-12/+12
The SD host controller specification defines 3 types software reset: software reset for data line, software reset for command line and software reset for all. Software reset for all means this reset affects the entire Host controller except for the card detection circuit. In sdhci_runtime_resume_host() we always do a software "reset for all", which causes the Spreadtrum variant controller to work abnormally after resuming. To fix the problem, let's do a software reset for the data and the command part, rather than "for all". However, as sdhci_runtime_resume() is a common sdhci function and we don't want to change the behaviour for other variants, let's introduce a new in-parameter for it. This enables the caller to decide if a "reset for all" shall be done or not. Signed-off-by: Baolin Wang <[email protected]> Fixes: fb8bd90f83c4 ("mmc: sdhci-sprd: Add Spreadtrum's initial host controller") Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.