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2019-09-13mmc: tmio: Fixup runtime PM management during probeUlf Hansson2-1/+9
The tmio_mmc_host_probe() calls pm_runtime_set_active() to update the runtime PM status of the device, as to make it reflect the current status of the HW. This works fine for most cases, but unfortunate not for all. Especially, there is a generic problem when the device has a genpd attached and that genpd have the ->start|stop() callbacks assigned. More precisely, if the driver calls pm_runtime_set_active() during ->probe(), genpd does not get to invoke the ->start() callback for it, which means the HW isn't really fully powered on. Furthermore, in the next phase, when the device becomes runtime suspended, genpd will invoke the ->stop() callback for it, potentially leading to usage count imbalance problems, depending on what's implemented behind the callbacks of course. To fix this problem, convert to call pm_runtime_get_sync() from tmio_mmc_host_probe() rather than pm_runtime_set_active(). Additionally, to avoid bumping usage counters and unnecessary re-initializing the HW the first time the tmio driver's ->runtime_resume() callback is called, introduce a state flag to keeping track of this. Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]>
2019-09-13Revert "mmc: tmio: move runtime PM enablement to the driver implementations"Ulf Hansson4-23/+2
This reverts commit 7ff213193310ef8d0ee5f04f79d791210787ac2c. It turns out that the above commit introduces other problems. For example, calling pm_runtime_set_active() must not be done prior calling pm_runtime_enable() as that makes it fail. This leads to additional problems, such as clock enables being wrongly balanced. Rather than fixing the problem on top, let's start over by doing a revert. Fixes: 7ff213193310 ("mmc: tmio: move runtime PM enablement to the driver implementations") Signed-off-by: Ulf Hansson <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]>
2019-09-12mmc: renesas_sdhi_internal_dmac: Add MMC_CAP2_MERGE_CAPABLEYoshihiro Shimoda1-1/+1
Since this host controller can merge bigger segments if DMA API layer cam merge the segments, this patch adds the flag. Signed-off-by: Yoshihiro Shimoda <[email protected]> Acked-by: Ulf Hansson <[email protected]> Signed-off-by: Christoph Hellwig <[email protected]>
2019-09-11mmc: dw_mmc: hi3798cv200: make array degrees static const, makes object smallerColin Ian King1-1/+1
Don't populate the array degrees on the stack but instead make it static const. Makes the object code smaller by 46 bytes. Before: text data bss dec hex filename 5356 1560 0 6916 1b04 dw_mmc-hi3798cv200.o After: text data bss dec hex filename 5214 1656 0 6870 1ad6 dw_mmc-hi3798cv200.o (gcc version 9.2.1, amd64) Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: Convert to use sdio_irq_claimed()Ulf Hansson2-7/+1
Instead of keeping track of whether SDIO IRQs have been enabled via an internal sdhci status flag, avoid the open-coding and convert into using sdio_irq_claimed(). Reviewed-by: Matthias Kaehlcke <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: Drop redundant code for SDIO IRQsUlf Hansson3-25/+16
Nowadays sdhci prevents runtime suspend when SDIO IRQs are enabled. However, some variants such as sdhci-esdhc-imx's, tries to allow runtime suspend while having the SDIO IRQs enabled, but without supporting remote wakeups. This support is a bit questionable, especially if the host device have a PM domain attached that can be power gated, but more importantly, the code have also become redundant (which was not the case when it was introduced). Rather than keeping the redundant code around, let's drop it and leave this to be revisited later on. Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: Drop redundant check in sdhci_ack_sdio_irq()Ulf Hansson1-2/+1
The sdhci_ack_sdio_irq() is called only when SDIO IRQs are enabled. Therefore, let's drop the redundant check of the internal SDHCI_SDIO_IRQ_ENABLED flag and just re-enable the IRQs immediately. Reviewed-by: Matthias Kaehlcke <[email protected]> Signed-off-by: Ulf Hansson <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mtk-sd: Re-store SDIO IRQs mask at system resumeUlf Hansson1-0/+3
In cases when SDIO IRQs have been enabled, runtime suspend is prevented by the driver. However, this still means msdc_runtime_suspend|resume() gets called during system suspend/resume, via pm_runtime_force_suspend|resume(). This means during system suspend/resume, the register context of the mtk-sd device most likely loses its register context, even in cases when SDIO IRQs have been enabled. To re-enable the SDIO IRQs during system resume, the mtk-sd driver currently relies on the mmc core to re-enable the SDIO IRQs when it resumes the SDIO card, but this isn't the recommended solution. Instead, it's better to deal with this locally in the mtk-sd driver, so let's do that. Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: dw_mmc: Re-store SDIO IRQs mask at system resumeUlf Hansson1-0/+4
In cases when SDIO IRQs have been enabled, runtime suspend is prevented by the driver. However, this still means dw_mci_runtime_suspend|resume() gets called during system suspend/resume, via pm_runtime_force_suspend|resume(). This means during system suspend/resume, the register context of the dw_mmc device most likely loses its register context, even in cases when SDIO IRQs have been enabled. To re-enable the SDIO IRQs during system resume, the dw_mmc driver currently relies on the mmc core to re-enable the SDIO IRQs when it resumes the SDIO card, but this isn't the recommended solution. Instead, it's better to deal with this locally in the dw_mmc driver, so let's do that. Tested-by: Matthias Kaehlcke <[email protected]> Signed-off-by: Ulf Hansson <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11Merge branch 'fixes' into nextUlf Hansson2-2/+2
2019-09-11mmc: sdhci-pci-o2micro: Fix O2 Host data read/write DLL Lock phase shift issueShirley Her (SC)1-2/+122
Fix data read/write error in HS200 mode due to chip DLL lock phase shift Signed-off-by: Shirley Her <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-pci-o2micro: Move functions in preparation to fix DLL lock phase ↵Shirley Her (SC)1-93/+94
shift issue Move functions in preparation to fix DLL lock phase shift issue Signed-off-by: Shirley Her <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-pci-o2micro: Change O2 Host PLL and DLL register nameShirley Her (SC)1-8/+8
Change O2 Host PLL and DLL register name Signed-off-by: Shirley Her <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: Fix incorrect switch to HS modeAl Cooper1-1/+3
When switching from any MMC speed mode that requires 1.8v (HS200, HS400 and HS400ES) to High Speed (HS) mode, the system ends up configured for SDR12 with a 50MHz clock which is an illegal mode. This happens because the SDHCI_CTRL_VDD_180 bit in the SDHCI_HOST_CONTROL2 register is left set and when this bit is set, the speed mode is controlled by the SDHCI_CTRL_UHS field in the SDHCI_HOST_CONTROL2 register. The SDHCI_CTRL_UHS field will end up being set to 0 (SDR12) by sdhci_set_uhs_signaling() because there is no UHS mode being set. The fix is to change sdhci_set_uhs_signaling() to set the SDHCI_CTRL_UHS field to SDR25 (which is the same as HS) for any switch to HS mode. This was found on a new eMMC controller that does strict checking of the speed mode and the corresponding clock rate. It caused the switch to HS400 mode to fail because part of the sequence to switch to HS400 requires a switch from HS200 to HS before going to HS400. Suggested-by: Adrian Hunter <[email protected]> Signed-off-by: Al Cooper <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Depend on CONFIG_OF_ADDRESSAndrew Jeffery1-1/+1
Resolves the following build error reported by the 0-day bot: ERROR: "of_platform_device_create" [drivers/mmc/host/sdhci-of-aspeed.ko] undefined! SPARC does not set CONFIG_OF_ADDRESS so the symbol is missing. Depend on CONFIG_OF_ADDRESS to ensure the driver is only built for supported configurations. Fixes: 2d28dbe042f4 ("mmc: sdhci-of-aspeed: Add support for the ASPEED SD controller") Reported-by: kbuild test robot <[email protected]> Signed-off-by: Andrew Jeffery <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Allow max-frequency limitation of SDCLKAndrew Jeffery1-2/+18
Add a get_max_clock() handler to sdhci-of-aspeed to report f_max as the maximum clock rate if it is set. This enables artificial limitation of the bus speed via max-frequency in the devicetree for e.g. the AST2600 evaluation board where I was seeing errors at 200MHz. Signed-off-by: Andrew Jeffery <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Uphold clocks-on post-condition of set_clock()Andrew Jeffery1-3/+0
The early-exit didn't seem to matter on the AST2500, but on the AST2600 the SD clock genuinely may not be running on entry to aspeed_sdhci_set_clock(). Remove the early exit to ensure we always run sdhci_enable_clk(). Signed-off-by: Andrew Jeffery <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Drop redundant assignment to host->clockAndrew Jeffery1-4/+1
host->clock is already managed by sdhci_set_ios(). Suggested-by: Ulf Hansson <[email protected]> Signed-off-by: Andrew Jeffery <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mmc_spi: Convert to use for_each_sg()Andy Shevchenko1-1/+1
Use for_each_sg() macro instead of open coded variant. No functional change intended. Signed-off-by: Andy Shevchenko <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhi: fill in actual_clockTamás Szűcs1-5/+8
Save set clock in mmc_host actual_clock enabling exporting it via debugfs. This will indicate the precise SD clock in I/O settings rather than only the sometimes misleading requested clock. Signed-off-by: Tamás Szűcs <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: use lower/upper_32_bits() macros for DMA addressesMasahiro Yamada1-14/+13
Currently, the DMA addresses are casted to (u64) for the upper 32bits to avoid "right shift count >= width of type" warning. <linux/kernel.h> provides macros to address this, and I like the macro names are self-documenting. I introduced a new helper, sdhci_set_adma_addr() to avoid the code duplication. Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-cadence: override spec versionMasahiro Yamada1-0/+2
The datasheet of the IP (sd4hc) says it is compiatible with SDHCI v4, but the spec version field in the version register is read as 2 (i.e. SDHCI_SPEC_300) based on the RTL provided by Cadence. Socionext did not fix it up when it integrated the IP into the SoCs. So, it is working as SDHCI v3. It is not a real problem because there is no difference in the program flow in sdhci.c between SDHCI_SPEC_300/400, but set the real version just in case. Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: constify references of parameters to __sdhci_read_caps()Masahiro Yamada2-3/+4
__sdhci_read_caps() does not modify *ver, *caps, or *caps1. Probably, the caller of this function will want to constifythe parameters passed in. Signed-off-by: Masahiro Yamada <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mediatek: enable SDIO IRQ low level trigger functionyong mao1-0/+2
SDIO IRQ is not defaultly triggered by low level, but by falling edge. It needs to set related register to enable SDIO IRQ low level trigger function. Otherwise the SDIO IRQ may be lost in some specail condition. Signed-off-by: Yong Mao <[email protected]> Signed-off-by: Chaotian Jing <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: Export sdhci_abort_tuning function symbolBen Chuang2-1/+3
Export sdhci_abort_tuning() function symbols which are used by other SD Host controller driver modules. Signed-off-by: Ben Chuang <[email protected]> Co-developed-by: Michael K Johnson <[email protected]> Signed-off-by: Michael K Johnson <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: Add PLL Enable support to internal clock setupBen Chuang2-0/+24
The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. Signed-off-by: Ben Chuang <[email protected]> Co-developed-by: Michael K Johnson <[email protected]> Signed-off-by: Michael K Johnson <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci: Change timeout of loop for checking internal clock stableBen Chuang1-2/+2
According to section 3.2.1 internal clock setup in SD Host Controller Simplified Specifications 4.20, the timeout of loop for checking internal clock stable is defined as 150ms. Signed-off-by: Ben Chuang <[email protected]> Co-developed-by: Michael K Johnson <[email protected]> Signed-off-by: Michael K Johnson <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-arasan: Add Support for Intel LGM eMMCRamuthevar Vadivel Muruganx1-0/+15
The current arasan sdhci PHY configuration isn't compatible with the PHY on Intel's LGM(Lightning Mountain) SoC devices. Therefore, add a new compatible, to adapt the Intel's LGM eMMC PHY with arasan-sdhc controller to configure the PHY. Signed-off-by: Ramuthevar Vadivel Muruganx <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Fix return value check in aspeed_sdc_probe()Wei Yongjun1-2/+2
In case of error, the function of_platform_device_create() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Signed-off-by: Wei Yongjun <[email protected]> Reviewed-by: Andrew Jeffery <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: bcm2835: Take SWIOTLB memory size limitation into accountStefan Wahren1-1/+1
Make sure the sdhost driver doesn't use requests bigger than SWIOTLB can handle. Signed-off-by: Stefan Wahren <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-aspeed: Add support for the ASPEED SD controllerAndrew Jeffery3-0/+345
Add a minimal driver for ASPEED's SD controller, which exposes two SDHCIs. The ASPEED design implements a common register set for the SDHCIs, and moves some of the standard configuration elements out to this common area (e.g. 8-bit mode, and card detect configuration which is not currently supported). The SD controller has a dedicated hardware interrupt that is shared between the slots. The common register set exposes information on which slot triggered the interrupt; early revisions of the patch introduced an irqchip for the register, but reality is it doesn't behave as an irqchip, and the result fits awkwardly into the irqchip APIs. Instead I've taken the simple approach of using the IRQ as a shared IRQ with some minor performance impact for the second slot. Ryan was the original author of the patch - I've taken his work and massaged it to drop the irqchip support and rework the devicetree integration. The driver has been smoke tested under qemu against a minimal SD controller model and lightly tested on an ast2500-evb. Signed-off-by: Ryan Chen <[email protected]> Signed-off-by: Andrew Jeffery <[email protected]> Acked-by: Adrian Hunter <[email protected]> Reviewed-by: Joel Stanley <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mediatek: support 24bits segment sizeChaotian Jing1-3/+13
MSDC IP which support 64G DRAM will support 24bits BDMA buffer length, so add support it. Signed-off-by: Chaotian Jing <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mediatek: fix controller busy when plug out SDChaotian Jing1-3/+5
when plug out SD card, may get data CRC error, the MMC core will issue CMD13 to get card status, then CMD13 timeout(due to card plug out) will trigger CMD19 tuning, first CMD19 timeout has not call msdc_reset_hw() and cause the next CMD19 gets controller busy. Signed-off-by: Chaotian Jing <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: renesas_sdhi_sys_dmac: Remove all R-Car Gen3 SoCsYoshihiro Shimoda1-36/+0
All R-Car Gen3 SoCs with any ES version cannot use this DMAC actually. So, this patch removes the compatibles of R-Car Gen3 SoCs from renesas_sdhi_sys_dmac_of_match. Since the previous code has an empty whitelist to prevent probing of R-Car Gen3 SoCs, no behavior changes. Signed-off-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Tested-by: Wolfram Sang <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: jz4740: Drop dependency on arch headerPaul Cercueil1-4/+0
We don't need to set the 'slave_id' anymore - that field is never read by the DMA driver. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: jz4740: Code cleanupPaul Cercueil1-7/+7
Fix wrong code indentation which made the code hard to read, and fix return with value in void function. Signed-off-by: Paul Cercueil <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-cadence: use struct_size() helperGustavo A. R. Silva1-3/+2
One of the more common cases of allocation size calculations is finding the size of a structure that has a zero-sized array at the end, along with memory for some number of elements for that array. For example: struct sdhci_cdns_priv { ... struct sdhci_cdns_phy_param phy_params[0]; }; Make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. So, replace the following form: sizeof(*priv) + sizeof(priv->phy_params[0]) * nr_phy_params with: struct_size(priv, phy_params, nr_phy_params) Also, notice that, in this case, variable priv_size is not necessary, hence it is removed. This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-of-esdhc: add erratum A011334 support in ls1028a 1.0 SoCYinbo Zhu1-0/+1
This patch is to add erratum A011334 support in ls1028a 1.0 SoC Signed-off-by: Yinbo Zhu <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: Remove dev_err() usage after platform_get_irq()Stephen Boyd10-19/+4
We don't need dev_err() messages when platform_get_irq() fails now that platform_get_irq() prints an error message itself when something goes wrong. Let's remove these prints with a simple semantic patch. // <smpl> @@ expression ret; struct platform_device *E; @@ ret = ( platform_get_irq(E, ...) | platform_get_irq_byname(E, ...) ); if ( \( ret < 0 \| ret <= 0 \) ) { ( -if (ret != -EPROBE_DEFER) -{ ... -dev_err(...); -... } | ... -dev_err(...); ) ... } // </smpl> While we're here, remove braces on if statements that only have one statement (manually). Cc: Ulf Hansson <[email protected]> Cc: [email protected] Cc: Greg Kroah-Hartman <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-pci: Add another Id for Intel CMLAdrian Hunter2-0/+2
Add another PCI Id for Intel CML. Signed-off-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-s3c: Mark expected switch fall-throughGustavo A. R. Silva1-0/+1
Mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mmc/host/sdhci-s3c.c: In function 'sdhci_s3c_probe': drivers/mmc/host/sdhci-s3c.c:613:19: warning: this statement may fall through [-Wimplicit-fallthrough=] host->mmc->caps |= MMC_CAP_8_BIT_DATA; drivers/mmc/host/sdhci-s3c.c:614:2: note: here case 4: ^~~~ Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: atmel-mci: Mark expected switch fall-throughsGustavo A. R. Silva1-0/+4
Mark switch cases where we are expecting to fall through. This patch fixes the following warnings: drivers/mmc/host/atmel-mci.c: In function 'atmci_get_cap': drivers/mmc/host/atmel-mci.c:2415:30: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.has_odd_clk_div = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2416:2: note: here case 0x400: ^~~~ drivers/mmc/host/atmel-mci.c:2422:28: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.has_highspeed = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2423:2: note: here case 0x200: ^~~~ drivers/mmc/host/atmel-mci.c:2426:40: warning: this statement may fall through [-Wimplicit-fallthrough=] host->caps.need_notbusy_for_read_ops = 1; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~ drivers/mmc/host/atmel-mci.c:2427:2: note: here case 0x100: ^~~~ Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]> Reviewed-by: Kees Cook <[email protected]> Acked-by: Ludovic Desroches <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-pltfm: Use devm_platform_ioremap_resource() to simplify codeJisheng Zhang1-3/+1
devm_platform_ioremap_resource() wraps platform_get_resource() and devm_ioremap_resource() in a single helper, let's use that helper to simplify the code. Signed-off-by: Jisheng Zhang <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mmci: Clarify comments and some code for busy detectionUlf Hansson1-32/+37
The code dealing with busy detection is somewhat complicated. In a way to make it a bit clearer, let's try to clarify the comments in the code about it. Additionally, move the part for clearing the so called busy start IRQ, to the place where the IRQ is actually delivered. Ideally, this should make the code a bit more robust. Finally, to improve understanding of the code and the sequence of the busy detection, move the corresponding code around a bit in mmci_cmd_irq(). Signed-off-by: Ulf Hansson <[email protected]> Tested-by: Jean Nicolas GRAUX <[email protected]> Reviewed-by: Jean Nicolas GRAUX <[email protected]>
2019-09-11mmc: sdhci-pci: Use dev_get_drvdataChuhong Yuan1-8/+4
Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: sdhci-iproc: Add support for emmc2 of the BCM2711Stefan Wahren1-0/+9
The additional emmc2 interface of the BCM2711 is an improved version of the old emmc controller, which is able to provide DDR50 mode on the Raspberry Pi 4. Except 32 bit only register access no other quirks are known yet. Signed-off-by: Stefan Wahren <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11mmc: mxs: use devm_platform_ioremap_resource() to simplify codeAnson Huang1-3/+1
Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11Revert "mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host controller"Daniel Drake1-1/+1
This reverts commit 414126f9e5abf1973c661d24229543a9458fa8ce. This commit broke eMMC storage access on a new consumer MiniPC based on AMD SoC, which has eMMC connected to: 02:00.0 SD Host controller: O2 Micro, Inc. Device 8620 (rev 01) (prog-if 01) Subsystem: O2 Micro, Inc. Device 0002 During probe, several errors are seen including: mmc1: Got data interrupt 0x02000000 even though no data operation was in progress. mmc1: Timeout waiting for hardware interrupt. mmc1: error -110 whilst initialising MMC card Reverting this commit allows the eMMC storage to be detected & usable again. Signed-off-by: Daniel Drake <[email protected]> Fixes: 414126f9e5ab ("mmc: sdhci: Remove unneeded quirk2 flag of O2 SD host controller") Cc: [email protected] # v5.1+ Signed-off-by: Ulf Hansson <[email protected]>
2019-09-11Revert "mmc: bcm2835: Terminate timeout work synchronously"Stefan Wahren1-1/+1
The commit 37fefadee8bb ("mmc: bcm2835: Terminate timeout work synchronously") causes lockups in case of hardware timeouts due the timeout work also calling cancel_delayed_work_sync() on its own. So revert it. Fixes: 37fefadee8bb ("mmc: bcm2835: Terminate timeout work synchronously") Cc: [email protected] Signed-off-by: Stefan Wahren <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-08-30mmc: sdhci-cadence: enable v4_mode to fix ADMA 64-bit addressingMasahiro Yamada1-0/+1
The IP datasheet says this controller is compatible with SD Host Specification Version v4.00. As it turned out, the ADMA of this IP does not work with 64-bit mode when it is in the Version 3.00 compatible mode; it understands the old 64-bit descriptor table (as defined in SDHCI v2), but the ADMA System Address Register (SDHCI_ADMA_ADDRESS) cannot point to the 64-bit address. I noticed this issue only after commit bd2e75633c80 ("dma-contiguous: use fallback alloc_pages for single pages"). Prior to that commit, dma_set_mask_and_coherent() returned the dma address that fits in 32-bit range, at least for the default arm64 configuration (arch/arm64/configs/defconfig). Now the host->adma_addr exceeds the 32-bit limit, causing the real problem for the Socionext SoCs. (As a side-note, I was also able to reproduce the issue for older kernels by turning off CONFIG_DMA_CMA.) Call sdhci_enable_v4_mode() to fix this. Cc: <[email protected]> # v4.20+ Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
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