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2019-11-14Merge branch 'fixes' into nextUlf Hansson1-1/+1
2019-11-14mmc: moxart: Use dma_request_chan() directly for channel requestPeter Ujfalusi1-2/+2
dma_request_slave_channel_reason() is: dma_request_chan(dev, name) Signed-off-by: Peter Ujfalusi <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-14mmc: atmel-mci: Use dma_request_chan() directly for channel requestPeter Ujfalusi1-2/+1
dma_request_slave_channel_reason() is: dma_request_chan(dev, name) Signed-off-by: Peter Ujfalusi <[email protected]> Acked-by: Ludovic Desroches <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-14mmc: mmc_spi: Use proper debounce time for CD GPIOThierry Reding1-1/+1
According to the comment, board files used to specify 1 ms for the debounce time. gpiod_set_debounce() needs the debounce time to be specified in units of microseconds, so make sure to multiply the value by 1000. Note that, according to the git log, the board files actually did specify 1 us for bounce times, but that seems really low. Device tree bindings for this type of GPIO typically specify the debounce times in milliseconds, so setting this default value to 1 ms seems like it would be somewhat safer. Signed-off-by: Thierry Reding <[email protected]> Acked-by: Pavel Machek <[email protected]> Reviewed-by: Linus Walleij <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-14mmc: sdhci-of-at91: fix quirk2 overwriteEugen Hristev1-1/+1
The quirks2 are parsed and set (e.g. from DT) before the quirk for broken HS200 is set in the driver. The driver needs to enable just this flag, not rewrite the whole quirk set. Fixes: 7871aa60ae00 ("mmc: sdhci-of-at91: add quirk for broken HS200") Signed-off-by: Eugen Hristev <[email protected]> Acked-by: Adrian Hunter <[email protected]> Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: vub300: Drop redundant host ops ->init_card()Ulf Hansson1-7/+0
The ->init_card() host ops is printing message to the log, without actually doing something useful. Let's just drop this code. Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: renesas_sdhi_internal_dmac: Add r8a774b1 supportBiju Das1-0/+1
This patch adds SDHI support for RZ/G2N (R8A774B1) SoC. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: sdhci-of-esdhc: fix up erratum A-008171 workaroundYangbo Lu2-33/+203
A previous patch implemented an incomplete workaround of erratum A-008171. The complete workaround is as below. This patch is to implement the complete workaround which uses SW tuning if HW tuning fails, and retries both HW/SW tuning once with reduced clock if workaround fails. This is suggested by hardware team, and the patch had been verified on LS1046A eSDHC + Phison 32G eMMC which could trigger the erratum. Workaround: /* For T1040, T2080, LS1021A, T1023 Rev 1: */ 1. Program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO. 2. Program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO. 3. Program the software tuning mode by setting TBCTL[TB_MODE] = 2'h3. 4. Set SYSCTL2[EXTN] and SYSCTL2[SAMPCLKSEL]. 5. Issue SEND_TUNING_BLK Command (CMD19 for SD, CMD21 for MMC). 6. Wait for IRQSTAT[BRR], buffer read ready, to be set. 7. Clear IRQSTAT[BRR]. 8. Check SYSCTL2[EXTN] to be cleared. 9. Check SYSCTL2[SAMPCLKSEL], Sampling Clock Select. It's set value indicate tuning procedure success, and clear indicate failure. In case of tuning failure, fixed sampling scheme could be used by clearing TBCTL[TB_EN]. /* For LS1080A Rev 1, LS2088A Rev 1.0, LA1575A Rev 1.0: */ 1. Read the TBCTL[31:0] register. Write TBCTL[11:8]=4'h8 and wait for 1ms. 2. Read the TBCTL[31:0] register and rewrite again. Wait for 1ms second. 3. Read the TBSTAT[31:0] register twice. 3.1 Reset data lines by setting ESDHCCTL[RSTD] bit. 3.2 Check ESDHCCTL[RSTD] bit. 3.3 If ESDHCCTL[RSTD] is 0, go to step 3.4 else go to step 3.2. 3.4 Write 32'hFFFF_FFFF to IRQSTAT register. 4. if TBSTAT[15:8]-TBSTAT[7:0] > 4*DIV_RATIO or TBSTAT[7:0]-TBSTAT[15:8] > 4*DIV_RATIO , then program TBPTR[TB_WNDW_END_PTR] = 4*DIV_RATIO and program TBPTR[TB_WNDW_START_PTR] = 8*DIV_RATIO. /* For LS1012A Rev1, LS1043A Rev 1.x, LS1046A 1.0: */ 1. Read the TBCTL[0:31] register. Write TBCTL[20:23]=4'h8 and wait for 1ms. 2. Read the TBCTL[0:31] register and rewrite again. Wait for 1ms second. 3. Read the TBSTAT[0:31] register twice. 3.1 Reset data lines by setting ESDHCCTL[RSTD] bit. 3.2 Check ESDHCCTL[RSTD] bit. 3.3 If ESDHCCTL[RSTD] is 0, go to step 3.4 else go to step 3.2. 3.4 Write 32'hFFFF_FFFF to IRQSTAT register. 4. if TBSTAT[16:23]-TBSTAT[24:31] > 4*DIV_RATIO or TBSTAT[24:31]- TBSTAT[16:23] > 4* DIV_RATIO , then program TBPTR[TB_WNDW_END_PTR] = 4*DIV_RATIO and program TBPTR[TB_WNDW_START_PTR] = 8*DIV_RATIO. /* For LS1080A Rev 1, LS2088A Rev 1.0, LA1575A Rev 1.0 LS1012A Rev1, * LS1043A Rev 1.x, LS1046A 1.0: */ 5. else program TBPTR[TB_WNDW_END_PTR] = 3*DIV_RATIO and program TBPTR[TB_WNDW_START_PTR] = 5*DIV_RATIO. 6. Program the software tuning mode by setting TBCTL[TB_MODE] = 2'h3. 7. Set SYSCTL2[EXTN], wait 1us and SYSCTL2[SAMPCLKSEL]. 8. Issue SEND_TUNING_BLK Command (CMD19 for SD, CMD21 for MMC). 9. Wait for IRQSTAT[BRR], buffer read ready, to be set. 10. Clear IRQSTAT[BRR]. 11. Check SYSCTL2[EXTN] to be cleared. 12. Check SYSCTL2[SAMPCLKSEL], Sampling Clock Select. It's set value indicate tuning procedure success, and clear indicate failure. In case of tuning failure, fixed sampling scheme could be used by clearing TBCTL[TB_EN]. Fixes: b1f378ab5334 ("mmc: sdhci-of-esdhc: add erratum A008171 support") Signed-off-by: Yinbo Zhu <[email protected]> Signed-off-by: Yangbo Lu <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: sdhci-of-esdhc: poll ESDHC_FLUSH_ASYNC_FIFO bit until completionYangbo Lu1-7/+28
The ESDHC_FLUSH_ASYNC_FIFO bit which is set to flush asynchronous FIFO should be polled until it's auto cleared by hardware. Signed-off-by: Yangbo Lu <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: sdhci-of-at91: add DT property to enable calibration on full resetNicolas Ferre1-0/+19
Add a property to keep the analog calibration cell powered. This feature is specific to the Microchip SDHCI IP and outside of the standard SDHCI register map. By always keeping it on, after a full reset sequence, we make sure that this feature is activated and not disabled. We expose a hardware property to the DT as this feature can be used to adapt SDHCI behavior vs. how the SDCAL SoC pin is connected on the board. Note that managing properly this property would reduce power consumption on some SAMA5D2 SiP revisions. Signed-off-by: Nicolas Ferre <[email protected]> Acked-by: Ludovic Desroches <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: mmci: stm32: make sdmmc_idma_validate_data staticBen Dooks1-2/+2
Make sdmmc_idma_validate_data to avoid the following warning from sparse: drivers/mmc/host/mmci_stm32_sdmmc.c:28:5: warning: symbol 'sdmmc_idma_validate_data' was not declared. Should it be static? Signed-off-by: Ben Dooks <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: sdhci-pci: Add support for Intel JSLAdrian Hunter2-0/+4
Add PCI Ids for Intel JSL. Signed-off-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: jz4740: Add support for Low Power Mode (LPM)Zhou Yanjie1-0/+23
Add support for low power mode to the Ingenic's MMC/SD Controller. Signed-off-by: Zhou Yanjie <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: jz4740: Add support for X1000Zhou Yanjie1-1/+3
Add support for probing mmc driver on the X1000 Soc from Ingenic. Signed-off-by: Zhou Yanjie <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: jz4740: Add support for JZ4760Zhou Yanjie1-0/+2
Add support for probing mmc driver on the JZ4760 Soc from Ingenic. Signed-off-by: Zhou Yanjie <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: jz4740: Add 8bit mode supportZhou Yanjie1-2/+10
Add support for 8bit mode, now supports 1bit/4bit/8bit modes. Signed-off-by: Zhou Yanjie <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: sdhci-pci: Make function amd_sdhci_reset staticzhengbin1-1/+1
Fix sparse warnings: drivers/mmc/host/sdhci-pci-core.c:1599:6: warning: symbol 'amd_sdhci_reset' was not declared. Should it be static? Reported-by: Hulk Robot <[email protected]> Signed-off-by: zhengbin <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: sdhci-of-arasan: Add Support for Intel LGM SDXCRamuthevar Vadivel Murugan1-0/+15
The current arasan sdhci PHY configuration isn't compatible with the PHY on Intel's LGM(Lightning Mountain) SoC devices. Therefore, add a new compatible, to adapt the Intel's LGM SDXC PHY with arasan-sdhc controller to configure the PHY. Signed-off-by: Ramuthevar Vadivel Murugan <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: mmci: sdmmc: add busy_complete callbackLudovic Barre3-0/+47
This patch adds a specific busy_complete callback for sdmmc variant. sdmmc has 2 status flags: -busyd0: This is a hardware status flag (inverted value of d0 line). it does not generate an interrupt. -busyd0end: This indicates only end of busy following a CMD response. On busy to Not busy changes, an interrupt is generated (if unmask) and BUSYD0END status flag is set. Status flag is cleared by writing corresponding interrupt clear bit in MMCICLEAR. The legacy busy completion has no dedicated interrupt for the end of busy, so it's must monitor step by step the busy progression. On sdmmc variant, this procedure is not needed, it's just need to wait the busyd0end interrupt. Signed-off-by: Ludovic Barre <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: mmci: add busy_complete callbackLudovic Barre2-62/+73
This patch adds busy_completion callback at mmci_host_ops to allow to define a specific busy completion by variant. The legacy code corresponding to busy completion used by ux500 variants is moved to ux500_busy_complete function. Signed-off-by: Ludovic Barre <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: mmci: add hardware busy timeout featureLudovic Barre2-5/+40
In the stm32_sdmmc variant, the datatimer is active not only during data transfers with the DPSM, but also while waiting for the busyend IRQs from commands having the MMC_RSP_BUSY flag set. This leads to an incorrect IRQ being raised to signal MCI_DATATIMEOUT error, which simply breaks the behaviour. Address this by updating the datatimer value before sending a command having the MMC_RSP_BUSY flag set. To inform the mmc core about the maximum supported busy timeout, which also depends on the current clock rate, set ->max_busy_timeout (in ms). Signed-off-by: Ludovic Barre <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: mmci: make unexported functions staticBen Dooks1-10/+10
Fix the following sparse warnings by making any functions not used outsde the mmci.c driver static. drivers/mmc/host/mmci.c:422:6: warning: symbol 'mmci_dma_release' was not declared. Should it be static? drivers/mmc/host/mmci.c:430:6: warning: symbol 'mmci_dma_setup' was not declared. Should it be static? drivers/mmc/host/mmci.c:465:5: warning: symbol 'mmci_prep_data' was not declared. Should it be static? drivers/mmc/host/mmci.c:481:6: warning: symbol 'mmci_unprep_data' was not declared. Should it be static? drivers/mmc/host/mmci.c:490:6: warning: symbol 'mmci_get_next_data' was not declared. Should it be static? drivers/mmc/host/mmci.c:498:5: warning: symbol 'mmci_dma_start' was not declared. Should it be static? drivers/mmc/host/mmci.c:533:6: warning: symbol 'mmci_dma_finalize' was not declared. Should it be static? drivers/mmc/host/mmci.c:542:6: warning: symbol 'mmci_dma_error' was not declared. Should it be static? drivers/mmc/host/mmci.c:951:6: warning: symbol 'mmci_variant_init' was not declared. Should it be static? drivers/mmc/host/mmci.c:956:6: warning: symbol 'ux500v2_variant_init' was not declared. Should it be static? Signed-off-by: Ben Dooks <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: dw_mmc: fix indentation issueColin Ian King1-2/+2
There are a couple of statements that are indented by an extra space, clean this up by remove the extraneous spaces. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: cavium-octeon: Use devm_platform_ioremap_resource()Markus Elfring1-13/+2
Simplify this function implementation by using a known wrapper function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: bcm2835: Use devm_platform_ioremap_resource wrapperSaiyam Doshi1-3/+1
Use devm_platform_ioremap_resource helper which wraps platform_get_resource() and devm_ioremap_resource() together. Generated by: scripts/coccinelle/api/devm_platform_ioremap_resource.cocci. More information about semantic patching is available at http://coccinelle.lip6.fr/ Signed-off-by: Saiyam Doshi <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: tmio: remove workaround for NON_REMOVABLEWolfram Sang1-9/+0
PM has been reworked, so eMMC gets now detected on R-Car H3 ES1.0 and 2.0 as well as M3-N without the workaround. Card detect and write protect also still work. Remove the workaround. Signed-off-by: Wolfram Sang <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: Add Actions Semi Owl SoCs SD/MMC driverManivannan Sadhasivam3-0/+705
Add SD/MMC driver for Actions Semi Owl SoCs. This driver currently supports standard, high speed, SDR12, SDR25 and SDR50. DDR50 mode is supported but it is untested. There is no SDIO support for now. Signed-off-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: sdhci-milbeaut: add Milbeaut SD controller driverTakao Orito5-25/+407
SD Host controller on Milbeaut consists of two controller parts. One is core controller F_SDH30, this is similar to sdhci-fujitsu controller. Another is bridge controller. This bridge controller is not compatible with sdhci-fujitsu controller. This is special for Milbeaut series. This has some functions. For example, reset control, clock enable/select for SDR50/25/12, set property of SD physical pins, retuning control, set capabilityies. This bridge controller requires special procedures at reset or clock enablement or change for further tuning of clock. Signed-off-by: Takao Orito <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: sdhci-pci: Quirk for AMD SDHC Device 0x7906Raul E Rangel1-1/+50
AMD SDHC 0x7906 requires a hard reset to clear all internal state. Otherwise it can get into a bad state where the DATA lines are always read as zeros. This change requires firmware that can transition the device into D3Cold for it to work correctly. If the firmware does not support transitioning to D3Cold then the power state transitions are a no-op. Signed-off-by: Raul E Rangel <[email protected]> Signed-off-by: Shyam Sundar S K <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: sdhci: Check card status after resetRaul E Rangel1-0/+11
In sdhci_do_reset we call the reset callback which is typically sdhci_reset. sdhci_reset can wait for up to 100ms waiting for the controller to reset. If SDHCI_RESET_ALL was passed as the flag, the controller will clear the IRQ mask. If during that 100ms the card is removed there is no notification to the MMC system that the card was removed. So from the drivers point of view the card is always present. By making sdhci_reinit compare the present state it can schedule a rescan if the card was removed while a reset was in progress. Signed-off-by: Raul E Rangel <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-11-13mmc: tmio: Avoid boilerplate code in ->runtime_suspend()Ulf Hansson2-7/+4
Rather than checking the 'runtime_synced' flag each time the ->runtime_suspend() callback is invoked, let's convert into using dev_pm_domain_start() during ->probe() and drop the corresponding boilerplate code. Signed-off-by: Ulf Hansson <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
2019-11-03mmc: dw_mmc: Remove superfluous cast in debugfs_create_u32() callGeert Uytterhoeven1-1/+1
"dw_mci.state" is an enum, which is compatible with u32, so there is no need to cast its address, preventing further compiler checks. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-11-03mmc: dw_mmc: Fix debugfs on 64-bit platformsGeert Uytterhoeven1-4/+4
"dw_mci.pending_events" and "dw_mci.completed_events" are "unsigned long", i.e. 32-bit or 64-bit, depending on the platform. Hence casting their addresses to "u32 *", and calling debugfs_create_x32() breaks operation on 64-bit platforms. Fix this by using the new debugfs_create_xul() helper instead. Fixes: f95f3850f7a9e1d4 ("mmc: dw_mmc: Add Synopsys DesignWare mmc host driver.") Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-11-03mmc: atmel-mci: Remove superfluous cast in debugfs_create_u32() callGeert Uytterhoeven1-1/+1
"atmel_mci.state" is an enum, which is compatible with u32, so there is no need to cast its address, preventing further compiler checks. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-11-03mmc: atmel-mci: Fix debugfs on 64-bit platformsGeert Uytterhoeven1-4/+4
"atmel_mci.pending_events" and "atmel_mci.completed_events" are "unsigned long", i.e. 32-bit or 64-bit, depending on the platform. Hence casting their addresses to "u32 *", and calling debugfs_create_x32() breaks operation on 64-bit platforms. Fix this by using the new debugfs_create_xul() helper instead. Fixes: deec9ae31e607955 ("atmel-mci: debugfs support") Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Ulf Hansson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-10-21mmc: mxs: fix flags passed to dmaengine_prep_slave_sgSascha Hauer1-3/+4
Since ceeeb99cd821 we no longer abuse the DMA_CTRL_ACK flag for custom driver use and introduced the MXS_DMA_CTRL_WAIT4END instead. We have not changed all users to this flag though. This patch fixes it for the mxs-mmc driver. Fixes: ceeeb99cd821 ("dmaengine: mxs: rename custom flag") Signed-off-by: Sascha Hauer <[email protected]> Tested-by: Fabio Estevam <[email protected]> Reported-by: Bruno Thomsen <[email protected]> Tested-by: Bruno Thomsen <[email protected]> Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-10-21mmc: cqhci: Commit descriptors before setting the doorbellFaiz Abbas1-1/+2
Add a write memory barrier to make sure that descriptors are actually written to memory, before ringing the doorbell. Signed-off-by: Faiz Abbas <[email protected]> Acked-by: Adrian Hunter <[email protected]> Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-10-21mmc: sdhci-omap: Fix Tuning procedure for temperatures < -20CFaiz Abbas1-1/+1
According to the App note[1] detailing the tuning algorithm, for temperatures < -20C, the initial tuning value should be min(largest value in LPW - 24, ceil(13/16 ratio of LPW)). The largest value in LPW is (max_window + 4 * (max_len - 1)) and not (max_window + 4 * max_len) itself. Fix this implementation. [1] http://www.ti.com/lit/an/spraca9b/spraca9b.pdf Fixes: 961de0a856e3 ("mmc: sdhci-omap: Workaround errata regarding SDR104/HS200 tuning failures (i929)") Cc: [email protected] Signed-off-by: Faiz Abbas <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-10-15mmc: sdhci-acpi: Switch to use acpi_dev_hid_uid_match()Andy Shevchenko1-33/+16
Since we have a generic helper, drop custom implementation in the driver. Signed-off-by: Andy Shevchenko <[email protected]> Reviewed-by: Mika Westerberg <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
2019-10-09mmc: sdhci-iproc: fix spurious interrupts on Multiblock reads with bcm2711Nicolas Saenz Julienne1-0/+1
The Raspberry Pi 4 SDHCI hardware seems to automatically issue CMD12 after multiblock reads even when ACMD12 is disabled. This triggers spurious interrupts after the data transfer is done with the following message: mmc1: Got data interrupt 0x00000002 even though no data operation was in progress. mmc1: sdhci: ============ SDHCI REGISTER DUMP =========== mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00001002 mmc1: sdhci: Blk size: 0x00007200 | Blk cnt: 0x00000000 mmc1: sdhci: Argument: 0x00000000 | Trn mode: 0x00000033 mmc1: sdhci: Present: 0x1fff0000 | Host ctl: 0x00000017 mmc1: sdhci: Power: 0x0000000f | Blk gap: 0x00000080 mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x00000107 mmc1: sdhci: Timeout: 0x00000000 | Int stat: 0x00000000 mmc1: sdhci: Int enab: 0x03ff100b | Sig enab: 0x03ff100b mmc1: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00000000 mmc1: sdhci: Caps: 0x45ee6432 | Caps_1: 0x0000a525 mmc1: sdhci: Cmd: 0x00000c1a | Max curr: 0x00080008 mmc1: sdhci: Resp[0]: 0x00000b00 | Resp[1]: 0x00edc87f mmc1: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x00400e00 mmc1: sdhci: Host ctl2: 0x00000001 mmc1: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0xf3025208 mmc1: sdhci: ============================================ Enable SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 to enable ACMD12 on multiblock reads and suppress the spurious interrupts. Fixes: f84e411c85be ("mmc: sdhci-iproc: Add support for emmc2 of the BCM2711") Signed-off-by: Nicolas Saenz Julienne <[email protected]> Tested-by: Matthias Brugger <[email protected]> Acked-by: Stefan Wahren <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-10-03mmc: sh_mmcif: Use platform_get_irq_optional() for optional interruptGeert Uytterhoeven1-4/+2
As platform_get_irq() now prints an error when the interrupt does not exist, a scary warning may be printed for an optional interrupt: sh_mmcif ee200000.mmc: IRQ index 1 not found Fix this by calling platform_get_irq_optional() instead for the second interrupt, which is optional. Remove the now superfluous error printing for the first interrupt, which is mandatory. Fixes: 7723f4c5ecdb8d83 ("driver core: platform: Add an error message to platform_get_irq*()") Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Tested-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Tested-by: Wolfram Sang <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-10-03mmc: renesas_sdhi: Do not use platform_get_irq() to count interruptsGeert Uytterhoeven1-12/+19
As platform_get_irq() now prints an error when the interrupt does not exist, counting interrupts by looping until failure causes the printing of scary messages like: renesas_sdhi_internal_dmac ee140000.sd: IRQ index 1 not found Fix this by using the platform_irq_count() helper to avoid touching non-existent interrupts. Fixes: 7723f4c5ecdb8d83 ("driver core: platform: Add an error message to platform_get_irq*()") Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Yoshihiro Shimoda <[email protected]> Reviewed-by: Wolfram Sang <[email protected]> Tested-by: Yoshihiro Shimoda <[email protected]> Tested-by: Wolfram Sang <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-27mmc: host: sdhci-pci: Add Genesys Logic GL975x supportBen Chuang5-1/+361
Add support for the GL9750 and GL9755 chipsets. Enable v4 mode and wait 5ms after set 1.8V signal enable for GL9750/ GL9755. Fix the value of SDHCI_MAX_CURRENT register and use the vendor tuning flow for GL9750. Co-developed-by: Michael K Johnson <[email protected]> Signed-off-by: Michael K Johnson <[email protected]> Signed-off-by: Ben Chuang <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2019-09-27mmc: tegra: Implement ->set_dma_mask()Nicolin Chen1-20/+28
The SDHCI controller on Tegra186 supports 40-bit addressing, which is usually enough to address all of system memory. However, if the SDHCI controller is behind an IOMMU, the address space can go beyond. This happens on Tegra186 and later where the ARM SMMU has an input address space of 48 bits. If the DMA API is backed by this ARM SMMU, the top- down IOVA allocator will cause IOV addresses to be returned that the SDHCI controller cannot access. Unfortunately, prior to the introduction of the ->set_dma_mask() host operation, the SDHCI core would set either a 64-bit DMA mask if the controller claimed to support 64-bit addressing, or a 32-bit DMA mask otherwise. Since the full 64 bits cannot be addressed on Tegra, this had to be worked around in commit 68481a7e1c84 ("mmc: tegra: Mark 64 bit dma broken on Tegra186") by setting the SDHCI_QUIRK2_BROKEN_64_BIT_DMA quirk, which effectively restricts the DMA mask to 32 bits. One disadvantage of this is that dma_map_*() APIs will now try to use the swiotlb to bounce DMA to addresses beyond of the controller's DMA mask. This in turn caused degraded performance and can lead to situations where the swiotlb buffer is exhausted, which in turn leads to DMA transfers to fail. With the recent introduction of the ->set_dma_mask() host operation, this can now be properly fixed. For each generation of Tegra, the exact supported DMA mask can be configured. This kills two birds with one stone: it avoids the use of bounce buffers because system memory never exceeds the addressable memory range of the SDHCI controllers on these devices, and at the same time when an IOMMU is involved, it prevents IOV addresses from being allocated beyond the addressible range of the controllers. Since the DMA mask is now properly handled, the 64-bit DMA quirk can be removed. Signed-off-by: Nicolin Chen <[email protected]> [[email protected]: provide more background in commit message] Tested-by: Nicolin Chen <[email protected]> Acked-by: Adrian Hunter <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Cc: [email protected] # v4.15 + Signed-off-by: Ulf Hansson <[email protected]>
2019-09-27mmc: sdhci: Let drivers define their DMA maskAdrian Hunter2-8/+5
Add host operation ->set_dma_mask() so that drivers can define their own DMA masks. Signed-off-by: Adrian Hunter <[email protected]> Tested-by: Nicolin Chen <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Cc: [email protected] # v4.15 + Signed-off-by: Ulf Hansson <[email protected]>
2019-09-27mmc: sdhci-of-esdhc: set DMA snooping based on DMA coherenceRussell King1-1/+6
We must not unconditionally set the DMA snoop bit; if the DMA API is assuming that the device is not DMA coherent, and the device snoops the CPU caches, the device can see stale cache lines brought in by speculative prefetch. This leads to the device seeing stale data, potentially resulting in corrupted data transfers. Commonly, this results in a descriptor fetch error such as: mmc0: ADMA error mmc0: sdhci: ============ SDHCI REGISTER DUMP =========== mmc0: sdhci: Sys addr: 0x00000000 | Version: 0x00002202 mmc0: sdhci: Blk size: 0x00000008 | Blk cnt: 0x00000001 mmc0: sdhci: Argument: 0x00000000 | Trn mode: 0x00000013 mmc0: sdhci: Present: 0x01f50008 | Host ctl: 0x00000038 mmc0: sdhci: Power: 0x00000003 | Blk gap: 0x00000000 mmc0: sdhci: Wake-up: 0x00000000 | Clock: 0x000040d8 mmc0: sdhci: Timeout: 0x00000003 | Int stat: 0x00000001 mmc0: sdhci: Int enab: 0x037f108f | Sig enab: 0x037f108b mmc0: sdhci: ACmd stat: 0x00000000 | Slot int: 0x00002202 mmc0: sdhci: Caps: 0x35fa0000 | Caps_1: 0x0000af00 mmc0: sdhci: Cmd: 0x0000333a | Max curr: 0x00000000 mmc0: sdhci: Resp[0]: 0x00000920 | Resp[1]: 0x001d8a33 mmc0: sdhci: Resp[2]: 0x325b5900 | Resp[3]: 0x3f400e00 mmc0: sdhci: Host ctl2: 0x00000000 mmc0: sdhci: ADMA Err: 0x00000009 | ADMA Ptr: 0x000000236d43820c mmc0: sdhci: ============================================ mmc0: error -5 whilst initialising SD card but can lead to other errors, and potentially direct the SDHCI controller to read/write data to other memory locations (e.g. if a valid descriptor is visible to the device in a stale cache line.) Fix this by ensuring that the DMA snoop bit corresponds with the behaviour of the DMA API. Since the driver currently only supports DT, use of_dma_is_coherent(). Note that device_get_dma_attr() can not be used as that risks re-introducing this bug if/when the driver is converted to ACPI. Signed-off-by: Russell King <[email protected]> Acked-by: Adrian Hunter <[email protected]> Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-09-27mmc: sdhci: improve ADMA error reportingRussell King1-5/+10
ADMA errors are potentially data corrupting events; although we print the register state, we do not usefully print the ADMA descriptors. Worse than that, we print them by referencing their virtual address which is meaningless when the register state gives us the DMA address of the failing descriptor. Print the ADMA descriptors giving their DMA addresses rather than their virtual addresses, and print them using SDHCI_DUMP() rather than DBG(). We also do not show the correct value of the interrupt status register; the register dump shows the current value, after we have cleared the pending interrupts we are going to service. What is more useful is to print the interrupts that _were_ pending at the time the ADMA error was encountered. Fix that too. Signed-off-by: Russell King <[email protected]> Acked-by: Adrian Hunter <[email protected]> Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]>
2019-09-19Merge tag 'dma-mapping-5.4' of git://git.infradead.org/users/hch/dma-mappingLinus Torvalds1-1/+1
Pull dma-mapping updates from Christoph Hellwig: - add dma-mapping and block layer helpers to take care of IOMMU merging for mmc plus subsequent fixups (Yoshihiro Shimoda) - rework handling of the pgprot bits for remapping (me) - take care of the dma direct infrastructure for swiotlb-xen (me) - improve the dma noncoherent remapping infrastructure (me) - better defaults for ->mmap, ->get_sgtable and ->get_required_mask (me) - cleanup mmaping of coherent DMA allocations (me) - various misc cleanups (Andy Shevchenko, me) * tag 'dma-mapping-5.4' of git://git.infradead.org/users/hch/dma-mapping: (41 commits) mmc: renesas_sdhi_internal_dmac: Add MMC_CAP2_MERGE_CAPABLE mmc: queue: Fix bigger segments usage arm64: use asm-generic/dma-mapping.h swiotlb-xen: merge xen_unmap_single into xen_swiotlb_unmap_page swiotlb-xen: simplify cache maintainance swiotlb-xen: use the same foreign page check everywhere swiotlb-xen: remove xen_swiotlb_dma_mmap and xen_swiotlb_dma_get_sgtable xen: remove the exports for xen_{create,destroy}_contiguous_region xen/arm: remove xen_dma_ops xen/arm: simplify dma_cache_maint xen/arm: use dev_is_dma_coherent xen/arm: consolidate page-coherent.h xen/arm: use dma-noncoherent.h calls for xen-swiotlb cache maintainance arm: remove wrappers for the generic dma remap helpers dma-mapping: introduce a dma_common_find_pages helper dma-mapping: always use VM_DMA_COHERENT for generic DMA remap vmalloc: lift the arm flag for coherent mappings to common code dma-mapping: provide a better default ->get_required_mask dma-mapping: remove the dma_declare_coherent_memory export remoteproc: don't allow modular build ...
2019-09-13Merge branch 'fixes' into nextUlf Hansson5-27/+15
2019-09-13mmc: tmio: Fixup runtime PM management during removeUlf Hansson1-3/+4
Accessing the device when it may be runtime suspended is a bug, which is the case in tmio_mmc_host_remove(). Let's fix the behaviour. Cc: [email protected] Signed-off-by: Ulf Hansson <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]>
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