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2021-04-01memory: tegra20: Protect debug code with a lockDmitry Osipenko1-0/+7
Simultaneous accesses to MC_STAT h/w shouldn't be allowed since one collection process stomps on another. There is no good reason for polling stats in parallel in practice, nevertheless let's add a protection lock, just for consistency. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2021-04-01memory: tegra20: Correct comment to MC_STAT registers writesDmitry Osipenko1-3/+2
The code was changed multiple times and the comment to MC_STAT registers writes became slightly outdated. The MC_STAT programming now isn't hardcoded to the "bandwidth" mode, let's clarify this in the comment. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2021-04-01memory: tegra20: Add debug statisticsDmitry Osipenko3-2/+337
Add debug statistics collection support. The statistics is available via debugfs in '/sys/kernel/debug/mc/stats', it shows percent of memory controller utilization for each memory client. This information is intended to help with debugging of memory performance issues, it already was proven to be useful by helping to improve memory bandwidth management of the display driver. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2021-04-01memory: tegra: replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTEYang Li1-2/+2
Fix the following coccicheck warning: drivers/memory/tegra/tegra124-emc.c:1207:0-23: WARNING: tegra_emc_debug_min_rate_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE Signed-off-by: Yang Li <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2021-02-11Merge tag 'memory-controller-drv-5.12-2' of ↵Arnd Bergmann1-6/+6
git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers Memory controller drivers for v5.12, part two Two minor cleanups and one fix for compile testing (when !CONFIG_OF). * tag 'memory-controller-drv-5.12-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: memory: tegra186-emc: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE memory: samsung: exynos5422-dmc: Correct function names in kerneldoc memory: ti-emif-pm: Drop of_match_ptr from of_device_id table Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2021-02-08memory: tegra186-emc: Replace DEFINE_SIMPLE_ATTRIBUTE with ↵Jiapeng Chong1-6/+6
DEFINE_DEBUGFS_ATTRIBUTE Fix the following coccicheck warning: drivers/memory/tegra/tegra186-emc.c:158:0-23: WARNING: tegra186_emc_debug_max_rate_fops should be defined with DEFINE_DEBUGFS_ATTRIBUTE. Signed-off-by: Jiapeng Chong <[email protected]> Link: https://lore.kernel.org/r/1612684970-125948-1-git-send-email-jiapeng.chong@linux.alibaba.com Signed-off-by: Krzysztof Kozlowski <[email protected]>
2021-01-29memory: tegra: Remove calls to dev_pm_opp_set_clkname()Viresh Kumar3-33/+6
There is no point calling dev_pm_opp_set_clkname() with the "name" parameter set to NULL, this is already done by the OPP core at setup time and should work as it is. Signed-off-by: Viresh Kumar <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]> Tested-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/0f22cc1791d8b88c50a9790c2dc19455b34ec7b0.1611742564.git.viresh.kumar@linaro.org Signed-off-by: Krzysztof Kozlowski <[email protected]>
2021-01-23memory: tegra: Check whether reset is already assertedDmitry Osipenko1-0/+7
Check whether memory client reset is already asserted in order to prevent DMA-flush error on trying to re-assert an already asserted reset. This becomes a problem once PMC GENPD is enabled to use memory resets since GENPD will get a error and fail to toggle power domain. PMC GENPDs can't be toggled safely without holding memory reset on Tegra and we're about to fix this. Tested-by: Peter Geis <[email protected]> # Ouya T30 Tested-by: Nicolas Chauvet <[email protected]> # PAZ00 T20 Tested-by: Matt Merhar <[email protected]> # Ouya T30 Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2021-01-05memory: tegra124: Support interconnect frameworkDmitry Osipenko3-12/+391
Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. Tested-by: Nicolas Chauvet <[email protected]> Acked-by: Georgi Djakov <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2021-01-05memory: tegra124-emc: Continue probing if timings are missing in device-treeDmitry Osipenko1-17/+9
EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Tested-by: Nicolas Chauvet <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2021-01-05memory: tegra124-emc: Make driver modularDmitry Osipenko2-11/+23
Add modularization support to the Tegra124 EMC driver, which now can be compiled as a loadable kernel module. Note that EMC clock must be registered at clk-init time, otherwise PLLM will be disabled as unused clock at boot time if EMC driver is compiled as a module. Hence add a prepare/complete callbacks. similarly to what is done for the Tegra20/30 EMC drivers. Tested-by: Nicolas Chauvet <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-12-05memory: tegra30: Support interconnect frameworkDmitry Osipenko3-22/+496
Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. MC driver now supports tuning of memory arbitration latency, which needs to be done for ISO memory clients, like a Display client for example. Signed-off-by: Dmitry Osipenko <[email protected]> Tested-by: Peter Geis <[email protected]> Acked-by: Georgi Djakov <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-12-05memory: tegra20: Support hardware versioning and clean up OPP table ↵Dmitry Osipenko1-28/+20
initialization Support hardware versioning, which is now required for Tegra20 EMC OPP. Clean up OPP table initialization by using a error code returned by OPP API for judging about the OPP table presence in a device-tree and remove OPP regulator initialization because we're now going to use power domain instead of a raw regulator. This puts Tegra20 EMC OPP preparation on par with the Tegra30/124 EMC drivers. Signed-off-by: Dmitry Osipenko <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra30-emc: Remove unnecessary of_node_put in tegra_emc_probeNathan Chancellor1-3/+1
Clang warns: drivers/memory/tegra/tegra30-emc.c:1275:15: warning: variable 'np' is uninitialized when used here [-Wuninitialized] of_node_put(np); ^~ drivers/memory/tegra/tegra30-emc.c:1269:24: note: initialize the variable 'np' to silence this warning There does not need to be an of_node_put call in this error handling block after the shuffling of the np assignment. Remove it so there is no use of uninitialized memory. Fixes: 5e00fd90183a ("memory: tegra30-emc: Continue probing if timings are missing in device-tree") Signed-off-by: Nathan Chancellor <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra: Complete tegra210_swgroupsNicolin Chen1-0/+10
According to Tegra X1 TRM, there are missing swgroups in the tegra210_swgroups list. So this patch adds them to the list. Note that the TEGRA_SWGROUP_GPU (in list) should be actually TEGRA_SWGROUP_GPUB (in TRM), yet TEGRA_SWGROUP_GPU (in TRM) is not being used -- only TEGRA_SWGROUP_GPUB (in TRM) is. So this patch does not add TEGRA_SWGROUP_GPU (in TRM) and keeps TEGRA_SWGROUP_GPU (in list) as it is. Signed-off-by: Nicolin Chen <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra30-emc: Continue probing if timings are missing in device-treeDmitry Osipenko1-14/+15
EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra30-emc: Make driver modularDmitry Osipenko3-6/+16
Add modularization support to the Tegra30 EMC driver, which now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra30: Add FIFO sizes to memory clientsDmitry Osipenko1-0/+66
The latency allowness is calculated based on buffering capabilities of memory clients. Add FIFO sizes to the Tegra30 memory clients. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra20-emc: Add devfreq supportDmitry Osipenko2-1/+92
Add devfreq support to the Tegra20 EMC driver. Memory utilization statistics will be periodically polled from the memory controller and appropriate minimum clock rate will be selected by the devfreq governor. Signed-off-by: Dmitry Osipenko <[email protected]> Reviewed-by: Chanwoo Choi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra20-emc: Remove IRQ number from error messageDmitry Osipenko1-1/+1
Remove IRQ number from error message since it doesn't add any useful information, especially because this number is virtual. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra20-emc: Factor out clk initializationDmitry Osipenko1-23/+47
Factor out clk initialization and make it resource-managed. This makes easier to follow code and will help to make further changes cleaner. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra20-emc: Use dev_pm_opp_set_clkname()Dmitry Osipenko1-11/+19
The dev_pm_opp_get_opp_table() shouldn't be used by drivers, use dev_pm_opp_set_clkname() instead. Suggested-by: Viresh Kumar <[email protected]> Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra20: Support interconnect frameworkDmitry Osipenko3-4/+386
Now Internal and External Memory Controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra20-emc: Continue probing if timings are missing in device-treeDmitry Osipenko1-18/+16
EMC driver will become mandatory after turning it into interconnect provider because interconnect users, like display controller driver, will fail to probe using newer device-trees that have interconnect properties. Thus make EMC driver to probe even if timings are missing in device-tree. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra20-emc: Make driver modularDmitry Osipenko2-6/+13
Add modularization support to the Tegra20 EMC driver, which now can be compiled as a loadable kernel module. Signed-off-by: Dmitry Osipenko <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra-mc: Add interconnect frameworkDmitry Osipenko3-0/+123
Add common SoC-agnostic ICC framework which turns Tegra Memory Controller into a memory interconnection provider. This allows us to use interconnect API for tuning of memory configurations. Signed-off-by: Dmitry Osipenko <[email protected]> Tested-by: Peter Geis <[email protected]> Tested-by: Nicolas Chauvet <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra: Add missing latency allowness entry for Page Table CacheDmitry Osipenko3-0/+18
Add missing PTC memory client latency allowness entry to the Tegra MC drivers. This prevents erroneous clearing of MC_INTSTATUS 0x0 register during of the LA programming in tegra_mc_setup_latency_allowance() due to the missing entry. Note that this patch doesn't fix any known problems. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra: Remove superfluous error messages around platform_get_irq()Dmitry Osipenko3-7/+3
The platform_get_irq() prints error message telling that interrupt is missing, hence there is no need to duplicated that message in the drivers. Signed-off-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra: Use devm_platform_ioremap_resource()Dmitry Osipenko2-6/+2
Use devm_platform_ioremap_resource() helper which makes code a bit cleaner. Signed-off-by: Dmitry Osipenko <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-11-26memory: tegra: Add and use devm_tegra_memory_controller_get()Dmitry Osipenko4-59/+64
Multiple Tegra drivers need to retrieve Memory Controller and there is duplication of the retrieval code among the drivers. Add new devm_tegra_memory_controller_get() helper to remove the code's duplication and to fix put_device() which was missed in the duplicated code. Make EMC drivers to use the new helper. Signed-off-by: Dmitry Osipenko <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-10-27memory: tegra: Sort tegra210_swgroups by reg addressNicolin Chen1-10/+10
Cleanup the list of swgroups (ordering by register address) to prepare for new ones. Signed-off-by: Nicolin Chen <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-10-27memory: tegra: Correct tegra210_mc_clients def valuesNicolin Chen1-14/+14
Some def values are mismatched with Tegra X1 TRM, probably because being copied from tegra124.c file. Signed-off-by: Nicolin Chen <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-10-27memory: tegra: Correct la.reg address of seswrNicolin Chen1-1/+1
According to Tegra X1 TRM, ALLOWANCE_SESWR is located in field [23:16] of register at address 0x3e0 with a reset value of 0x80 at register 0x3e0, while bit-1 of register 0xb98 is for enable bit of seswr. Signed-off-by: Nicolin Chen <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-10-24Merge tag 'armsoc-drivers' of ↵Linus Torvalds5-25/+5
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms. A bulk of this is smaller fixes or cleanups, but some of the new material this time around is: - Support for Nvidia Tegra234 SoC - Ring accelerator support for TI AM65x - PRUSS driver for TI platforms - Renesas support for R-Car V3U SoC - Reset support for Cortex-M4 processor on i.MX8MQ There are also new socinfo entries for a handful of different SoCs and platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (131 commits) drm/mediatek: reduce clear event soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api soc: mediatek: cmdq: add jump function soc: mediatek: cmdq: add write_s_mask value function soc: mediatek: cmdq: add write_s value function soc: mediatek: cmdq: add read_s function soc: mediatek: cmdq: add write_s_mask function soc: mediatek: cmdq: add write_s function soc: mediatek: cmdq: add address shift in jump soc: mediatek: mtk-infracfg: Fix kerneldoc soc: amlogic: pm-domains: use always-on flag reset: sti: reset-syscfg: fix struct description warnings reset: imx7: add the cm4 reset for i.MX8MQ dt-bindings: reset: imx8mq: add m4 reset reset: Fix and extend kerneldoc reset: reset-zynqmp: Added support for Versal platform dt-bindings: reset: Updated binding for Versal reset driver reset: imx7: Support module build soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clk soc: fsl: qman: convert to use be32_add_cpu() ...
2020-09-20memory: tegra: Convert to DEFINE_SHOW_ATTRIBUTEQinglang Miao1-13/+1
Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code. Signed-off-by: Qinglang Miao <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-09-18memory: tegra: Correct num_tlb_lines for tegra210Nicolin Chen1-1/+1
According to Tegra210 TRM, the default value of TLB_ACTIVE_LINES field of register MC_SMMU_TLB_CONFIG_0 is 0x30. So num_tlb_lines should be 48 (0x30) rather than 32 (0x20). Signed-off-by: Nicolin Chen <[email protected]> Acked-by: Thierry Reding <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Joerg Roedel <[email protected]>
2020-09-09memory: tegra: Delete duplicated argument to '|' in function ↵Ye Bin1-1/+0
tegra210_emc_r21021_periodic_compensation In function tegra210_emc_r21021_periodic_compensation when calculate emc_cfg EMC_CFG_DRAM_CLKSTOP_PD is duplicated. Signed-off-by: Ye Bin <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-09-02memory: tegra: Remove GPU from DRM IOMMU groupThierry Reding1-1/+0
Commit 63a613fdb16c ("memory: tegra: Add gr2d and gr3d to DRM IOMMU group") added the GPU to the DRM IOMMU group, which doesn't make any sense. This causes problems when Nouveau tries to attach to the SMMU and causes it to fall back to using the DMA API. Remove the GPU from the DRM groups to restore the old behaviour. The GPU should always have its own IOMMU domain to make sure it can map buffers into contiguous chunks (for big page support) without getting in the way of mappings from the DRM group. Cc: <[email protected]> Fixes: 63a613fdb16c ("memory: tegra: Add gr2d and gr3d to DRM IOMMU group") Reported-by: Matias Zuniga <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Reviewed-by: Dmitry Osipenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-09-02memory: tegra186-emc: Simplify with dev_err_probe()Krzysztof Kozlowski1-8/+2
Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-08-20memory: tegra: Correct shift value of apewNicolin Chen1-1/+1
According to Tegra X1 (Tegra210) TRM, the APEW field is between [23:16] so the shift bit for apew should be 16 accordingly. Signed-off-by: Nicolin Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2020-08-17memory: tegra: tegra210-emc: fix indentationKrzysztof Kozlowski1-1/+1
Use tabs instead of spaces for indentation. Signed-off-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-07-15memory: tegra: Add Tegra132 compatible string matchThierry Reding1-0/+1
Ensure that the driver will bind against the Tegra132 instantiation of the external memory controller. While the two are roughly the same from a capability perspective, they do require some incompatible changes to the programming sequences and therefore need separate compatible strings. Signed-off-by: Thierry Reding <[email protected]>
2020-07-14memory: tegra: Fix KCONFIG variables for Tegra186 and Tegra194Jon Hunter1-2/+2
Commit a127e690b051 ("memory: tegra: Add support for the Tegra194 memory controller") and commit 4e04b88633ae ("memory: tegra: Only include support for enabled SoCs") incorrectly added the KCONFIG variables CONFIG_ARCH_TEGRA186_SOC and CONFIG_ARCH_TEGRA194_SOC to the Tegra EMC driver. These KCONFIG variables do not exist and prevent the EMC driver from being probed on Tegra186 and Tegra194. These KCONFIG variable names are simply missing one underscore and so fix this by adding the necessary underscore to the variable names. Signed-off-by: Jon Hunter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-06-22memory: tegra: Delete some dead codeDan Carpenter1-5/+0
The debugfs_create_dir() function never returns NULL and anyway the correct behavior is to ignore errors in this situation. The debugfs_create_file() will become a no-op if "emc->debugfs.root" is an error pointer. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-06-22memory: tegra: Avoid unused function warningsArnd Bergmann1-2/+2
The suspend/resume functions have no callers depending on configuration, so they must be marked __maybe_unused to avoid these harmless warnings: drivers/memory/tegra/tegra186.c:1578:12: error: 'tegra186_mc_resume' defined but not used [-Werror=unused-function] 1578 | static int tegra186_mc_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~ drivers/memory/tegra/tegra186.c:1573:12: error: 'tegra186_mc_suspend' defined but not used [-Werror=unused-function] 1573 | static int tegra186_mc_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~ Fixes: 177602b00641 ("memory: tegra: Add system sleep support") Signed-off-by: Arnd Bergmann <[email protected]> Acked-by: Thierry Reding <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-06-22memory: tegra: Drop <linux/clk-provider.h>Geert Uytterhoeven2-2/+0
The Tegra EMC scaling support code is not a clock provider, but merely a clock consumer, and thus does not need to include <linux/clk-provider.h>. Fixes: 0bf368c5b2cf ("memory: tegra: Add EMC scaling support code for Tegra210") Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-06-22memory: tegra: Fix an error handling path in tegra186_emc_probe()Christophe JAILLET1-5/+11
The call to tegra_bpmp_get() must be balanced by a call to tegra_bpmp_put() in case of error, as already done in the remove function. Add an error handling path and corresponding goto. Fixes: 52d15dd23f0b ("memory: tegra: Support DVFS on Tegra186 and later") Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-06-22memory: tegra30-emc: Poll EMC-CaR handshake instead of waiting for interruptDmitry Osipenko1-72/+44
The memory clock-rate change could be running on a non-boot CPU, while the boot CPU handles the EMC interrupt. This introduces an unnecessary latency since boot CPU should handle the interrupt and then notify the sibling CPU about clock-rate change completion. In some rare cases boot CPU could be in uninterruptible state for a significant time (like in a case of KASAN + NFS root), it could get to the point that completion timeouts before boot CPU gets a chance to handle interrupt. The solution is to get rid of the completion and replace it with interrupt-status polling. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-06-22memory: tegra20-emc: Poll EMC-CaR handshake instead of waiting for interruptDmitry Osipenko1-17/+11
The memory clock-rate change could be running on a non-boot CPU, while the boot CPU handles the EMC interrupt. This introduces an unnecessary latency since boot CPU should handle the interrupt and then notify the sibling CPU about clock-rate change completion. In some rare cases boot CPU could be in uninterruptible state for a significant time (like in a case of KASAN + NFS root), it could get to the point that completion timeouts before boot CPU gets a chance to handle interrupt. The solution is to get rid of the completion and replace it with interrupt-status polling. Signed-off-by: Dmitry Osipenko <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2020-06-22memory: tegra: Support derated timings on Tegra210Thierry Reding4-13/+363
Derated timings are used to ensure that the memory chips keep operating correctly at high temperatures. This adds code to support polling of the chip operating state when high temperatures are measured on the chip and change the refresh mode accordingly. Under very high temperatures, the driver will switch to the derated tables to ensure proper operation of the memory chips. Signed-off-by: Thierry Reding <[email protected]>
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