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2020-07-30irqchip/imx-intmux: Fix irqdata regs save in imx_intmux_runtime_suspend()Wei Yongjun1-6/+6
Gcc report warning as follows: drivers/irqchip/irq-imx-intmux.c:316:29: warning: variable 'irqchip_data' set but not used [-Wunused-but-set-variable] 316 | struct intmux_irqchip_data irqchip_data; | ^~~~~~~~~~~~ irqdata regs is stored to this variable on the stack in imx_intmux_runtime_suspend(), which means a nop. this commit fix to save regs to the right place. Fixes: bb403111e017 ("irqchip/imx-intmux: Implement intmux runtime power management") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200729155849.33919-1-weiyongjun1@huawei.com
2020-07-28bus: fsl-mc: Add ACPI support for fsl-mcMakarand Pawagi1-19/+73
Add ACPI support in the fsl-mc driver. Driver parses MC DSDT table to extract memory and other resources. Interrupt (GIC ITS) information is extracted from the MADT table by drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c. IORT table is parsed to configure DMA. Signed-off-by: Makarand Pawagi <makarand.pawagi@nxp.com> Signed-off-by: Diana Craciun <diana.craciun@oss.nxp.com> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com> Link: https://lore.kernel.org/r/20200619082013.13661-13-lorenzo.pieralisi@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-07-28bus/fsl-mc: Refactor the MSI domain creation in the DPRC driverDiana Craciun1-1/+14
The DPRC driver is not taking into account the msi-map property and assumes that the icid is the same as the stream ID. Although this assumption is correct, generalize the code to include a translation between icid and streamID. Furthermore do not just copy the MSI domain from parent (for child containers), but use the information provided by the msi-map property. If the msi-map property is missing from the device tree retain the old behaviour for backward compatibility ie the child DPRC objects inherit the MSI domain from the parent. Signed-off-by: Diana Craciun <diana.craciun@oss.nxp.com> Acked-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200619082013.13661-12-lorenzo.pieralisi@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2020-07-27genirq/affinity: Make affinity setting if activated opt-inThomas Gleixner1-1/+4
John reported that on a RK3288 system the perf per CPU interrupts are all affine to CPU0 and provided the analysis: "It looks like what happens is that because the interrupts are not per-CPU in the hardware, armpmu_request_irq() calls irq_force_affinity() while the interrupt is deactivated and then request_irq() with IRQF_PERCPU | IRQF_NOBALANCING. Now when irq_startup() runs with IRQ_STARTUP_NORMAL, it calls irq_setup_affinity() which returns early because IRQF_PERCPU and IRQF_NOBALANCING are set, leaving the interrupt on its original CPU." This was broken by the recent commit which blocked interrupt affinity setting in hardware before activation of the interrupt. While this works in general, it does not work for this particular case. As contrary to the initial analysis not all interrupt chip drivers implement an activate callback, the safe cure is to make the deferred interrupt affinity setting at activation time opt-in. Implement the necessary core logic and make the two irqchip implementations for which this is required opt-in. In hindsight this would have been the right thing to do, but ... Fixes: baedb87d1b53 ("genirq/affinity: Handle affinity setting on inactive interrupts correctly") Reported-by: John Keeping <john@metanate.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Tested-by: Marc Zyngier <maz@kernel.org> Acked-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Link: https://lkml.kernel.org/r/87blk4tzgm.fsf@nanos.tec.linutronix.de
2020-07-27irqchip/imx-intmux: Implement intmux runtime power managementJoakim Zhang1-2/+65
When the system is suspended, we can explicitly disable clock to save power. To achieve this, we need save registers' state since it could be lost after power off. Implement power management which will: - Turn the clock off after probing - Disable clock and save registers' state on system suspend, as well as enable clock and restore registers' state on resume - Rely on the Power Domain framework to shutdown the intmux power domain Without CONFIG_PM, the clock is always on after probe stage. Signed-off-by: Joakim Zhang <qiangqing.zhang@nxp.com> [maz: revamped commit message] Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200727141734.24890-2-qiangqing.zhang@nxp.com
2020-07-27irqchip/gic-v4.1: Use GFP_ATOMIC flag in allocate_vpe_l1_table()Zenghui Yu1-2/+2
Booting the latest kernel with DEBUG_ATOMIC_SLEEP=y on a GICv4.1 enabled box, I get the following kernel splat: [ 0.053766] BUG: sleeping function called from invalid context at mm/slab.h:567 [ 0.053767] in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/1 [ 0.053769] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 5.8.0-rc3+ #23 [ 0.053770] Call trace: [ 0.053774] dump_backtrace+0x0/0x218 [ 0.053775] show_stack+0x2c/0x38 [ 0.053777] dump_stack+0xc4/0x10c [ 0.053779] ___might_sleep+0xfc/0x140 [ 0.053780] __might_sleep+0x58/0x90 [ 0.053782] slab_pre_alloc_hook+0x7c/0x90 [ 0.053783] kmem_cache_alloc_trace+0x60/0x2f0 [ 0.053785] its_cpu_init+0x6f4/0xe40 [ 0.053786] gic_starting_cpu+0x24/0x38 [ 0.053788] cpuhp_invoke_callback+0xa0/0x710 [ 0.053789] notify_cpu_starting+0xcc/0xd8 [ 0.053790] secondary_start_kernel+0x148/0x200 # ./scripts/faddr2line vmlinux its_cpu_init+0x6f4/0xe40 its_cpu_init+0x6f4/0xe40: allocate_vpe_l1_table at drivers/irqchip/irq-gic-v3-its.c:2818 (inlined by) its_cpu_init_lpis at drivers/irqchip/irq-gic-v3-its.c:3138 (inlined by) its_cpu_init at drivers/irqchip/irq-gic-v3-its.c:5166 It turned out that we're allocating memory using GFP_KERNEL (may sleep) within the CPU hotplug notifier, which is indeed an atomic context. Bad thing may happen if we're playing on a system with more than a single CommonLPIAff group. Avoid it by turning this into an atomic allocation. Fixes: 5e5168461c22 ("irqchip/gic-v4.1: VPE table (aka GICR_VPROPBASER) allocation") Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200630133746.816-1-yuzenghui@huawei.com
2020-07-27irqchip/stm32-exti: Map direct event to irq parentAlexandre Torgue1-34/+67
EXTI lines are mainly used to wake-up system from CStop low power mode. Currently, if a device wants to use a EXTI (direct) line as wakeup line, it has to declare 2 interrupts: - one for EXTI used to wake-up system (with dedicated_wake_irq api). - one for GIC used to get the wake up reason inside the concerned IP. This split is not really needed as each EXTI line is actually "linked " to a GIC. So to avoid this useless double interrupt management in each wake-up driver, this patch lets the STM32 EXTI driver abstract it by mapping each EXTI line to his corresponding GIC. Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200717140717.29606-1-alexandre.torgue@st.com
2020-07-27irqchip/mtk-cirq: Convert to a platform driverSaravana Kannan1-1/+3
This driver can work as a platform driver. So covert it to a platform driver. Signed-off-by: Saravana Kannan <saravanak@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Hanks Chen <hanks.chen@mediatek.com> Link: https://lore.kernel.org/r/20200718000637.3632841-5-saravanak@google.com
2020-07-27irqchip/mtk-sysirq: Convert to a platform driverSaravana Kannan1-1/+3
This driver can work as a platform driver. So covert it to a platform driver. Signed-off-by: Saravana Kannan <saravanak@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Hanks Chen <hanks.chen@mediatek.com> Link: https://lore.kernel.org/r/20200718000637.3632841-4-saravanak@google.com
2020-07-27irqchip/qcom-pdc: Switch to using IRQCHIP_PLATFORM_DRIVER helper macrosSaravana Kannan1-23/+3
Switch the driver to use the helper macros. In addition to reducing the number of lines, this also adds module unload protection (if the driver is compiled as a module) by switching from module_platform_driver to builtin_platform_driver. Signed-off-by: Saravana Kannan <saravanak@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200718000637.3632841-3-saravanak@google.com
2020-07-27irqchip: Add IRQCHIP_PLATFORM_DRIVER_BEGIN/END and IRQCHIP_MATCH helper macrosSaravana Kannan1-0/+29
Compiling an irqchip driver as a platform driver needs to bunch of things to be done right: - Making sure the parent domain is initialized first - Making sure the device can't be unbound from sysfs - Disallowing module unload if it's built as a module - Finding the parent node - Etc. Instead of trying to make sure all future irqchip platform drivers get this right, provide boilerplate macros that take care of all of this. An example use would look something like this. Where acme_foo_init and acme_bar_init are similar to what would be passed to IRQCHIP_DECLARE. IRQCHIP_PLATFORM_DRIVER_BEGIN(acme_irq) IRQCHIP_MATCH("acme,foo", acme_foo_init) IRQCHIP_MATCH("acme,bar", acme_bar_init) IRQCHIP_PLATFORM_DRIVER_END(acme_irq) Signed-off-by: Saravana Kannan <saravanak@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: John Stultz <john.stultz@linaro.org> Link: https://lore.kernel.org/r/20200718000637.3632841-2-saravanak@google.com
2020-07-27irqchip/gic-v4.1: Ensure accessing the correct RD when writing INVALLRZenghui Yu1-3/+7
The GICv4.1 spec tells us that it's CONSTRAINED UNPREDICTABLE to issue a register-based invalidation operation for a vPEID not mapped to that RD, or another RD within the same CommonLPIAff group. To follow this rule, commit f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access") tried to address the race between the RD accesses and the vPE affinity change, but somehow forgot to take GICR_INVALLR into account. Let's take the vpe_lock before evaluating vpe->col_idx to fix it. Fixes: f3a059219bc7 ("irqchip/gic-v4.1: Ensure mutual exclusion between vPE affinity change and RD access") Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Cc: stable@vger.kernel.org Link: https://lore.kernel.org/r/20200720092328.708-1-yuzenghui@huawei.com
2020-07-27irqchip/irq-bcm7038-l1: Guard uses of cpu_logical_mapFlorian Fainelli1-0/+8
cpu_logical_map is only defined for CONFIG_SMP builds, when we are in an UP configuration, the boot CPU is 0. Fixes: 6468fc18b006 ("irqchip/irq-bcm7038-l1: Add PM support") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200724184157.29150-1-f.fainelli@gmail.com
2020-07-27irqchip/qcom-pdc: Allow QCOM_PDC to be loadable as a permanent moduleJohn Stultz2-2/+28
Allows qcom-pdc driver to be loaded as a permanent module Also, due to the fact that IRQCHIP_DECLARE becomes a no-op when building as a module, we have to replace it with platform driver hooks explicitly. Thanks to Saravana for his help on pointing out the IRQCHIP_DECLARE issue and guidance on a solution. Signed-off-by: John Stultz <john.stultz@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Cc: Andy Gross <agross@kernel.org> Cc: Bjorn Andersson <bjorn.andersson@linaro.org> Cc: Joerg Roedel <joro@8bytes.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <maz@kernel.org> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Maulik Shah <mkshah@codeaurora.org> Cc: Lina Iyer <ilina@codeaurora.org> Cc: Saravana Kannan <saravanak@google.com> Cc: Todd Kjos <tkjos@google.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: linux-arm-msm@vger.kernel.org Cc: iommu@lists.linux-foundation.org Cc: linux-gpio@vger.kernel.org Link: https://lore.kernel.org/r/20200710231824.60699-4-john.stultz@linaro.org
2020-07-27irqchip/mips-gic: Make local symbols staticWei Yongjun1-5/+5
The sparse tool complains as follows: drivers/irqchip/irq-mips-gic.c:49:1: warning: symbol '__pcpu_scope_pcpu_masks' was not declared. Should it be static? drivers/irqchip/irq-mips-gic.c:620:6: warning: symbol 'gic_ipi_domain_free' was not declared. Should it be static? drivers/irqchip/irq-mips-gic.c:634:5: warning: symbol 'gic_ipi_domain_match' was not declared. Should it be static? Those symbols are not used outside of irq-mips-gic.c, so marks them static. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200714142245.16124-1-weiyongjun1@huawei.com
2020-07-27irqchip/ativic32: Constify irq_domain_opsMasahiro Yamada1-1/+1
This is passed to irq_domain_add_linear(), which accepts a pointer to a const structure. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200714173857.477422-1-masahiroy@kernel.org
2020-07-27irqchip/stm32-exti: Use the hwspin_lock_timeout_in_atomic() APIFabien Dessenne1-45/+20
Now that the hwspin_lock_timeout_in_atomic() API is available use it. Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200706081115.25180-1-alexandre.torgue@st.com
2020-07-24firmware: ti_sci: Replace HTTP links with HTTPS onesAlexander A. Klimov2-2/+2
Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
2020-07-17irqchip/loongson-liointc: Fix potential dead lockTiezhu Yang1-0/+1
In the function liointc_set_type(), we need to call the function irq_gc_unlock_irqrestore() before returning. Fixes: dbb152267908 ("irqchip: Add driver for Loongson I/O Local Interrupt Controller") Reported-by: Jianmin Lv <lvjianmin@loongson.cn> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1594087972-21715-8-git-send-email-yangtiezhu@loongson.cn
2020-07-17irqchip/loongson-pch-msi: Remove unneeded variableTiezhu Yang1-6/+1
irq_domain_alloc_irqs_parent() returns 0 on success and non-zero value on failure, it is redudant to check its non-zero return value and then return it, so just remove the variable "ret" and return directly in the function pch_msi_parent_domain_alloc(). Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1594087972-21715-7-git-send-email-yangtiezhu@loongson.cn
2020-07-17irqchip/loongson-pch-pic: Check return value of irq_domain_translate_twocell()Tiezhu Yang1-6/+9
Check the return value of irq_domain_translate_twocell() due to it may returns -EINVAL if failed and use variable fwspec for it, and then use a new variable parent_fwspec which is proper for irq_domain_alloc_irqs_parent(). Fixes: ef8c01eb64ca ("irqchip: Add Loongson PCH PIC controller") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1594087972-21715-6-git-send-email-yangtiezhu@loongson.cn
2020-07-17irqchip/loongson-htvec: Check return value of irq_domain_translate_onecell()Tiezhu Yang1-1/+4
Check the return value of irq_domain_translate_onecell() due to it may returns -EINVAL if failed. Fixes: 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1594087972-21715-5-git-send-email-yangtiezhu@loongson.cn
2020-07-17irqchip/loongson-htvec: Fix potential resource leakTiezhu Yang1-1/+4
In the function htvec_of_init(), system resource "parent_irq" was not released in an error case. Thus add a jump target for the completion of the desired exception handling. Fixes: 818e915fbac5 ("irqchip: Add Loongson HyperTransport Vector support") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1594087972-21715-4-git-send-email-yangtiezhu@loongson.cn
2020-07-17irqchip/loongson-htpic: Remove unneeded select of I8259Tiezhu Yang1-1/+0
LOONGSON_HTPIC depends on MACH_LOONGSON64 and MACH_LOONGSON64 already selects I8259 in arch/mips/Kconfig, so no need to select I8259 again when config LOONGSON_HTPIC. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1594087972-21715-3-git-send-email-yangtiezhu@loongson.cn
2020-07-17irqchip/loongson-htpic: Remove redundant kfree operationTiezhu Yang1-4/+2
In the function htpic_of_init(), when kzalloc htpic fails, it should return -ENOMEM directly, no need to execute "goto" to kfree. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/1594087972-21715-2-git-send-email-yangtiezhu@loongson.cn
2020-07-17irqchip/irq-bcm7038-l1: Allow building on ARM 32-bitFlorian Fainelli1-0/+3
We need to have a definition for cpu_logical_map[] which on ARM platforms is provided by asm/smp_plat.h. This header is not automatically included from linux/smp.h and untangling it is a bit difficult. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200709234141.4901-1-f.fainelli@gmail.com
2020-07-17irqchip/brcmstb-l2: Match UPG_AUX_AON_INTR2 compatibleFlorian Fainelli1-0/+2
The UPG_AUX_AON_INTR2 Level 2 interrupt controller node is defined with the "brcm,upg-aux-aon-l2-intc" compatible string in Device Tree and behaves as an edge triggered standard Broadcom STB L2 interrupt controller. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200709223016.989-7-f.fainelli@gmail.com
2020-07-17irqchip/brcmstb-l2: Match HIF_SPI_INTR2 compatibleKamal Dasu1-0/+2
The HIF_SPI_INTR2 Level 2 interrupt controller node is defined with the "brcm,hif-spi-l2-intc" compatible string in Device Tree and behaves as an edge triggered standard Broadcom STB L2 interrupt controller. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200709223016.989-5-f.fainelli@gmail.com
2020-07-17irqchip/brcmstb-l2: Set controller as wake-up sourceJustin Chen1-0/+1
Utilize the Broadcom interrupt controller standard property "brcm,irq-can-wake" to flag whether this particular interrupt controller instance is wake-up capable. Since we do not know what type of parent interrupt controller we are interfaced with, ensure that enable_irq_wake() is called early on. Signed-off-by: Justin Chen <justinpopo6@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200709223016.989-3-f.fainelli@gmail.com
2020-07-17irqchip/bcm7120-l2: Set controller as wake-up sourceJustin Chen1-3/+5
Utilize the Broadcom interrupt controller standard property "brcm,irq-can-wake" to flag whether this particular interrupt controller instance is wake-up capable. Since we do not know what type of parent interrupt controller we are interfaced with, ensure that enable_irq_wake() is called early on. Signed-off-by: Justin Chen <justinpopo6@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200709223016.989-2-f.fainelli@gmail.com
2020-07-06Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds1-0/+8
Pull kvm fixes from Paolo Bonzini: "Bugfixes and a one-liner patch to silence a sparse warning" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: arm64: Stop clobbering x0 for HVC_SOFT_RESTART KVM: arm64: PMU: Fix per-CPU access in preemptible context KVM: VMX: Use KVM_POSSIBLE_CR*_GUEST_BITS to initialize guest/host masks KVM: x86: Mark CR4.TSD as being possibly owned by the guest KVM: x86: Inject #GP if guest attempts to toggle CR4.LA57 in 64-bit mode kvm: use more precise cast and do not drop __user KVM: x86: bit 8 of non-leaf PDPEs is not reserved KVM: X86: Fix async pf caused null-ptr-deref KVM: arm64: vgic-v4: Plug race between non-residency and v4.1 doorbell KVM: arm64: pvtime: Ensure task delay accounting is enabled KVM: arm64: Fix kvm_reset_vcpu() return code being incorrect with SVE KVM: arm64: Annotate hyp NMI-related functions as __always_inline KVM: s390: reduce number of IO pins to 1
2020-06-27drivers/irqchip: Use new macro ACPI_DECLARE_SUBTABLE_PROBE_ENTRYOscar Carter2-2/+2
In an effort to enable -Wcast-function-type in the top-level Makefile to support Control Flow Integrity builds, there are the need to remove all the function callback casts. To do this, modify the IRQCHIP_ACPI_DECLARE macro to use the new defined macro ACPI_DECLARE_SUBTABLE_PROBE_ENTRY instead of the macro ACPI_DECLARE_PROBE_ENTRY. This is necessary to be able to initialize the the acpi_probe_entry struct using the probe_subtbl field instead of the probe_table field and avoid function cast mismatches. Also, modify the prototype of the functions used by the invocation of the IRQCHIP_ACPI_DECLARE macro to match all the parameters. Co-developed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Oscar Carter <oscar.carter@gmx.com> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Link: https://lore.kernel.org/r/20200530143430.5203-3-oscar.carter@gmx.com
2020-06-27irqchip/atmel-aic5: Add support for sam9x60 rtt fixupClaudiu Beznea1-1/+7
Add support for SAM9X60 RTT fixup. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1591779936-18577-2-git-send-email-claudiu.beznea@microchip.com
2020-06-27irqchip/imx-intmux: Use struct_size() helper in devm_kzalloc()Gustavo A. R. Silva1-2/+1
Make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes. This code was detected with the help of Coccinelle and, audited and fixed manually. Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200616230923.GA24937@embeddedor
2020-06-27irqchip/irq-mtk-sysirq: Replace spinlock with raw_spinlockBartosz Golaszewski1-4/+4
This driver may take a regular spinlock when a raw spinlock (irq_desc->lock) is already taken which results in the following lockdep splat: ============================= [ BUG: Invalid wait context ] 5.7.0-rc7 #1 Not tainted ----------------------------- swapper/0/0 is trying to lock: ffffff800303b798 (&chip_data->lock){....}-{3:3}, at: mtk_sysirq_set_type+0x48/0xc0 other info that might help us debug this: context-{5:5} 2 locks held by swapper/0/0: #0: ffffff800302ee68 (&desc->request_mutex){....}-{4:4}, at: __setup_irq+0xc4/0x8a0 #1: ffffff800302ecf0 (&irq_desc_lock_class){....}-{2:2}, at: __setup_irq+0xe4/0x8a0 stack backtrace: CPU: 0 PID: 0 Comm: swapper/0 Not tainted 5.7.0-rc7 #1 Hardware name: Pumpkin MT8516 (DT) Call trace: dump_backtrace+0x0/0x180 show_stack+0x14/0x20 dump_stack+0xd0/0x118 __lock_acquire+0x8c8/0x2270 lock_acquire+0xf8/0x470 _raw_spin_lock_irqsave+0x50/0x78 mtk_sysirq_set_type+0x48/0xc0 __irq_set_trigger+0x58/0x170 __setup_irq+0x420/0x8a0 request_threaded_irq+0xd8/0x190 timer_of_init+0x1e8/0x2c4 mtk_gpt_init+0x5c/0x1dc timer_probe+0x74/0xf4 time_init+0x14/0x44 start_kernel+0x394/0x4f0 Replace the spinlock_t with raw_spinlock_t to avoid this warning. Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200615074445.3579-1-brgl@bgdev.pl
2020-06-27irqchip/vic: Cut down the external APILinus Walleij1-1/+4
There are registers and functions in the header file that are only used inside the driver. Move these into the driver. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200607215124.48638-2-linus.walleij@linaro.org
2020-06-27irqchip/vic: Drop cascaded intialization callLinus Walleij1-21/+0
We got rid of the last user of the cascaded intialization from board files so drop this API. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200607215124.48638-1-linus.walleij@linaro.org
2020-06-27irqchip/ti-sci-inta: Fix typo about MODULE_AUTHORTiezhu Yang1-1/+1
It should be "ti.com" instead of "ticom". Fixes: 9f1463b86c13 ("irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/1591437017-5295-3-git-send-email-yangtiezhu@loongson.cn
2020-06-27irqchip/ti-sci-inta: Fix return value about devm_ioremap_resource()Tiezhu Yang1-1/+1
When call function devm_ioremap_resource(), we should use IS_ERR() to check the return value and return PTR_ERR() if failed. Fixes: 9f1463b86c13 ("irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/1591437017-5295-2-git-send-email-yangtiezhu@loongson.cn
2020-06-27irqchip/ti-sci-inta: Remove dead code in ti_sci_inta_set_type()Tiezhu Yang1-2/+0
In the function ti_sci_inta_set_type(), the statement "return -EINVAL;" out of switch case is dead code, remove it. Fixes: 9f1463b86c13 ("irqchip/ti-sci-inta: Add support for Interrupt Aggregator driver") Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/1591437017-5295-1-git-send-email-yangtiezhu@loongson.cn
2020-06-23KVM: arm64: vgic-v4: Plug race between non-residency and v4.1 doorbellMarc Zyngier1-0/+8
When making a vPE non-resident because it has hit a blocking WFI, the doorbell can fire at any time after the write to the RD. Crucially, it can fire right between the write to GICR_VPENDBASER and the write to the pending_last field in the its_vpe structure. This means that we would overwrite pending_last with stale data, and potentially not wakeup until some unrelated event (such as a timer interrupt) puts the vPE back on the CPU. GICv4 isn't affected by this as we actively mask the doorbell on entering the guest, while GICv4.1 automatically manages doorbell delivery without any hypervisor-driven masking. Use the vpe_lock to synchronize such update, which solves the problem altogether. Fixes: ae699ad348cdc ("irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer") Reported-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-21irqchip/gic: Atomically update affinityMarc Zyngier1-11/+3
The GIC driver uses a RMW sequence to update the affinity, and relies on the gic_lock_irqsave/gic_unlock_irqrestore sequences to update it atomically. But these sequences only expand into anything meaningful if the BL_SWITCHER option is selected, which almost never happens. It also turns out that using a RMW and locks is just as silly, as the GIC distributor supports byte accesses for the GICD_TARGETRn registers, which when used make the update atomic by definition. Drop the terminally broken code and replace it by a byte write. Fixes: 04c8b0f82c7d ("irqchip/gic: Make locking a BL_SWITCHER only feature") Cc: stable@vger.kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org>
2020-06-21irqchip/riscv-intc: Fix a typo in a pr_warn()Palmer Dabbelt1-1/+1
Anup originally re-spun his patch set to include this fix, but it was a bit too late for my PR so I've split it out. Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200611175302.253540-1-palmer@dabbelt.com
2020-06-21irqchip/gic-v4.1: Use readx_poll_timeout_atomic() to fix sleep in atomicZenghui Yu1-4/+4
readx_poll_timeout() can sleep if @sleep_us is specified by the caller, and is therefore unsafe to be used inside the atomic context, which is this case when we use it to poll the GICR_VPENDBASER.Dirty bit in irq_set_vcpu_affinity() callback. Let's convert to its atomic version instead which helps to get the v4.1 board back to life! Fixes: 96806229ca03 ("irqchip/gic-v4.1: Add support for VPENDBASER's Dirty+Valid signaling") Signed-off-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200605052345.1494-1-yuzenghui@huawei.com
2020-06-21irqchip/loongson-pci-msi: Fix a typo in KconfigJiaxun Yang1-1/+1
PCH MSI driver's menuconfig entry was wrong. Fix it. Fixes: 632dcc2c75ef ("irqchip: Add Loongson PCH MSI controller") Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200530121113.1797678-2-jiaxun.yang@flygoat.com
2020-06-09clocksource/drivers/timer-riscv: Use per-CPU timer interruptAnup Patel1-8/+0
Instead of directly calling RISC-V timer interrupt handler from RISC-V local interrupt conntroller driver, this patch implements RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs of Linux IRQ subsystem. Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-06-09irqchip: RISC-V per-HART local interrupt controller driverAnup Patel4-9/+183
The RISC-V per-HART local interrupt controller manages software interrupts, timer interrupts, external interrupts (which are routed via the platform level interrupt controller) and other per-HART local interrupts. We add a driver for the RISC-V local interrupt controller, which eventually replaces the RISC-V architecture code, allowing for a better split between arch code and drivers. The driver is compliant with RISC-V Hart-Level Interrupt Controller DT bindings located at: Documentation/devicetree/bindings/interrupt-controller/riscv,cpu-intc.txt Co-developed-by: Palmer Dabbelt <palmer@dabbelt.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> [Palmer: Cleaned up warnings] Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
2020-06-09RISC-V: Rename and move plic_find_hart_id() to arch directoryAnup Patel1-15/+1
The plic_find_hart_id() can be useful to other interrupt controller drivers (such as RISC-V local interrupt driver) so we rename this function to riscv_of_parent_hartid() and place it in arch directory along with riscv_of_processor_hartid(). Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2020-06-01irqchip: Fix "Loongson HyperTransport Vector support" driver build on all ↵Ingo Molnar1-1/+1
non-MIPS platforms This commit: 818e915fbac5: ("irqchip: Add Loongson HyperTransport Vector support") Added a MIPS-only driver, but turned on compilation on all other architectures as well: config LOONGSON_HTVEC bool "Loongson3 HyperTransport Interrupt Vector Controller" depends on MACH_LOONGSON64 || COMPILE_TEST But this driver was never build tested on any other architecture than MIPS: drivers/irqchip/irq-loongson-htvec.c: In function ‘htvec_irq_dispatch’: drivers/irqchip/irq-loongson-htvec.c:59:3: error: implicit declaration of function ‘spurious_interrupt’; did you mean ‘smp_reboot_interrupt’? [-Werror=implicit-function-declaration] Because spurious_interrupt() only exists on MIPS. So make it MIPS-only. Signed-off-by: Ingo Molnar <mingo@kernel.org> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@kernel.org>
2020-05-29irqchip: Add Loongson PCH MSI controllerJiaxun Yang3-0/+266
This controller appears on Loongson LS7A family of PCH to transform interrupts from PCI MSI into HyperTransport vectorized interrrupts and send them to procrssor's HT vector controller. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20200528152757.1028711-6-jiaxun.yang@flygoat.com
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