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Enable device system suspend and resume PM support, and mark the device
state as suspended during system suspend to reject any data transfer.
Signed-off-by: Ji Sheng Teoh <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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DRV_NAME was useful back in the days. But here, being used once, it is
only cruft.
Signed-off-by: Wolfram Sang <[email protected]>
Reviewed-by: Chris Packham <[email protected]>
Tested-by: Chris Packham <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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"i2c-scl-clk-low-timeout-us" is wrongly used here because it describes
maximum clock stretching not maximum transfer time. Additionally, it is
deprecated because of issues. Move this driver to the correct binding.
Signed-off-by: Wolfram Sang <[email protected]>
Reviewed-by: Chris Packham <[email protected]>
Tested-by: Chris Packham <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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If this is an adapter on a muxed bus segment, assume that each segment
is connected to a subset of the (> 8) overall memory slots. In this
case let's probe the maximum of 8 slots, however stop if the number
of overall populated slots is reached.
If we're not on a muxed segment and the total number of slots is > 8,
then warn because then not all SPD eeproms can be addressed.
Presumably the bus is muxed, but the mux config is missing.
Signed-off-by: Heiner Kallweit <[email protected]>
[wsa: removed a superfluous printout]
Signed-off-by: Wolfram Sang <[email protected]>
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Since commit aed65af1cc2f ("drivers: make device_type const"), the driver
core can properly handle constant struct device_type. Move the
i2c_adapter_type and i2c_client_type variables to be constant structures as
well, placing it into read-only memory which can not be modified at
runtime.
Signed-off-by: Ricardo B. Marliere <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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I got an idea the i2c-designware should not need duplicated state
machines for the interrupt and polling modes. The IP is practically the
same and state transitions happens in response to the events that can be
observed from the DW_IC_RAW_INTR_STAT register. Either by interrupts or
by polling.
Another reasons are the interrupt mode is the most tested, has handling
for special cases as well as transmit abort handling and those are
missing from two polling mode quirks.
Patch implements a generic polling mode by using existing code for
interrupt mode. This is done by moving event handling from the
i2c_dw_isr() into a new i2c_dw_process_transfer() that will be called
both from the i2c_dw_isr() and a polling loop.
Polling loop is implemented in a new i2c_dw_wait_transfer() that is
shared between both modes. In interrupt mode it waits for the completion
object as before. In polling mode both completion object and
DW_IC_RAW_INTR_STAT are polled to determine completed transfer and state
transitions.
Loop tries to save power by sleeping "stetson guessed" range between
3 and 25 µS which falls between 10 cycles of High-speed mode 3.4 Mb/s
and Fast mode 400 kHz. With it the CPU usage was reduced under heavy
Fast mode I2C transfer without much increase in total transfer time but
otherwise no more effort has been put to optimize this.
I decided to convert the txgbe_i2c_dw_xfer_quirk() straight to generic
polling mode code in this patch. It doesn't have HW dependent quirks
like the amd_i2c_dw_xfer_quirk() does have and without users this patch
is needless.
Signed-off-by: Jarkko Nikula <[email protected]>
Tested-by: Jiawen Wu <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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I believe RX FIFO depth define 0 is incorrect on Wangxun 10Gb NIC. It
must be at least 1 since code is able to read received data from the
DW_IC_DATA_CMD register.
For now this define is irrelevant since the txgbe_i2c_dw_xfer_quirk()
doesn't use the rx_fifo_depth member variable of struct dw_i2c_dev but
is needed when converting code into generic polling mode implementation.
Signed-off-by: Jarkko Nikula <[email protected]>
Tested-by: Jiawen Wu <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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Code is more logically arranged when i2c_dw_read_clear_intrbits() and
i2c_dw_isr() are located before i2c_dw_xfer().
Real reason for this is to prepare for more shared code between
interrupt and polling mode code.
While at it, remove one extra space and refer to the
i2c_dw_init_master() in two comment sections.
Signed-off-by: Jarkko Nikula <[email protected]>
Tested-by: Jiawen Wu <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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Convert access to DW_IC_INTR_MASK register using the existing
__i2c_dw_write_intr_mask() and a __i2c_dw_read_intr_mask() introduced
here. Motivation to this is to prepare for generic polling mode code
where polling mode will use a SW mask instead of DW_IC_INTR_MASK.
Signed-off-by: Jarkko Nikula <[email protected]>
Tested-by: Jiawen Wu <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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I was testing the polling mode txgbe_i2c_dw_xfer_quirk() on a HW where
the i2c-designware has interrupt connected and shared with other device.
I noticed there is a bogus interrupt for each transfer.
Reason for this that both polling mode functions call the
i2c_dw_xfer_init() which enable interrupts then followed by immediate
disable by the same polling mode functions. This is enough to trigger
TX_EMPTY interrupt.
Fix this by introducing a __i2c_dw_write_intr_mask() helper that unmasks
interrupts conditionally and use it in i2c_dw_xfer_init().
Signed-off-by: Jarkko Nikula <[email protected]>
Tested-by: Jiawen Wu <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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Currently initialization flow in i2c_dw_probe_master() skips a few steps
and has code duplication for polling mode implementation.
Simplify this by adding a new ACCESS_POLLING flag that is set for those
two platforms that currently use polling mode and use it to skip
interrupt handler setup.
Signed-off-by: Jarkko Nikula <[email protected]>
Tested-by: Jiawen Wu <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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When being a target, NAK from the controller means that all bytes have
been transferred. So, the last byte needs also to be marked as
'processed'. Otherwise index registers of backends may not increase.
Fixes: f7414cd6923f ("i2c: imx: support slave mode for imx I2C driver")
Signed-off-by: Corey Minyard <[email protected]>
Tested-by: Andrew Manley <[email protected]>
Reviewed-by: Andrew Manley <[email protected]>
Reviewed-by: Oleksij Rempel <[email protected]>
[wsa: fixed comment and commit message to properly describe the case]
Signed-off-by: Wolfram Sang <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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In the npcm_i2c_reg_slave() function, there was a redundant
comparison that checked if 'bus->slave' was null immediately after
assigning it the 'client' value. There were concerns about a
potential null dereference because of `client->adapter`, but
according to Wolfram Sang, "we trusted ourselves here" Therefore,
this comparison is unnecessary.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Rand Deeb <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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According to the Intel datasheets, software must reset the block
buffer index twice for block process call transactions: once before
writing the outgoing data to the buffer, and once again before
reading the incoming data from the buffer.
The driver is currently missing the second reset, causing the wrong
portion of the block buffer to be read.
Signed-off-by: Jean Delvare <[email protected]>
Reported-by: Piotr Zakowski <[email protected]>
Closes: https://lore.kernel.org/linux-i2c/[email protected]/
Fixes: 315cd67c9453 ("i2c: i801: Add Block Write-Block Read Process Call support")
Reviewed-by: Alexander Sverdlin <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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On powerpc, it is possible to compile test both the new apple (arm) and
old pasemi (powerpc) drivers for the i2c hardware at the same time,
which leads to a warning about linking the same object file twice:
scripts/Makefile.build:244: drivers/i2c/busses/Makefile: i2c-pasemi-core.o is added to multiple modules: i2c-apple i2c-pasemi
Rework the driver to have an explicit helper module, letting Kbuild
take care of whether this should be built-in or a loadable driver.
Fixes: 9bc5f4f660ff ("i2c: pasemi: Split pci driver to its own file")
Signed-off-by: Arnd Bergmann <[email protected]>
Reviewed-by: Sven Peter <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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For i2c read operation in GSI mode, we are getting timeout
due to malformed TRE basically incorrect TRE sequence
in gpi(drivers/dma/qcom/gpi.c) driver.
I2C driver has geni_i2c_gpi(I2C_WRITE) function which generates GO TRE and
geni_i2c_gpi(I2C_READ)generates DMA TRE. Hence to generate GO TRE before
DMA TRE, we should move geni_i2c_gpi(I2C_WRITE) before
geni_i2c_gpi(I2C_READ) inside the I2C GSI mode transfer function
i.e. geni_i2c_gpi_xfer().
TRE stands for Transfer Ring Element - which is basically an element with
size of 4 words. It contains all information like slave address,
clk divider, dma address value data size etc).
Mainly we have 3 TREs(Config, GO and DMA tre).
- CONFIG TRE : consists of internal register configuration which is
required before start of the transfer.
- DMA TRE : contains DDR/Memory address, called as DMA descriptor.
- GO TRE : contains Transfer directions, slave ID, Delay flags, Length
of the transfer.
I2c driver calls GPI driver API to config each TRE depending on the
protocol.
For read operation tre sequence will be as below which is not aligned
to hardware programming guide.
- CONFIG tre
- DMA tre
- GO tre
As per Qualcomm's internal Hardware Programming Guide, we should configure
TREs in below sequence for any RX only transfer.
- CONFIG tre
- GO tre
- DMA tre
Fixes: d8703554f4de ("i2c: qcom-geni: Add support for GPI DMA")
Reviewed-by: Andi Shyti <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Tested-by: Bryan O'Donoghue <[email protected]> # qrb5165-rb5
Co-developed-by: Mukesh Kumar Savaliya <[email protected]>
Signed-off-by: Mukesh Kumar Savaliya <[email protected]>
Signed-off-by: Viken Dadhaniya <[email protected]>
Reviewed-by: Dmitry Baryshkov <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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Avoid code duplication and factor out retrieving and checking the
block length value to new helper i801_get_block_len().
Signed-off-by: Heiner Kallweit <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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Add a sentinel length value that is used to check whether we should
read and use the length value provided by the slave device.
This simplifies the currently used checks.
Signed-off-by: Heiner Kallweit <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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i2c and smbus block transaction handling have little in common,
therefore split this function to improve code readability.
Signed-off-by: Heiner Kallweit <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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Avoid code duplication and factor out checking and clearing PEC error
bit to new helper i801_check_and_clear_pec_error().
Signed-off-by: Heiner Kallweit <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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This change simplifies the code a little and makes clearer that the
ICH5 feature set is an extension of the ICH4 feature set.
Signed-off-by: Heiner Kallweit <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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The driver receives the tx fifo almost empty(aempty) interrupt and
reads the tx_aempty_int_mstat to start a round of data transfer.
The operation of clearing the TX aempty interrupt after completing
a write cycle is added to ensure that the FIFO is truly at almost
empty status when an aempty interrupt is received.
The threshold for fifo almost empty interrupt is defined as 1.
Signed-off-by: Devyn Liu <[email protected]>
Reviewed-by: Yicong Yang <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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The driver finishes a write cycle by read the fifo tx full status
or write limit decrease to 0. The driver starts to write data to
the FIFO after the I2C FIFO almost empty interrupt is reported.
The threshold for FIFO almost empty interrupt is that the amount
of data in the FIFO is less than or equal to 1.
Reduce write maxwrite to the fifo depth - aempty interrupt
threshold. Limiting the number of data to be written at a time
to remaining fifo capacity.
Signed-off-by: Devyn Liu <[email protected]>
Reviewed-by: Yicong Yang <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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calculation
Switch the R-Mobile A1, R-Mobile APE6, and SH-Mobile AG5 SoCs to the new
frequency calculation formula, to (a) avoid running the I2C bus too fast,
and (b) bring the low/high ratio closer to the recommended ratio 5/4.
As this makes fast_clock_dt_config and v2_freq_calc_dt_config identical,
merge them into a single fast_clock_dt_config.
Legacy SH users (sh7343, sh7366, and sh772[234]) are left alone, and
still use the old formula.
Measurement results on R-Mobile APE6 and SH-Mobile AG5 (fck=104 MHz,
clks_per_count=2):
100 kHz: 106 kHz LH=1.12 before, 99.6 kHz L/H=1.22 after
400 kHz: 384 kHz LH=1.67 before, 392 kHz L/H=1.27 after
Measurement results on R-Mobile A1 (fck=49.5 MHz, clks_per_count=1):
100 kHz: 106 kHz L/H=1.09 before, 99.6 kHz L/H=1.20 after
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Wolfram Sang <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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Starting with
commit 75820314de26 ("i2c: core: add generic I2C GPIO recovery")
GPIO bus recovery is supported by the I2C core, so we can remove the
driver implementation and use that one instead.
As a nice side-effect, pinctrl becomes optional, allowing bus recovery on
LS1021A, which does not have such luxury, but can be wired up to use extra
fixed GPIO pins.
Note: The previous error messages about bus recovery not being supported is
dropped with this change. Given that it is perfectly possible to have platforms
where bus recovery works without pinctrl support, I happen to work on one such,
both error messages does not really make sense in those cases. And I don't see
how to know if this is the case or not.
Signed-off-by: Esben Haabendal <[email protected]>
Acked-by: Oleksij Rempel <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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Argument priv isn't used, so remove it.
Signed-off-by: Heiner Kallweit <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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Replace magic number 10 with the appropriate constant.
Signed-off-by: Heiner Kallweit <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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Enable additional features based on DT settings and unconditionally
release the shared interrupt pin after 1.6 seconds and allow to use
it as reset.
These features aren't enabled by default and it's up to board designer
to validate for proper functioning and detection of devices in secondary
bus as sometimes it can cause secondary bus being disabled.
Signed-off-by: Patrick Rudolph <[email protected]>
Signed-off-by: Naresh Solanki <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Andi Shyti <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c updates from Wolfram Sang:
"This removes the currently unused CLASS_DDC support (controllers set
the flag, but there is no client to use it).
Also, CLASS_SPD support gets simplified to prepare removal in the
future. Class based instantiation is not recommended these days
anyhow.
Furthermore, I2C core now creates a debugfs directory per I2C adapter.
Current bus driver users were converted to use it.
Finally, quite some driver updates. Standing out are patches for the
wmt-driver which is refactored to support more variants.
This is the rebased pull request where a large series for the
designware driver was dropped"
* tag 'i2c-for-6.8-rc1-rebased' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: (38 commits)
MAINTAINERS: use proper email for my I2C work
i2c: stm32f7: add support for stm32mp25 soc
i2c: stm32f7: perform I2C_ISR read once at beginning of event isr
dt-bindings: i2c: document st,stm32mp25-i2c compatible
i2c: stm32f7: simplify status messages in case of errors
i2c: stm32f7: perform most of irq job in threaded handler
i2c: stm32f7: use dev_err_probe upon calls of devm_request_irq
i2c: i801: Add lis3lv02d for Dell XPS 15 7590
i2c: i801: Add lis3lv02d for Dell Precision 3540
i2c: wmt: Reduce redundant: REG_CR setting
i2c: wmt: Reduce redundant: function parameter
i2c: wmt: Reduce redundant: clock mode setting
i2c: wmt: Reduce redundant: wait event complete
i2c: wmt: Reduce redundant: bus busy check
i2c: mux: reg: Remove class-based device auto-detection support
i2c: make i2c_bus_type const
dt-bindings: at24: add ROHM BR24G04
eeprom: at24: use of_match_ptr()
i2c: cpm: Remove linux,i2c-index conversion from be32
i2c: imx: Make SDA actually optional for bus recovering
...
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The stm32mp25 has only a single interrupt line used for both
events and errors. In order to cope with that, reorganise the
error handling code so that it can be called either from the
common handler (used in case of SoC having only a single IT line)
and the error handler for others.
The CR1 register also embeds a new FMP bit, necessary when running
at Fast Mode Plus frequency. This bit should be used instead of
the SYSCFG bit used on other platforms.
Add a new compatible to distinguish between the SoCs and two
boolean within the setup structure in order to know if the
platform has a single/multiple IT lines and if the FMP bit
within CR1 is available or not.
Signed-off-by: Valentin Caron <[email protected]>
Signed-off-by: Alain Volmat <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Move readl_relaxed of I2C_ISR register at beginning of event isr
so that it done once for both master & slave handling.
Signed-off-by: Alain Volmat <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Avoid usage of __func__ when reporting an error message
since dev_err/dev_dbg are already providing enough details
to identify the source of the message.
Signed-off-by: Alain Volmat <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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The irq handling is currently split between the irq handler
and the threaded irq handler. Some of the handling (such as
dma related stuffs) done within the irq handler might sleep or
take some time leading to issues if the kernel is built with
realtime constraints. In order to fix that, perform an overall
rework to perform most of the job within the threaded handler
and only keep fifo access in the non threaded handler.
Signed-off-by: Alain Volmat <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Convert error handling upon calls of devm_request_irq functions during
the probe of the driver.
Signed-off-by: Alain Volmat <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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On the Dell XPS 15 7590/0VYV0G, BIOS 1.24.0 09/11/2023, Linux prints the
warning below.
i801_smbus 0000:00:1f.4: Accelerometer lis3lv02d is present on SMBus but its address is unknown, skipping registration
Following the same suggestions by Wolfram Sang as for the Dell Precision
3540 [1], the accelerometer can be successfully found on I2C bus 2 at
address 0x29.
$ echo lis3lv02d 0x29 | sudo tee /sys/bus/i2c/devices/i2c-2/new_device
lis3lv02d 0x29
$ dmesg | tail -5
[ 549.522876] lis3lv02d_i2c 2-0029: supply Vdd not found, using dummy regulator
[ 549.522904] lis3lv02d_i2c 2-0029: supply Vdd_IO not found, using dummy regulator
[ 549.542486] lis3lv02d: 8 bits 3DC sensor found
[ 549.630022] input: ST LIS3LV02DL Accelerometer as /devices/platform/lis3lv02d/input/input35
[ 549.630586] i2c i2c-2: new_device: Instantiated device lis3lv02d at 0x29
So, the device has that accelerometer. Add the I2C address to the
mapping list, and test it successfully on the device.
[1]: https://lore.kernel.org/linux-i2c/[email protected]/
Signed-off-by: Paul Menzel <[email protected]>
Acked-by: Pali Rohár <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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On the Dell Precision 3540/0M14W7, BIOS 1.7.4 05/12/2020, Linux prints
the warning below.
i801_smbus 0000:00:1f.4: Accelerometer lis3lv02d is present on SMBus but its address is unknown, skipping registration
With the help of Wolfram Sang, the test to probe it on I2C bus 6 at address
0x29 was successful.
$ echo lis3lv02d 0x29 | sudo tee /sys/bus/i2c/devices/i2c-6/new_device
[ 2110.787000] i2c i2c-6: new_device: Instantiated device lis3lv02d at 0x29
[ 2110.791932] lis3lv02d_i2c 6-0029: supply Vdd not found, using dummy regulator
[ 2110.791981] lis3lv02d_i2c 6-0029: supply Vdd_IO not found, using dummy regulator
[ 2110.809233] lis3lv02d: 8 bits 3DC sensor found
[ 2110.900668] input: ST LIS3LV02DL Accelerometer as /devices/platform/lis3lv02d/input/input23
So, the device has that accelerometer. Add the I2C address to the
mapping list.
Link: https://lore.kernel.org/linux-i2c/[email protected]/
Signed-off-by: Paul Menzel <[email protected]>
Acked-by: Pali Rohár <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
[wsa: shortened commit message a little]
Signed-off-by: Wolfram Sang <[email protected]>
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These Settings for the same register, REG_CR,
can be put together to reduce code redundancy.
Signed-off-by: Hans Hu <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Use more appropriate parameter passing to reduce the amount of code
Signed-off-by: Hans Hu <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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The frequency setting mode is adjusted to reduce the code redundancy,
and it is also convenient to share with zhaoxin
Signed-off-by: Hans Hu <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Put the handling of interrupt events in a function class
to reduce code redundancy.
Signed-off-by: Hans Hu <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Put wmt_i2c_wait_bus_not_busy() in a more appropriate place
to reduce code redundancy
Signed-off-by: Hans Hu <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Legacy class-based device auto-detection shouldn't be used in new code.
Therefore remove support in i2c-mux-reg as long as we don't have a
user of this feature yet.
Link: https://lore.kernel.org/linux-i2c/[email protected]/
Signed-off-by: Heiner Kallweit <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Now that the driver core can properly handle constant struct bus_type,
move the i2c_bus_type variable to be a constant structure as well, placing
it into read-only memory which can not be modified at runtime.
Note, the sound/soc/rockchip/rk3399_gru_sound.c also needed tweaking as
it decided to save off a pointer to a bus type for internal stuff, and
it was using the i2c_bus_type as well.
Signed-off-by: Greg Kroah-Hartman <[email protected]>
Acked-by: Mark Brown <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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sparse reports an error on some data that gets converted from be32.
That's because that data is typed u32 instead of __be32.
The type is correct, the be32_to_cpu() conversion is not.
Remove the conversion.
Reported-by: kernel test robot <[email protected]>
Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Signed-off-by: Christophe Leroy <[email protected]>
Acked-By: Jochen Friedrich <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Both i2c_generic_scl_recovery() and the debug output indicate that SDA is
purely optional for bus recovery. But devm_gpiod_get() never returns NULL
making it mandatory. Fix this by calling devm_gpiod_get_optional instead.
Signed-off-by: Alexander Stein <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Reviewed-by: Oleksij Rempel <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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I originally restricted i2c_register_spd() to only support systems
with up to 4 memory slots, so that we can experiment with it on
a limited numbers of systems. It's been more than 3 years and it
seems to work just fine, so the time has come to lift this arbitrary
limitation.
The maximum number of memory slots which can be connected to a single
I2C segment is 8, so support that many SPD EEPROMs. Any system with
more than 8 memory slots would have either multiple SMBus channels
or SMBus multiplexing, so it would need dedicated care. We'll get to
that later as needed.
Signed-off-by: Jean Delvare <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Rockchip RV1126 is using old style i2c controller, the i2c2
bus uses a non-sequential offset in the grf register for the
mask/value bits for this bus.
This patch fixes i2c2 bus on rv1126 SoCs.
Signed-off-by: Tim Lunn <[email protected]>
Acked-by: Heiko Stuebner <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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Add support for atomic transfers using polling mode with interrupts
intentionally disabled to get rid of the following warning introduced by
commit 63b96983a5dd ("i2c: core: introduce callbacks for atomic
transfers") during system reboot and power-off:
------------[ cut here ]------------
WARNING: CPU: 0 PID: 1518 at drivers/i2c/i2c-core.h:40 i2c_transfer+0xe8/0xf4
No atomic I2C transfer handler for 'i2c-0'
...
---[ end trace 0000000000000000 ]---
Signed-off-by: Marek Szyprowski <[email protected]>
Reviewed-by: Chanho Park <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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To properly handle ACK on the bus when transferring more than one
message in polling mode, move the polling handling loop from
s3c24xx_i2c_message_start() to s3c24xx_i2c_doxfer(). This way
i2c_s3c_irq_nextbyte() is always executed till the end, properly
acknowledging the IRQ bits and no recursive calls to
i2c_s3c_irq_nextbyte() are made.
While touching this, also fix finishing transfers in polling mode by
using common code path and always waiting for the bus to become idle
and disabled.
Fixes: 117053f77a5a ("i2c: s3c2410: Add polling mode support")
Signed-off-by: Marek Szyprowski <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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To properly handle read transfers in polling mode, no waiting for the ACK
state is needed as it will never come. Just wait a bit to ensure start
state is on the bus and continue processing next bytes.
Fixes: 117053f77a5a ("i2c: s3c2410: Add polling mode support")
Signed-off-by: Marek Szyprowski <[email protected]>
Reviewed-by: Chanho Park <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Signed-off-by: Wolfram Sang <[email protected]>
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