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2023-11-30drm/amdgpu: enable mca debug mode on APU by defaultYang Wang1-1/+2
enable MCA debug mode on APU device by default. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-30drm/amdgpu: distinguish rlc fw for different SKULikun Gao1-1/+6
For some SKU, rlc firmware should use different one compared with the normal rlc firmware. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-30drm/amdgpu: Fix missing mca debugfs nodeYang Wang1-1/+1
Use amdgpu_ip_version() helper function to check ip version. The ip version contains other information, use the helper function to avoid reading wrong value. Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Yang Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-30drm/amdgpu: Skip access gfx11 golden registers under SRIOVZhenGuo Yin1-0/+3
[Why] Golden registers are PF-only registers on gfx11. RLCG interface will return "out-of-range" under SRIOV VF. [How] Skip access gfx11 golden registers under SRIOV. Reviewed-by: Horace Chen <[email protected]> Signed-off-by: ZhenGuo Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-12-01Merge tag 'drm-misc-fixes-2023-11-29' of ↵Dave Airlie7-27/+10
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes Fixes for v6.7-rc4: - Revert panel fixes as they require exporting device_is_dependent. - Do not double add fences in dma_resv_add_fence. - Fix GPUVM license identifier. - Assorted nouveau fixes. - Fix error check for nt36523. Signed-off-by: Dave Airlie <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-30drm/i915/guc: Add a selftest for FAST_REQUEST errorsJohn Harrison3-0/+128
There is a mechanism for reporting errors from fire and forget H2G messages. This is the only way to find out about almost any error in the GuC backend submission path. So it would be useful to know that it is working. v2: Fix some dumb over-complications and a couple of typos - review feedback from Daniele. Signed-off-by: John Harrison <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-30drm/i915/guc: Fix for potential false positives in GuC hang selftestJohn Harrison1-1/+1
Noticed that the hangcheck selftest is submitting a non-preemptoble spinner. That means that even if the GuC does not die, the heartbeat will still kick in and trigger a reset. Which is rather defeating the purpose of the test - to verify that the heartbeat will kick in if the GuC itself has died. The test is deliberately killing the GuC, so it should never hit the case of a non-dead GuC. But it is not impossible that the kill might fail at some future point due to other driver re-work. So, make the spinner pre-emptible. That way the heartbeat can get through if the GuC is alive and context switching. Thus a reset only happens if the GuC dies. Thus, if the kill should stop working the test will now fail rather than claim to pass. Signed-off-by: John Harrison <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-30Revert "drm/prime: Unexport helpers for fd/handle conversion"Felix Kuehling1-15/+18
This reverts commit 71a7974ac7019afeec105a54447ae1dc7216cbb3. These helper functions are needed for KFD to export and import DMABufs the right way without duplicating the tracking of DMABufs associated with GEM objects while ensuring that move notifier callbacks are working as intended. CC: Christian König <[email protected]> CC: Thomas Zimmermann <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Acked-by: Daniel Vetter <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-30drm/panfrost: Fix incorrect updating of current device frequencyAdrián Larumbe1-2/+15
It was noticed when setting the Panfrost's DVFS device to the performant governor, GPU frequency as reported by fdinfo had dropped to 0 permamently. There are two separate issues causing this behaviour: - Not initialising the device's current_frequency variable to its original value during device probe(). - Updating said variable in Panfrost devfreq's get_dev_status() rather than after the new OPP's frequency had been retrieved in target(), which meant the old frequency would be assigned instead. Signed-off-by: Adrián Larumbe <[email protected]> Fixes: f11b0417eec2 ("drm/panfrost: Add fdinfo support GPU load metrics") Reviewed-by: Steven Price <[email protected]> Signed-off-by: Steven Price <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-30drm/panfrost: Consider dma-buf imported objects as residentAdrián Larumbe1-1/+1
A GEM object constructed from a dma-buf imported sgtable should be regarded as being memory resident, because the dma-buf API mandates backing storage to be allocated when attachment succeeds. Signed-off-by: Adrián Larumbe <[email protected]> Fixes: 9ccdac7aa822 ("drm/panfrost: Add fdinfo support for memory stats") Reported-by: Boris Brezillon <[email protected]> Reviewed-by: Steven Price <[email protected]> Signed-off-by: Steven Price <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-30drm/imagination: fix off by one in pvr_vm_mips_init() error handlingDan Carpenter1-6/+5
If the call to vmap() fails the "page_nr" is one element beyond the end of the mips_data->pt_dma_addr[] and mips_data->pt_pages[] arrays. The way that this is traditionally written is that we clean up the partial loop iteration before the goto and then we can say while (--i >= 0). At that point we know that all the elements thus far are initialized so we don't need to have NULL checks. Fixes: 927f3e0253c1 ("drm/imagination: Implement MIPS firmware processor and MMU support") Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Frank Binns <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-30drm/imagination: Fix IS_ERR() vs NULL bug in pvr_request_firmware()Dan Carpenter1-2/+2
The pvr_build_firmware_filename() function returns NULL on error. It doesn't return error pointers. Fixes: f99f5f3ea7ef ("drm/imagination: Add GPU ID parsing and firmware loading") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-30drm/imagination: Fix error codes in pvr_device_clk_init()Dan Carpenter1-2/+2
There is a cut and paste error so this code returns the wrong variable. Fixes: 1f88f017e649 ("drm/imagination: Get GPU resources") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-30nouveau/tu102: flush all pdbs on vmm flushDave Airlie1-1/+1
This is a hack around a bug exposed with the GSP code, I'm not sure what is happening exactly, but it appears some of our flushes don't result in proper tlb invalidation for out BAR2 and we get a BAR2 fault from GSP and it all dies. Signed-off-by: Dave Airlie <[email protected]> Signed-off-by: Danilo Krummrich <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-29drm/i915: Skip pxp init if gt is wedgedZhanjun Dong2-1/+6
The gt wedged could be triggered by missing guc firmware file, HW not working, etc. Once triggered, it means all gt usage is dead, therefore we can't enable pxp under this fatal error condition. v2: Updated commit message. v3: Updated return code check. Signed-off-by: Zhanjun Dong <[email protected]> Reviewed-by: Alan Previn <[email protected]> Signed-off-by: John Harrison <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-30drm/nouveau: Removes unnecessary args check in nouveau_uvmm_sm_prepareYuran Pereira1-1/+4
Checking `args` after calling `op_map_prepare` is unnecessary since if `op_map_prepare` was to be called with NULL args, it would lead to a NULL pointer dereference, thus never hitting that check. Hence remove the check and add a note to remind users of this function to ensure that args != NULL when calling this function for a map operation as it was suggested by Danilo [1]. [1] https://lore.kernel.org/lkml/[email protected] Suggested-by: Danilo Krummrich <[email protected]> Signed-off-by: Yuran Pereira <[email protected]> Signed-off-by: Danilo Krummrich <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/GV1PR10MB65637F4BAABFE2D8E261E1DCE8B0A@GV1PR10MB6563.EURPRD10.PROD.OUTLOOK.COM
2023-11-30nouveau/gsp: document some aspects of GSP-RMTimur Tabi2-0/+133
Document a few aspects of communication with GSP-RM. These comments are derived from notes made during early development of GSP-RM support in Nouveau, but were not included in the initial patch set. Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Timur Tabi <[email protected]> Reviewed-by: Danilo Krummrich <[email protected]> Signed-off-by: Danilo Krummrich <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-29drm/amdgpu: Use another offset for GC 9.4.3 remapLijo Lazar1-0/+5
The legacy region at 0x7F000 maps to valid registers in GC 9.4.3 SOCs. Use 0x1A000 offset instead as MMIO register remap region. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Fix some HostVM parameters in DMLTaimur Hassan2-3/+39
[Why] A number of DML parameters related to HostVM were either missing or being set incorrectly, which may cause inaccuracies in calculating margins and determining BW limitations. [How] Correct these values where needed and populate the missing values. Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdkfd: Free gang_ctx_bo and wptr_bo in pqm_uninitZhenGuo Yin1-21/+33
[Why] Memory leaks of gang_ctx_bo and wptr_bo. [How] Free gang_ctx_bo and wptr_bo in pqm_uninit. v2: add a common function pqm_clean_queue_resource to free queue's resources. v3: reset pdd->pqd.num_gws when destorying GWS queue. Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: ZhenGuo Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdgpu: Update EEPROM I2C address for smu v13_0_0Candice Li1-0/+6
Check smu v13_0_0 SKU type to select EEPROM I2C address. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.1.x
2023-11-29drm/amd/display: Allow DTBCLK disable for DCN35Nicholas Kazlauskas1-15/+12
[Why] DTBCLK is enabled on idle and it will burn power. [How] There's a few issues here: - Always enabling DTBCLK on clock manager init - Setting refclk when DTBCLK is supposed to be disabled - Not applying the correct calculated version refclk, but instead the base value which might be zero On dtbclk_en change we'll message PMFW to enable or disable the clock accordingly. The DTBDTO will be then based on refclk, but it will be set to the default fixed value if there was nothing calculated in DML despite the clock being considered enabled. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdgpu: Fix cat debugfs amdgpu_regs_didt causes kernel null pointerLu Yao1-0/+6
For 'AMDGPU_FAMILY_SI' family cards, in 'si_common_early_init' func, init 'didt_rreg' and 'didt_wreg' to 'NULL'. But in func 'amdgpu_debugfs_regs_didt_read/write', using 'RREG32_DIDT' 'WREG32_DIDT' lacks of relevant judgment. And other 'amdgpu_ip_block_version' that use these two definitions won't be added for 'AMDGPU_FAMILY_SI'. So, add null pointer judgment before calling. Reviewed-by: Christian König <[email protected]> Signed-off-by: Lu Yao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd: Enable PCIe PME from D3Mario Limonciello1-0/+2
When dGPU is put into BOCO it may be in D3cold but still able send PME on display hotplug event. For this to work it must be enabled as wake source from D3. When runpm is enabled use pci_wake_from_d3() to mark wakeup as enabled by default. Cc: [email protected] # 6.1+ Signed-off-by: Mario Limonciello <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/pm: fix a memleak in aldebaran_tables_initDinghao Liu1-1/+4
When kzalloc() for smu_table->ecc_table fails, we should free the previously allocated resources to prevent memleak. Fixes: edd794208555 ("drm/amd/pm: add message smu to get ecc_table v2") Signed-off-by: Dinghao Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdgpu: fix AGP addressing when GART is not at 0Alex Deucher3-6/+11
This worked by luck if the GART aperture ended up at 0. When we ended up moving GART on some chips, the GART aperture ended up offsetting the AGP address since the resource->start is a GART offset, not an MC address. Fix this by moving the AGP address setup into amdgpu_bo_gpu_offset_no_check(). v2: check mem_type before checking agp v3: check if the ttm bo has a ttm_tt allocated yet Fixes: 67318cb84341 ("drm/amdgpu/gmc11: set gart placement GC11") Tested-by: Mario Limonciello <[email protected]> Reported-by: Jesse Zhang <[email protected]> Reported-by: Yifan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] Cc: [email protected]
2023-11-29drm/amd/display: update dcn315 lpddr pstate latencyDmytro Laktyushkin1-4/+4
[WHY/HOW] Increase the pstate latency to improve ac/dc transition Reviewed-by: Charlene Liu <[email protected]> Acked-by: Tom Chung <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: fix ABM disablementHamza Mahfooz1-3/+5
On recent versions of DMUB firmware, if we want to completely disable ABM we have to pass ABM_LEVEL_IMMEDIATE_DISABLE as the requested ABM level to DMUB. Otherwise, LCD eDP displays are unable to reach their maximum brightness levels. So, to fix this whenever the user requests an ABM level of 0 pass ABM_LEVEL_IMMEDIATE_DISABLE to DMUB instead. Also, to keep the user's experience consistent map ABM_LEVEL_IMMEDIATE_DISABLE to 0 when a user tries to read the requested ABM level. Cc: [email protected] # 6.1+ Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Fix black screen on video playback with embedded panelSung Joon Kim2-1/+10
[why] We have dynamic power control in driver but should be ignored when power is forced on. [how] Bypass any power control when it's forced on. Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Fix conversions between bytes and KBTaimur Hassan2-10/+10
[Why] There are a number of instances where we convert HostVMMinPageSize or GPUVMMinPageSize from bytes to KB by dividing (rather than multiplying) and vice versa. Additionally, in some cases, a parameter is passed through DML in KB but later checked as if it were in bytes. Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdkfd: Use common function for IP version checkMukul Joshi1-1/+1
KFD_GC_VERSION was recently updated to use a new function for IP version checks. As a result, use KFD_GC_VERSION as the common function for all IP version checks in KFD. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Remove config updateTaimur Hassan1-1/+1
[Why] Prevent overwrite of dc->config.use_default_clock_table, as it should be pre-configured. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Update DCN35 clock table policyNicholas Kazlauskas1-26/+51
[Why] The new table doesn't have an implicit mapping between Fclk SOC voltage and MemClk and it currently builds the table off of number of Fclk states rather than DcfClock states. The DML table in use is not correct for functionality or power and does not align with our existing policies for DCN3x. [How] Build the table based on DcfClock with the following assumptions: 1. Raising Soc voltage is the most expensive operation, so assume that running at max DispClock or DppClock is preferable. 2. Assume that we can run at max Fclk / MemClk at any state, but restrict the maximum state to the very last entry in the table as the worst case scenario. 3. Assume that Fclk always has a 2x multiplier on DcfClock unless the table specifies something lower. Reviewed-by: Taimur Hassan <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: force toggle rate wa for first link training for a retimerZhongwei1-3/+3
[WHY] Handover from DMUB to driver does not perform link rate toggle. It might cause link training failure for boot up. [HOW] Force toggle rate wa for first link train. link->vendor_specific_lttpr_link_rate_wa should be zero then. Cc: [email protected] # 6.1+ Reviewed-by: Michael Strauss <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Zhongwei <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdgpu: correct the amdgpu runtime dereference usage countPrike Liang1-6/+3
Fix the amdgpu runpm dereference usage count. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2023-11-29drm/amd/display: Update min Z8 residency time to 2100 for DCN314Nicholas Kazlauskas1-1/+1
[Why] Some panels with residency period of 2054 exhibit flickering with Z8 at the end of the frame. [How] As a workaround, increase the limit to block these panels. Cc: [email protected] # 6.1+ Reviewed-by: Syed Hassan <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Remove min_dst_y_next_start check for Z8Nicholas Kazlauskas1-14/+1
[Why] Flickering occurs on DRR supported panels when engaged in DRR due to min_dst_y_next becoming larger than the frame size itself. [How] In general, we should be able to enter Z8 when this is engaged but it might be a net power loss even if the calculation wasn't bugged. Don't support enabling Z8 during the DRR region. Cc: [email protected] # 6.1+ Reviewed-by: Syed Hassan <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/i915/pxp: Add drm_dbgs for critical PXP events.Alan Previn5-6/+23
Debugging PXP issues can't even begin without understanding precedding sequence of important events. Add drm_dbg into the most important PXP events. v5 : - rebase. v4 : - rebase. v3 : - move gt_dbg to after mutex block in function i915_gsc_proxy_component_bind. (Vivaik) v2 : - remove __func__ since drm_dbg covers that (Jani). - add timeout dbg of the restart from front-end (Alan). Signed-off-by: Alan Previn <[email protected]> Reviewed-by: Vivaik Balasubrawmanian <[email protected]> Signed-off-by: John Harrison <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-11-29drm/amdgpu: fix memory overflow in the IB testTim Huang4-7/+7
Fix a memory overflow issue in the gfx IB test for some ASICs. At least 20 bytes are needed for the IB test packet. v2: correct code indentation errors. (Christian) Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2023-11-29drm/amdgpu: add init_registers for nbio v7.11Li Ma3-9/+40
enable init_registers callback func for nbio v7.11. Signed-off-by: Li Ma <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Simplify brightness initializationCamille Cho6-22/+5
[Why] Remove the brightness cache in DC. It uses a single value to represent the brightness for both SDR and HDR mode. This leads to flash in HDR on/off. It also unconditionally programs brightness as in HDR mode. This may introduce garbage on SDR mode in miniLED panel. [How] Simplify the initialization flow by removing the DC cache and taking what panel has as default. Expand the mechanism for PWM to DPCD Aux to restore cached brightness value generally. Cc: [email protected] # 6.1+ Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Camille Cho <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Increase num voltage states to 40Alvin Lee1-1/+1
[Description] If during driver init stage there are greater than 20 intermediary voltage states while constructing the SOC BB we could hit issues because we will index outside of the clock_limits array and start overwriting data. Increase the total number of states to 40 to avoid this issue. Cc: [email protected] # 6.1+ Reviewed-by: Samson Tam <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Do not read DPREFCLK spread info from LUT on DCN35Michael Strauss1-22/+0
[WHY] Currently DCN35 does not spread DPREFCLK [HOW] Remove hardcoded table with nonzero caps Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Use DRAM speed from validation for dummy p-stateAlvin Lee1-1/+2
[Description] When choosing which dummy p-state latency to use, we need to use the DRAM speed from validation. The DRAMSpeed DML variable can change because we use different input params to DML when populating watermarks set B. Cc: [email protected] # 6.1+ Reviewed-by: Samson Tam <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Fix MPCC 1DLUT programmingIlya Bakoulin1-4/+2
[Why] Wrong function is used to translate LUT values to HW format, leading to visible artifacting in some cases. [How] Use the correct cm3_helper function. Cc: [email protected] # 6.1+ Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Feed SR and Z8 watermarks into DML2 for DCN35Nicholas Kazlauskas1-0/+9
[Why] We've updated the table but the values aren't being reflected in DML2 calculation. [How] Pass them into the bbox overrides. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdgpu: Force order between a read and write to the same addressAlex Sierra2-0/+10
Setting register to force ordering to prevent read/write or write/read hazards for un-cached modes. Signed-off-by: Alex Sierra <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.1.x
2023-11-29drm/amdgpu: Do not issue gpu reset from nbio v7_9 bif interruptHawking Zhang1-5/+0
In nbio v7_9, host driver should not issu gpu reset Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Stanley Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amd/display: Add Z8 watermarks for DML2 bbox overridesNicholas Kazlauskas2-15/+34
[Why] We can override SR watermarks but not Z8 ones. [How] Add new parameters for Z8 matching the SR ones and feed them into the states. These also weren't being applied to every state, so make sure that we loop over and update all SOC states if given an override. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-11-29drm/amdgpu: optimize RLC powerdown notification on VangoghPerry Yuan8-3/+43
The smu needs to get the rlc power down message to sync the rlc state with smu, the rlc state updating message need to be sent at while smu begin suspend sequence , otherwise SMU will crash while RLC state is not notified by driver, and rlc state probally changed after that notification, so it needs to notify rlc state to smu at the end of the suspend sequence in amdgpu_device_suspend() that can make sure the rlc state is correctly set to SMU. [ 101.000590] amdgpu 0000:03:00.0: amdgpu: SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x0000001E SMN_C2PMSG_82:0x00000000 [ 101.000598] amdgpu 0000:03:00.0: amdgpu: Failed to disable gfxoff! [ 110.838026] amdgpu 0000:03:00.0: amdgpu: SMU: I'm not done with your previous command: SMN_C2PMSG_66:0x0000001E SMN_C2PMSG_82:0x00000000 [ 110.838035] amdgpu 0000:03:00.0: amdgpu: Failed to disable smu features. [ 110.838039] amdgpu 0000:03:00.0: amdgpu: Fail to disable dpm features! [ 110.838040] [drm:amdgpu_device_ip_suspend_phase2 [amdgpu]] *ERROR* suspend of IP block <smu> failed -62 [ 110.884394] PM: suspend of devices aborted after 21213.620 msecs [ 110.884402] PM: start suspend of devices aborted after 21213.882 msecs [ 110.884405] PM: Some devices failed to suspend, or early wake event detected Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Perry Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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