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2023-12-21drm/xe: Add command MI_LOAD_REGISTER_MEMMichal Wajdeczko2-0/+17
We will need this shortly during context state preparation. Cc: Matt Roper <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Michal Wajdeczko <[email protected]>
2023-12-21drm/xe/dg2: Drop pre-production workaroundsMatt Roper4-207/+5
Pre-production hardware is anything before C0 (for DG2-G10), before B1 (for DG2-G11), or before A1 (for DG2-G12). Workarounds specific to such hardware was already removed from i915 in commit eaeb4b361452 ("drm/i915/dg2: Drop pre-production GT workarounds") and there's even less value keeping these around in the Xe driver. v2: - Drop Wa_14011441408 from xe_mocs.c. (Gustavo) - Drop Wa_14010648519, Wa_14010198302, and Wa_1608949956 which were mis-implemented; they were only supposed to apply to early steppings of DG2-G10, but were being applied unconditionally on all DG2. (Gustavo) - Drop reference to Wa_16011620976; the implementation stays because it still matches Wa_22015475538. (Gustavo) Cc: Gustavo Sousa <[email protected]> Reviewed-by: Gustavo Sousa <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]>
2023-12-26drm/xe: Fix warning on impossible conditionLucas De Marchi1-0/+1
Having a different value for op is not possible: this is already kept out of user-visible warning by the check in xe_wait_user_fence_ioctl() if op > MAX_OP. The warning is useful as if this switch() is not update when a new op is added, it should be triggered. Fix warning as reported by 0-DAY CI Kernel: drivers/gpu/drm/xe/xe_wait_user_fence.c:46:2: warning: variable 'passed' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-26drm/xe: Fix UBSAN splat in add_preempt_fences()Matthew Brost1-0/+3
add_preempt_fences() calls dma_resv_reserve_fences() with num_fences == 0 resulting in the below UBSAN splat. Short circuit add_preempt_fences() if num_fences == 0. [ 58.652241] ================================================================================ [ 58.660736] UBSAN: shift-out-of-bounds in ./include/linux/log2.h:57:13 [ 58.667281] shift exponent 64 is too large for 64-bit type 'long unsigned int' [ 58.674539] CPU: 2 PID: 1170 Comm: xe_gpgpu_fill Not tainted 6.6.0-rc3-guc+ #630 [ 58.674545] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWI1.R00.3243.A01.2006102133 06/10/2020 [ 58.674547] Call Trace: [ 58.674548] <TASK> [ 58.674550] dump_stack_lvl+0x92/0xb0 [ 58.674555] __ubsan_handle_shift_out_of_bounds+0x15a/0x300 [ 58.674559] ? rcu_is_watching+0x12/0x60 [ 58.674564] ? software_resume+0x141/0x210 [ 58.674575] ? new_vma+0x44b/0x600 [xe] [ 58.674606] dma_resv_reserve_fences.cold+0x40/0x66 [ 58.674612] new_vma+0x4b3/0x600 [xe] [ 58.674638] xe_vm_bind_ioctl+0xffd/0x1e00 [xe] [ 58.674663] ? __pfx_xe_vm_bind_ioctl+0x10/0x10 [xe] [ 58.674680] drm_ioctl_kernel+0xc1/0x170 [ 58.674686] ? __pfx_xe_vm_bind_ioctl+0x10/0x10 [xe] [ 58.674703] drm_ioctl+0x247/0x4c0 [ 58.674709] ? find_held_lock+0x2b/0x80 [ 58.674716] __x64_sys_ioctl+0x8c/0xb0 [ 58.674720] do_syscall_64+0x3c/0x90 [ 58.674723] entry_SYSCALL_64_after_hwframe+0x6e/0xd8 [ 58.674727] RIP: 0033:0x7fce4bd1aaff [ 58.674730] Code: 00 48 89 44 24 18 31 c0 48 8d 44 24 60 c7 04 24 10 00 00 00 48 89 44 24 08 48 8d 44 24 20 48 89 44 24 10 b8 10 00 00 00 0f 05 <41> 89 c0 3d 00 f0 ff ff 77 1f 48 8b 44 24 18 64 48 2b 04 25 28 00 [ 58.674731] RSP: 002b:00007ffc57434050 EFLAGS: 00000246 ORIG_RAX: 0000000000000010 [ 58.674734] RAX: ffffffffffffffda RBX: 00007ffc574340e0 RCX: 00007fce4bd1aaff [ 58.674736] RDX: 00007ffc574340e0 RSI: 0000000040886445 RDI: 0000000000000003 [ 58.674737] RBP: 0000000040886445 R08: 0000000000000002 R09: 00007ffc574341b0 [ 58.674739] R10: 000055de43eb3780 R11: 0000000000000246 R12: 00007ffc574340e0 [ 58.674740] R13: 0000000000000003 R14: 00007ffc574341b0 R15: 0000000000000001 [ 58.674747] </TASK> [ 58.674748] ================================================================================ Fixes: dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs") Cc: Lucas De Marchi <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Remove uninitialized variable from warningLucas De Marchi1-2/+2
"err" is not initialized when failing to create and add the freq0 sysfs file. Remove it from the message. This fixes the following warning with clang: ../drivers/gpu/drm/xe/xe_gt_freq.c:202:30: error: variable 'err' is uninitialized when used here [-Werror,-Wuninitialized] kobject_name(gt->sysfs), err); ^~~ Fixes: bef52b5c7a19 ("drm/xe: Create a xe_gt_freq component for raw management and sysfs") Reviewed-by: Michał Winiarski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Remove ci-only GuC FW definitionsDaniele Ceraolo Spurio1-2/+0
As part of the FW definitions, we declare each blob as required via the MODULE_FIRMWARE() macro. This causes the initramfs update (or equivalent process) to look for the blobs on disk when the kernel is installed; therefore, we need to make sure that all FWs we define are available in linux-firmware. We currently don't plan to push the PVC blob to linux-firmware, while the LNL one will only be pushed once we have machines in CI to test it, so we need to remove them from the list for now. Signed-off-by: Daniele Ceraolo Spurio <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Fix build without CONFIG_FAULT_INJECTIONRodrigo Vivi2-2/+2
Ideally this header could be included without the CONFIG_FAULT_INJECTION and it would take care itself for the includes it needs. So, let's temporary workaround this by moving this below and including only when CONFIG_FAULT_INJECTION is selected to avoid build breakages. Another solution would be us including the linux/types.h as well, but this creates unnecessary cases. Reference: https://lore.kernel.org/all/[email protected]/ Cc: Himal Prasad Ghimiray <[email protected]> Cc: Oded Gabbay <[email protected]> Cc: Thomas Hellström <[email protected]> Cc: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Thomas Hellström <[email protected]>
2023-12-21drm/xe/uapi: Remove reset uevent for nowRodrigo Vivi1-18/+0
This kernel uevent is getting removed for now. It will come back later with a better future proof name. v2: Rebase (Francois Dugast) Cc: Himal Prasad Ghimiray <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: Francois Dugast <[email protected]> Cc: Aravind Iddamsetty <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Himal Prasad Ghimiray <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Acked-by: José Roberto de Souza <[email protected]> Acked-by: Mateusz Naklicki <[email protected]> Signed-off-by: Francois Dugast <[email protected]>
2023-12-21drm/xe/uapi: Document the memory_region bitmaskRodrigo Vivi1-0/+19
The uAPI should stay generic in regarding to the bitmask. It is the userspace responsibility to check for the type/class of the memory, without any assumption. Also add comments inside the code to explain how it is actually constructed so we don't accidentally change the assignment of the instance and the masks. No functional change in this patch. It only explains and document the memory_region masks. A further follow-up work with the organization of all memory regions around struct xe_mem_regions is desired, but not part of this patch. Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Acked-by: José Roberto de Souza <[email protected]> Acked-by: Mateusz Naklicki <[email protected]> Signed-off-by: Francois Dugast <[email protected]>
2023-12-21drm/xe/uapi: Remove sync bindsMatthew Brost4-81/+16
Remove concept of async vs sync VM bind queues, rather make all binds async. The following bits have dropped from the uAPI: DRM_XE_ENGINE_CLASS_VM_BIND_ASYNC DRM_XE_ENGINE_CLASS_VM_BIND_SYNC DRM_XE_VM_CREATE_FLAG_ASYNC_DEFAULT DRM_XE_VM_BIND_FLAG_ASYNC To implement sync binds the UMD is expected to use the out-fence interface. v2: Send correct version v3: Drop drm_xe_syncs Cc: Rodrigo Vivi <[email protected]> Cc: Thomas Hellström <[email protected]> Cc: Francois Dugast <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Acked-by: José Roberto de Souza <[email protected]> Acked-by: Mateusz Naklicki <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/uapi: Ensure every uapi struct has drm_xe prefixRodrigo Vivi1-1/+1
To ensure consistency and avoid possible later conflicts, let's add drm_xe prefix to xe_user_extension struct. Cc: Francois Dugast <[email protected]> Suggested-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Acked-by: José Roberto de Souza <[email protected]> Acked-by: Mateusz Naklicki <[email protected]>
2023-12-21drm/xe/pmu: Remove PMU from Xe till uapi is finalizedAshutosh Dixit10-758/+2
PMU uapi is likely to change in the future. Till the uapi is finalized, remove PMU from Xe. PMU can be re-added after uapi is finalized. v2: Include xe_drm.h in xe/tests/xe_dma_buf.c (Francois) Signed-off-by: Ashutosh Dixit <[email protected]> Acked-by: Aravind Iddamsetty <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Reviewed-by: Umesh Nerlige Ramappa <[email protected]> Acked-by: José Roberto de Souza <[email protected]> Acked-by: Mateusz Naklicki <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/uapi: Return correct error code for xe_wait_user_fence_ioctlBommu Krishnaiah4-6/+43
Currently xe_wait_user_fence_ioctl is not checking exec_queue state and blocking until timeout, with this patch wakeup the blocking wait if exec_queue reset happen and returning proper error code Signed-off-by: Bommu Krishnaiah <[email protected]> Cc: Oak Zeng <[email protected]> Cc: Kempczynski Zbigniew <[email protected]> Cc: Matthew Brost <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Acked-by: José Roberto de Souza <[email protected]> Acked-by: Mateusz Naklicki <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/uapi: add exec_queue_id member to drm_xe_wait_user_fence structureBommu Krishnaiah1-63/+2
remove the num_engines/instances members from drm_xe_wait_user_fence structure and add a exec_queue_id member Right now this is only checking if the engine list is sane and nothing else. In the end every operation with this IOCTL is a soft check. So, let's formalize that and only use this IOCTL to wait on the fence. exec_queue_id member will help to user space to get proper error code from kernel while in exec_queue reset Signed-off-by: Bommu Krishnaiah <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]> Acked-by: Matthew Brost <[email protected]> Reviewed-by: Francois Dugast <[email protected]> Acked-by: José Roberto de Souza <[email protected]> Acked-by: Mateusz Naklicki <[email protected]> Signed-off-by: Francois Dugast <[email protected]>
2023-12-21drm/xe: Enable W=1 warnings by defaultLucas De Marchi1-19/+28
Like done in commit 2250c7ead8ad ("drm/i915: enable W=1 warnings by default") for i915, enable W=1 warnings by default in xe. Reviewed-by: Rodrigo Vivi <[email protected]> Acked-by: Jani Nikula <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/display: Fix dummy __i915_inject_probe_error()Lucas De Marchi1-0/+4
When CONFIG_DRM_I915_DEBUG is not set, a dummy __i915_inject_probe_error() is provided on the xe side. Use the same logic as in drivers/gpu/drm/i915/i915_utils.c to ifdef it out. This fixes the build with W=1 and without that config: CC [M] drivers/gpu/drm/xe/display/ext/i915_utils.o ../drivers/gpu/drm/xe/display/ext/i915_utils.c:19:5: error: no previous prototype for ‘__i915_inject_probe_error’ [-Werror=missing-prototypes] 19 | int __i915_inject_probe_error(struct drm_i915_private *i915, int err, | ^~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/bo: Remove unusued variableLucas De Marchi1-4/+0
bo is not used since all the checks are against tbo. Fix warning: ../drivers/gpu/drm/xe/xe_bo.c: In function ‘xe_evict_flags’: ../drivers/gpu/drm/xe/xe_bo.c:250:23: error: variable ‘bo’ set but not used [-Werror=unused-but-set-variable] 250 | struct xe_bo *bo; Signed-off-by: Lucas De Marchi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Return error if drm_buddy_init() failsLucas De Marchi1-0/+2
Fix warning: ../drivers/gpu/drm/xe/xe_ttm_vram_mgr.c: In function ‘__xe_ttm_vram_mgr_init’: ../drivers/gpu/drm/xe/xe_ttm_vram_mgr.c:340:13: error: variable ‘err’ set but not used [-Werror=unused-but-set-variable] 340 | int err; | ^~~ Check for the error return and return it, like done by other drivers. Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Drop some unnecessary header includesMatt Roper6-7/+0
Several files were including register headers that they no longer require. Drop the unnecessary includes to reduce build dependencies. Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Re-sort GT register headerMatt Roper1-38/+38
Keeping the register definitions sorted will make it easy to find existing definitions and prevent accidental introduction of duplicate definitions. v2: - Reorder FUSE3/FUSE4 registers and move GT0_PERF_LIMIT_REASONS / MTL_MEDIA_PERF_LIMIT_REASONS to proper places. (Lucas) Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Define interrupt vector bits with the interrupt registersMatt Roper3-7/+5
The bit definitions had become a bit orphaned; move them to the same location as the interrupt registers that they're used with. Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Move GSC HECI base offsets out of register headerMatt Roper2-4/+4
These offsets are only used to setup the auxiliary device BAR information and are never used for driver read/write operations. Move them to the GSC HECI file where they're actually used. Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Move engine base offsets to engine register headerMatt Roper2-28/+33
These offsets are primarily used as parameters for the engine register definitions, so it makes more sense to define them in the engine header rather than the general register header. Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Fix whitespace in register definitionsMatt Roper2-5/+5
Our register headers use tabs to align the definition values. Convert a few definitions that were using spaces instead. Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Move some per-engine register definitions to the engine headerMatt Roper4-28/+30
Although we only work with the RCS instances today, the FF_SLICE_CS_CHICKEN1[1,2] CS_DEBUG_MODE1, CS_CHICKEN1, and FF_THREAD_MODE registers all have instances on both the RCS and CCS engines. Convert these to parameterized macros and move them to the engine register header. Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Drop "_REG" suffix from CSFE_CHICKEN1Matt Roper2-6/+5
We don't use this suffix on any other registers, and it isn't part of the register's official name either, so drop it for consistency. While at it, move the register definition slightly so that it isn't separating RING_CMD_CCTL's definition from its fields. Reviewed-by: Lucas De Marchi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Support flat ccsHimal Prasad Ghimiray1-1/+1
Enable flat ccs for XE2_GFX_FEATURES. Cc: Thomas Hellström <[email protected]> Signed-off-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Modify xe_bo_test for system memoryHimal Prasad Ghimiray1-17/+27
Modify test to valid ccs clear and copy during evict/restore on igfx. v2: -Vram is associated with tiles not with gt. Use tile based iterator for ccs_test_run_gt. (Matt) Cc: Matt Roper <[email protected]> Cc: Thomas Hellström <[email protected]> Signed-off-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Handle flat ccs move for igfx.Himal Prasad Ghimiray5-42/+66
- Clear flat ccs during user bo creation. - copy ccs meta data between flat ccs and bo during eviction and restore. - Add a bool field ccs_cleared in bo, true means ccs region of bo is already cleared. v2: - Rebase. v3: - Maintain order of xe_bo_move_notify for ttm_bo_type_sg. v4: - xe_migrate_copy can be used to copy src to dst bo on igfx too. Add a bool which handles only ccs metadata copy. v5: - on dgfx ccs should be cleared even if the bo is not compression enabled. Cc: Thomas Hellström <[email protected]> Signed-off-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Update emit_pte to use compression enabled PAT indexHimal Prasad Ghimiray4-7/+18
For indirect accessed buffer use compression enabled PAT index. v2: - Fix parameter name. v3: - use a relevant define instead of fix number. Cc: Thomas Hellström <[email protected]> Cc: Matthew Auld <[email protected]> Signed-off-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Update chunk size for each iteration of ccs copyHimal Prasad Ghimiray1-11/+25
In xe2 platform XY_CTRL_SURF_COPY_BLT can handle ccs copy for max of 1024 main surface pages. v2: - Use better logic to determine chunk size (Matt/Thomas) v3: - use function instead of macro(Thomas) Cc: Matt Roper <[email protected]> Cc: Thomas Hellström <[email protected]> Signed-off-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe_migrate: Use NULL 1G PTE mapped at 255GiB VA for ccs clearHimal Prasad Ghimiray1-54/+11
Get rid of the cleared bo, instead use null 1G PTE mapped at 255GiB offset, this can be used for both dgfx and igfx. v2: - Remove xe_migrate::cleared_bo. - Add a comment for NULL mapping.(Thomas) Cc: Thomas Hellström <[email protected]> Signed-off-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Updates on XY_CTRL_SURF_COPY_BLTHimal Prasad Ghimiray2-9/+17
- The XY_CTRL_SURF_COPY_BLT instruction operating on ccs data expects size in pages of main memory for which CCS data should be copied. - The bitfield representing copy size in XY_CTRL_SURF_COPY_BLT has shifted one bit higher in the instruction. v2: - Fix the num_pages for ccs size calculation. - Address nits (Thomas) v3: - Use FIELD_PREP and FIELD_FIT instead of shifts and numbers.(Matt) Cc: Matt Roper <[email protected]> Cc: Thomas Hellström <[email protected]> Signed-off-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Allocate extra pages for ccs during bo createHimal Prasad Ghimiray1-9/+14
Incase of bo move from PL_TT to PL_SYSTEM these pages will be used to store ccs metadata from flat ccs. And during bo move to PL_TT from PL_SYSTEM the metadata will be copied from extra pages to flat ccs. This copy of ccs metadata ensures ccs remains unaltered between swapping out of bo to disk and its restore to PL_TT. Bspec:58796 v2: - For dgfx ensure system bit is not set. - Modify comments.(Thomas) v3: - Separate out patch to modify main memory to ccs memory ratio.(Matt) v4: - Update description for commit message. - Make bo allocation routine more readable.(Matt) Cc: Matt Roper <[email protected]> Cc: Thomas Hellström <[email protected]> Signed-off-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Modify main memory to ccs memory ratio.Himal Prasad Ghimiray2-2/+2
On xe2 platforms each byte of CCS data now represents 512 bytes of main memory data. Cc: Matt Roper <[email protected]> Cc: Thomas Hellström <[email protected]> Signed-off-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe/xe2: Determine bios enablement for flat ccs on igfxHimal Prasad Ghimiray2-0/+33
If bios disables flat ccs on igfx make has_flat_ccs as 0 and notify via drm_dbg. Bspec:59255 v2: - Release forcewake. - Add registers in order. - drop dgfx condition and only add it back in the future when the support for an Xe2 dgpu will be added. - Use drm_dbg instead of drm_info. (Matt) v3: - Address nit(Matt) Cc: Matt Roper <[email protected]> Cc: Thomas Hellström <[email protected]> Signed-off-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Matt Roper <[email protected]> Acked-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Remove duplicate RING_MAX_NONPRIV_SLOTS definitionMatt Roper1-1/+0
The engine register header wound up with two definitions for RING_MAX_NONPRIV_SLOTS, likely due to a rebase mistake. Keep the definition that's in an appropriate place (i.e., with the FORCE_TO_NONPRIV register definition) and remove the other. Reviewed-by: Matthew Brost <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Allow num_batch_buffer / num_binds == 0 in IOCTLsMatthew Brost9-28/+206
The idea being out-syncs can signal indicating all previous operations on the bind queue are complete. An example use case of this would be support for implementing vkQueueWaitIdle easily. All in-syncs are waited on before signaling out-syncs. This is implemented by forming a composite software fence of in-syncs and installing this fence in the out-syncs and exec queue last fence slot. The last fence must be added as a dependency for jobs on user exec queues as it is possible for the last fence to be a composite software fence (unordered, ioctl with zero bb or binds) rather than hardware fence (ordered, previous job on queue). Cc: Thomas Hellström <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Remove vram size info from sysfsRodrigo Vivi1-22/+1
This information is already part of the query IOCTL. Let's not duplicate it here in the sysfs. Cc: Matt Roper <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Use a flags field instead of bools for sync parseMatthew Brost4-6/+13
Use a flags field instead of severval bools for sync parse as it is easier to read and less bug prone. v2: Pull in header change from subsequent patch Suggested-by: Thomas Hellström <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Use a flags field instead of bools for VMA createMatthew Brost1-30/+34
Use a flags field instead of severval bools for VMA create as it is easier to read and less bug prone. Suggested-by: Thomas Hellström <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: Thomas Hellström <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Use DRM_GPUVM_RESV_PROTECTED for gpuvmThomas Hellström1-2/+2
Use DRM_GPUVM_RESV_PROTECTED to use corse-grained locking for the evict and external object list. Since we are already holding the relevant RESV locks, for now at least, we don't need the fine-grained locking. Signed-off-by: Thomas Hellström <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Use DRM GPUVM helpers for external- and evicted objectsThomas Hellström5-386/+129
Adapt to the DRM_GPUVM helpers moving removing a lot of complicated driver-specific code. For now this uses fine-grained locking for the evict list and external object list, which may incur a slight performance penalty in some situations. v2: - Don't lock all bos and validate on LR exec submissions (Matthew Brost) - Add some kerneldoc Signed-off-by: Thomas Hellström <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Acked-by: Matthew Brost <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Fix lockdep warning in xe_force_wake callsAravind Iddamsetty1-4/+6
Use spin_lock_irqsave, spin_unlock_irqrestore Fix for below: [13994.811263] ======================================================== [13994.811295] WARNING: possible irq lock inversion dependency detected [13994.811326] 6.6.0-rc3-xe #2 Tainted: G U [13994.811358] -------------------------------------------------------- [13994.811388] swapper/0/0 just changed the state of lock: [13994.811416] ffff895c7e044db8 (&cpuctx_lock){-...}-{2:2}, at: __perf_event_read+0xb7/0x3a0 [13994.811494] but this lock took another, HARDIRQ-unsafe lock in the past: [13994.811528] (&fw->lock){+.+.}-{2:2} [13994.811544] and interrupts could create inverse lock ordering between them. [13994.811606] other info that might help us debug this: [13994.811636] Possible interrupt unsafe locking scenario: [13994.811667] CPU0 CPU1 [13994.811691] ---- ---- [13994.811715] lock(&fw->lock); [13994.811744] local_irq_disable(); [13994.811773] lock(&cpuctx_lock); [13994.811810] lock(&fw->lock); [13994.811846] <Interrupt> [13994.811865] lock(&cpuctx_lock); [13994.811895] *** DEADLOCK *** v2: Use spin_lock in atomic context and spin_lock_irq in a non atomic context (Matthew Brost) v3: just use spin_lock_irqsave/restore Cc: Matthew Brost <[email protected]> Cc: Anshuman Gupta <[email protected]> Cc: Ville Syrjala <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Aravind Iddamsetty <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Check skip_guc_pc before disabling gucrcVinay Belgaumkar1-3/+5
Also, use the new C6 helper instead of duplicating that code. v2: Check skip flag at the beginning of the function (Rodrigo) Fixes: 975e4a3795d4 ("drm/xe: Manually setup C6 when skip_guc_pc is set") Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Vinay Belgaumkar <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Use NULL PTEs as scratch PTEsThomas Hellström5-72/+74
Currently scratch PTEs are write-enabled and points to a single scratch page. This has the side effect that buggy applications with out-of-bounds memory accesses may not notice the bad access since what's written may be read back. Instead use NULL PTEs as scratch PTEs. These always return 0 when reading, and writing has no effect. As a slight benefit, we can also use huge NULL PTEs. One drawback pointed out is that debugging may be hampered since previously when inspecting the content of the scratch page, it might be possible to detect writes to out-of-bound addresses and possibly also from where the out-of-bounds address originated. However since the scratch page-table structure is kept, it will be easy to add back the single RW-enabled scratch page under a debug define if needed. Also update the kerneldoc accordingly and move the function to create the scratch page-tables from xe_pt.c to xe_pt.h since it is accessing vm structure internals and this also makes it possible to make it static. v2: - Don't try to encode scratch PTEs larger than 1GiB. - Move xe_pt_create_scratch(), Update kerneldoc. v3: - Rebase. Cc: Brian Welty <[email protected]> Cc: Matt Roper <[email protected]> Signed-off-by: Thomas Hellström <[email protected]> Acked-by: Lucas De Marchi <[email protected]> #for general direction. Reviewed-by: Brian Welty <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Restrict huge PTEs to 1GiBThomas Hellström3-1/+7
Add a define for the highest level for which we can encode a huge PTE, and use it for page-table building. Also update an assert that checks that we don't try to encode for larger sizes. Signed-off-by: Thomas Hellström <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Reviewed-by: Brian Welty <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Add frequency throttle reasons sysfs attributesSujaritha Sundaresan5-0/+283
Add throttle reasons sysfs attributes under a separate directory. /device/tile<n>/gt<n>/freq0/throttle |- reason_pl1 |- reason_pl2 |- reason_pl4 |- reason_prochot |- reason_ratl |- reason_vr_tdc |- reason_vr_thermalert |- status v2: Remove unnecessary headers and clean-up action (Riana) Signed-off-by: Sujaritha Sundaresan <[email protected]> Reviewed-by: Riana Tauro <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Create a xe_gt_freq component for raw management and sysfsRodrigo Vivi7-104/+347
Goals of this new xe_gt_freq component: 1. Detach sysfs controls and raw freq management from GuC SLPC. 2. Create a directory that could later be aligned with devfreq. 3. Encapsulate all the freq control in a single directory. Although we only have one freq domain per GT, already start with a numbered freq0 directory so it could be expanded in the future if multiple domains or PLL are needed. Note: Although in the goal #1, the raw freq management control is mentioned, this patch only starts by the sysfs control. The RP freq configuration and init freq selection are still under the guc_pc, but should be moved to this component in a follow-up patch. v2: - Add /tile# to the doc and remove unnecessary kobject_put (Riana) - s/ssize_t/int on some ret variables (Vinay) Cc: Sujaritha Sundaresan <[email protected]> Cc: Vinay Belgaumkar <[email protected]> Cc: Riana Tauro <[email protected]> Reviewed-by: Vinay Belgaumkar <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
2023-12-21drm/xe: Change the name of frequency sysfs attributesSujaritha Sundaresan1-30/+30
Switching the names of frequency sysfs attrbutes to align with required devfreq changes. The name changes are as below; -freq_act -> act_freq -freq_cur -> cur_freq -freq_rpn -> rpn_freq -freq_rpe -> rpe_freq -freq_rp0 -> rp0_freq -freq_min -> min_freq -freq_max -> max_freq Signed-off-by: Sujaritha Sundaresan <[email protected]> Reviewed-by: Riana Tauro <[email protected]> Signed-off-by: Rodrigo Vivi <[email protected]>
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