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2024-04-09drm/amd/display: Add OTG check for set AV muteLeo (Hanghong) Ma1-1/+1
[Why && How] OTG can be disabled before setting dpms on. Add check to skip wait when setting AV mute if OTG is disabled. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Leo (Hanghong) Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Skip on writeback when it's not applicableAlex Hung1-1/+8
[WHY] dynamic memory safety error detector (KASAN) catches and generates error messages "BUG: KASAN: slab-out-of-bounds" as writeback connector does not support certain features which are not initialized. [HOW] Skip them when connector type is DRM_MODE_CONNECTOR_WRITEBACK. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3199 Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Allow HPO PG for DCN35Duncan Ma1-1/+1
[Why] HPO can be power gated unconditionally for DCN35. [How] Set disable flag to false. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Enable RCO for HDMISTREAMCLK in DCN35Daniel Miess2-2/+13
[Why & How] Enable root clock optimization for HDMISTREAMCLK and only disable it when it's actively being used. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Add dummy interface for tracing DCN32 SMU messagesGeorge Shen4-1/+31
[Why/How] Some issues may require a trace of the previous SMU messages from DC to understand the context and aid in debugging. Actual logging to be implemented when needed. Reviewed-by: Josip Pavic <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Enable DTBCLK DTO earlier in the sequenceSung Joon Kim1-16/+16
[why] As per programming guide, we need to enable the virtual pixel clock via DTBCLK DTO and ungate the clock before we begin programming OPP/OPTC control registers. Otherwise, the double-buffered registers will be left pending until the clocks are enabled. [how] Move the DTBCLK DTO programming up to where we do the legacy DP DTO programming. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: update pipe topology log to support subvpWenjing Liu1-31/+65
[why] There is an ambiguity in subvp pipe topology log. The log doesn't show subvp relation to main stream and it is not clear that certain stream is an internal stream for subvp pipes. [how] Separate subvp pipe topology logging from main pipe topology. Log main stream indices instead of the internal stream for subvp pipes. The following is a sample log showing 2 streams with subvp enabled on both: pipe topology update ________________________ | plane0 slice0 stream0| |DPP1----OPP1----OTG1----| | plane0 slice0 stream1| |DPP0----OPP0----OTG0----| | (phantom pipes) | | plane0 slice0 stream0| |DPP3----OPP3----OTG3----| | plane0 slice0 stream1| |DPP2----OPP2----OTG2----| |________________________| Reviewed-by: Alvin Lee <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Add dmub additional interface support for FAMSDillon Varone5-5/+9
[WHY&HOW] Update dmub and driver interface for future FAMS revisions. Reviewed-by: Anthony Koo <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: use vm_update_mode=0 as default in sriov for gfx10.3 onwardsDanijel Slivka2-6/+7
Apply this rule to all newer asics in sriov case. For asic with VF MMIO access protection avoid using CPU for VM table updates. CPU pagetable updates have issues with HDP flush as VF MMIO access protection blocks write to BIF_BX_DEV0_EPF0_VF0_HDP_MEM_COHERENCY_FLUSH_CNTL register during sriov runtime. Moved the check to amdgpu_device_init() to ensure it is done after amdgpu_device_ip_early_init() where the IP versions are discovered. Signed-off-by: Danijel Slivka <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/amdgpu: add pipe1 hardware supportArunpravin Paneer Selvam1-1/+1
Enable pipe1 support starting from SIENNA CICHLID asic Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2117 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Arunpravin Paneer Selvam <[email protected]> Signed-off-by: ZhenGuo Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: select HDP ref/mask according to gfx ring pipeZhenGuo Yin1-1/+1
Use correct ref/mask for differnent gfx ring pipe. This should fix the gfx hang issue after enabling gfx pipe1. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2117 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: ZhenGuo Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: handle invalid connector indicesJoshua Aberback8-8/+10
[Why] The function to count the number of valid connectors does not guarantee that the first n indices are valid, only that there exist n valid indices. When invalid indices are present, this results in later valid connectors being missed, as processing would end after checking n indices. [How] - count valid indices separately from total indices examined - add explicit definition of MAX_LINKS Reviewed-by: Dillon Varone <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: FEC overhead should be checked once for mst slot numsHersen Wu2-30/+10
[Why] Mst slot nums equals to pbn / pbn_div. Today, pbn_div refers to dm_mst_get_pbn_divider -> dc_link_bandwidth_kbps. In dp_link_bandwidth_kbps, which includes effect of FEC overhead already. As result, we should not include effect of FEC overhead again while calculating pbn by kpbs_to_peak_pbn (stream_kbps). [How] Include FEC overhead within dp_link_bandwidth_kbps. Remove FEC overhead from kbps_to_peak_pbn. Reviewed-by: Wayne Lin <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: implement IRQ_STATE_ENABLE for SDMA v4.4.2Tao Zhou1-13/+3
SDMA_CNTL is not set in some cases, driver configures it by itself. v2: simplify code Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Expand supported Replay residency modeLeon Huang3-4/+7
[Why] Dmub provides several Replay residency calculation methods, but current interface only supports either ALPM or PHY mode [How] Modify the interface for supporting different types of Replay residency calculation. Reviewed-by: Robin Chen <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Leon Huang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Toggle additional RCO options in DCN35Daniel Miess10-14/+314
[Why] With root clock optimization now enabled for DCN35 there are still RCO registers still not being toggled [How] Add in logic to toggle RCO registers for DPPCLK, DPSTREAMCLK and DSCCLK Reviewed-by: Charlene Liu <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: optimize dml2 pipe resource allocation orderWenjing Liu4-44/+97
[why] There could be cases that we are transition from MPC to ODM combine. In this case if we map pipes before unmapping MPC pipes, we might temporarly run out of pipes. The change reorders pipe resource allocation. So we unmapping pipes before mapping new pipes. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: fix underflow in some two display subvp/non-subvp configsSamson Tam2-130/+199
[Why] In two display configuration, switching between subvp and non-subvp may cause underflow because it moves an existing pipe between displays [How] Create helper function for applying pipe split flags Apply pipe split flags prior to deciding on subvp During subvp check, do not merge pipes, so it can retain previous pipe configuration Add check for prev odm pipe in subvp check For single display subvp case, use same odm policy for phantom pipes as main subvp pipe Reviewed-by: Alvin Lee <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Samson Tam <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Add timing pixel encoding for mst mode validationHersen Wu1-5/+30
[Why] Mode pbn is not calculated correctly because timing pixel encoding is not checked within convert_dc_color_depth_into_bpc. [How] Get mode kbps from dc_bandwidth_in_kbps_from_timing, then calculate pbn by kbps_to_peak_pbn. Reviewed-by: Wayne Lin <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: Fix compiler redefinition warnings for certain configsMounika Adhuri2-4/+4
[why & how] Modified definitions of 1 function and 2 structs to remove warnings on certain specific compiler configurations due to redefinition. Reviewed-by: Martin Leung <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: add smu 14.0.1 discovery supportYifan Zhang1-0/+1
This patch to add smu 14.0.1 support Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/swsmu: Update smu v14.0.0 headers to be 14.0.1 compatiblelima10026-43/+413
update ppsmc.h pmfw.h and driver_if.h for smu v14_0_1 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: lima1002 <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu : Increase the mes log buffer size as per new MES FW versionshaoyunl2-3/+3
From MES version 0x54, the log entry increased and require the log buffer size to be increased. The 16k is maximum size agreed Signed-off-by: shaoyunl <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu : Add mes_log_enable to control mes log featureshaoyunl4-3/+20
The MES log might slow down the performance for extra step of log the data, disable it by default and introduce a parameter can enable it when necessary Signed-off-by: shaoyunl <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11Tim Huang1-1/+11
While doing multiple S4 stress tests, GC/RLC/PMFW get into an invalid state resulting into hard hangs. Adding a GFX reset as workaround just before sending the MP1_UNLOAD message avoids this failure. Signed-off-by: Tim Huang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: refine function signature of amdgpu_aca_get_error_data()Yang Wang2-6/+8
refine function signature of amdgpu_aca_get_error_data(); Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: add DCN 351 version for microcode loadLi Ma1-1/+6
There is a new DCN veriosn 3.5.1 need to load Signed-off-by: Li Ma <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: Reset dGPU if suspend got abortedLijo Lazar1-0/+25
For SOC21 ASICs, there is an issue in re-enabling PM features if a suspend got aborted. In such cases, reset the device during resume phase. This is a workaround till a proper solution is finalized. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2024-04-09drm/amdgpu: add IP's FW information to devcoredumpSunil Khatri1-0/+129
Add FW information of all the IP's in the devcoredump. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu/umsch: reinitialize write pointer in hw initLang Yu1-0/+2
Otherwise the old one will be used during GPU reset. That's not expected. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: Refine IB schedule error loggingLijo Lazar1-2/+5
Downgrade to debug information when IBs are skipped. Also, use dev_* to identify the device. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: make amdgpu device attr_update() function more efficientYang Wang2-2/+43
v1: add a new enumeration type to identify device attribute node, this method is relatively more efficient compared with 'strcmp' in update_attr() function. v2: rename device_attr_type to device_attr_id. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Ma Jun <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/xe/xe2hpm: Add initial set of workaroundsGustavo Sousa2-0/+36
Define the initial set of workarounds for Xe2_HPM. Signed-off-by: Gustavo Sousa <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2hpg: Introduce performance tuning changes for Xe2_HPG.Shekhar Chauhan1-3/+3
Introduces performance tuning guide changes for Xe_HPG. v2: Switched to open upper bound for "Tuning: L3 Cache" setting. BSpec: 72161 Signed-off-by: Shekhar Chauhan <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2hpg: Add initial GT workaroundsHaridhar Kalvala2-2/+70
Add the initial set of Xe2_HPG gt/engine/lrc workarounds. v2: Removed WA_16020183090 which is no more applicable Extended WA_18033852989,18034896535 also to xe2hpg Signed-off-by: Haridhar Kalvala <[email protected]> Signed-off-by: Clint Taylor <[email protected]> Signed-off-by: Gustavo Sousa <[email protected]> Signed-off-by: Dnyaneshar Bhadane <[email protected]> Signed-off-by: Shekhar Chauhan <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2: Add workaround 18034896535Bommu Krishnaiah1-0/+5
Add 18034896535 as driver permanent workaround. v2: 18034896535 and 16021540221 are two independent workarounds that just happen to have the same implementation, hence keeping it. Signed-off-by: Bommu Krishnaiah <[email protected]> Reviewed-by: Tejas Upadhyay <[email protected]> Cc: Tejas Upadhyay <[email protected]> Cc: Matt Roper <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2hpg: Remove extra allocation of CCS pages for dgfxAkshata Jahagirdar1-0/+3
On Xe2 dGPU, compression is only supported with VRAM. When copying from VRAM -> system memory the KMD uses mapping with uncompressed PAT so the copy in system memory is guaranteed to be uncompressed. When restoring such buffers from system memory -> VRAM the KMD can't easily know which pages were originally compressed, so we always use uncompressed -> uncompressed here. so this means that there's no need for extra CCS storage on such platforms. v2: More description added to commit message Signed-off-by: Akshata Jahagirdar <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2hpg: Determine flat ccs offset for vramHimal Prasad Ghimiray2-2/+42
on Xe2 dgfx platform determine the offset using Flat CCS size bitfield of XE2_FLAT_CCS_BASE_RANGE_[UPPER/LOWER] mcr registers. v2: function argument tile_size changed from pass by reference to pass by value Bspec: 68023 Signed-off-by: Himal Prasad Ghimiray <[email protected]> Signed-off-by: Akshata Jahagirdar <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/bmg: Program an additional discrete-specific PAT settingMatt Roper1-0/+7
Discrete Xe2 platforms require programming of one additional row of PAT settings which controls the access characteristics for PPGTT and LMTT page tables. Integrated GPUs do not need this programming and will leave the register at its hardware default value. Bspec: 71582 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Himal Prasad Ghimiray <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/bmg: Add BMG mocs tableBalasubramani Vivekanandan1-0/+1
BMG uses the same MOCS table as LNL. Bpsec: 71582 CC: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/bmg: Add BMG platform definitionMatt Roper3-0/+8
BMG is a discrete GPU based on the Xe2 architecture. No device ids are bound to the BMG platform descriptor yet. BMG device ids will be added once we have all the basic required platform enabling patches landed. v2: Removed device ids, deferring it to a later patch v3: Squash in compat header IS_BATTLEMAGE() patch. (Lucas) Bspec: 68090 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2: Recognize Xe2_HPM IPMatt Roper1-1/+2
Xe2_HPM uses the same general feature flags as Xe2_LPM. Xe2_HPM is identified as version 13.01 in the GMD_ID register. Bspec: 68090, 67163 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2: Recognize Xe2_HPG IPMatt Roper1-1/+2
Xe2_HPG uses the same general feature flags as Xe2_LPG. Xe2_HPG is identified as version 20.01 in the GMD_ID register. Bspec: 68090 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/vmwgfx: Enable DMA mappings with SEVZack Rusin1-5/+6
Enable DMA mappings in vmwgfx after TTM has been fixed in commit 3bf3710e3718 ("drm/ttm: Add a generic TTM memcpy move for page-based iomem") This enables full guest-backed memory support and in particular allows usage of screen targets as the presentation mechanism. Signed-off-by: Zack Rusin <[email protected]> Reported-by: Ye Li <[email protected]> Tested-by: Ye Li <[email protected]> Fixes: 3b0d6458c705 ("drm/vmwgfx: Refuse DMA operation when SEV encryption is active") Cc: Broadcom internal kernel review list <[email protected]> Cc: [email protected] Cc: <[email protected]> # v6.6+ Reviewed-by: Martin Krastev <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/hwmon: Cast result to output precision on left shift of operandKarthik Poosa1-2/+2
Address potential overflow in result of left shift of a lower precision (u32) operand before assignment to higher precision (u64) variable. v2: - Update commit message. (Himal) Fixes: 4446fcf220ce ("drm/xe/hwmon: Expose power1_max_interval") Signed-off-by: Karthik Poosa <[email protected]> Reviewed-by: Anshuman Gupta <[email protected]> Cc: Badal Nilawar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-09drm/xe/hwmon: Update xe_hwmon_get_reg to return struct xe_regKarthik Poosa1-21/+26
Return struct xe_reg instead of reg.raw from xe_hwmon_get_reg to have abstracted usage of struct xe_reg. v2: - Use xe_reg_is_valid function instead of XE_REG_IS_VALID macro as it is removed. Signed-off-by: Karthik Poosa <[email protected]> Suggested-by: Lucas De Marchi <[email protected]> Cc: Badal Nilawar <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-09drm/xe: Define xe_reg_is_validKarthik Poosa1-0/+5
Add a function to check if struct xe_reg has valid address. v2: - Rebase. - Make xe_reg_is_valid as inline function instead of a macro. (Badal). - Update commit msg. Signed-off-by: Karthik Poosa <[email protected]> Suggested-by: Lucas De Marchi <[email protected]> Cc: Badal Nilawar <[email protected]> Reviewed-by: Badal Nilawar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-09drm/i915: Introduce intel_crtc_joined_pipe_mask()Ville Syrjälä3-6/+13
Add a small helper to compute the set of pipes that the current crtc is using. And we have at least one trivial place in intel_ddi_update_active_dpll() where we can use it immediately, so let's do that. v2: Use the name 'pipe_crtc' for the per-pipe crtc pointer Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Arun R Murthy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/i915: Pass connector to intel_dp_need_bigjoiner()Ville Syrjälä3-6/+10
Pass the connector explicitly to intel_dp_need_bigjoiner() so that it'll actually check the correct place for the bigjoiner force flag. Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/i915/mst: Check intel_dp_joiner_needs_dsc()Ville Syrjälä1-4/+6
intel_dp_mst_compute_config() is missing the "does the joiner need DSC?" check despite claiming to have a lot of other joiner/dsc stuff in there (albeit disabled). Replicate the logic from the SST side. TODO: refactor all this duplicated code! Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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