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2024-04-30drm/amd/display: Separate setting and programming of cursorHarry Wentland5-33/+72
We're seeing issues when user-space tries to do an atomic update of the primary surface, as well as the cursor. These two updates are separate calls into DC and don't currently act as an atomic update. This might lead to cursor updates being locked out and cursors stuttering. In order to solve this problem we want to separate the setting and programming of cursor attributes and position. That's what we're doing in this patch. The subsequent patch will then be able to use the cursor setters in independent cursor updates, as well as in atomic commits. Reviewed-by: Agustin Gutierrez <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30Revert "drm/amd/display: Fix incorrect pointer assignment"Joshua Aberback1-5/+5
This reverts commit 0a571e8657c40047e6602466abfcb6514a391041. [Why] The change being reverted incorrectly assumes that a pointer type was intended, however copying to a new structure is correct. As well, there is no compiler error, it was instead an error in the testing framework being used. Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Add condition for dp_set_dsc_config callIlya Bakoulin1-7/+9
Not every ASIC implements dp_set_dsc_config. Add condition to prevent calls to unimplemented function. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Allocate zero bw after bw alloc enableMeenakshikumar Somasundaram1-1/+9
[Why] During DP tunnel creation, CM preallocates BW and reduces estimated BW of other DPIA. CM release preallocation only when allocation is complete. Display mode validation logic validates timings based on bw available per host router. In multi display setup, this causes bw allocation failure when allocation greater than estimated bw. [How] Do zero alloc to make the CM to release preallocation and update estimated BW correctly for all DPIAs per host router. Reviewed-by: PeiChen Huang <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Fix incorrect DSC instance for MSTHersen Wu1-12/+36
[Why] DSC debugfs, such as dp_dsc_clock_en_read, use aconnector->dc_link to find pipe_ctx for display. Displays connected to MST hub share the same dc_link. DSC instance is from pipe_ctx. This causes incorrect DSC instance for display connected to MST hub. [How] Add aconnector->sink check to find pipe_ctx. CC: [email protected] Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amdgpu: Add soc24 common ip block (v2)Hawking Zhang3-1/+561
Add initial soc24 support. v1: Add soc24 common ip block. v2: Switch to new select_se_sh/enter_safe_mode interface. v3: squash in correct ext rev id, etc. (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Force flush after write to IPS driver signalsNicholas Kazlauskas2-0/+3
[Why] It's possible that the write hasn't fully completed by the time we send (and flush) a command to DMCUB to notify idle to request IPS2 exit. [How] Perform a readback of the volatile structure into dc_dmub_srv state. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Block FPO According to Luminance DeltaEthan Bitnun5-2/+274
[Description] - Block FPO if the max stretch refresh rate is low enough to cause a flicker by storing the maximum safe refresh decrease from nominal in stream. - Brought over various Freesync Luminance functions to dc. Use these new functions to block fpo if we will flicker. - Generalized increase/reduce dependent functions to reduce code clutter and allow for easier use. - Added a debug option to enable the feature. Disabled by default. Co-authored-by: Ethan Bitnun <[email protected]> Reviewed-by: Dillon Varone <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Ethan Bitnun <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amdgpu: Add soc24 chip enum definitions (v4)Hawking Zhang1-0/+21073
Add enum definitions for soc24. v2: Updates (Alex) v3: Updates (Alex) v4: Fix clash with display code (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amdgpu: Add gc v12_0_0 ip headers (v4)Hawking Zhang2-0/+51505
v1: Add gc v12_0_0 register offset and shift masks header files. (Hawking) v2: Update gc v12_0_0 register offset and shift masks header files to LSD version. (Likun) v3: Update gc v12_0_0 register offset and shift masks header files to RE3 version. (Likun) v4: Updates (Alex) v5: updates (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Skip SST ACT polling when sink_count is 0George Shen1-2/+4
[Why] Upon disconnecting a UHBR SST display, the disconnection and the SetTimings to disable the display can occur such that link_set_dpms_off occurs after the disconnection has already processed (link->type is dc_connection_none). Thus, the AUX related operations should be skipped when clearing the payload allocation table. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Atom Integrated System Info v2_2 for DCN35Gabe Teeger1-0/+1
New request from KMD/VBIOS in order to support new UMA carveout model. This fixes a null dereference from accessing Ctx->dc_bios->integrated_info while it was NULL. DAL parses through the BIOS and extracts the necessary integrated_info but was missing a case for the new BIOS version 2.3. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Add delay to improve LTTPR UHBR interopMichael Strauss1-0/+5
[WHY] Avoid race condition which puts LTTPR into bad state during UHBR LT. [HOW] Delay 30ms between starting UHBR TPS1 PHY output and sending TPS1 via DPCD. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Handle HPD_IRQ for internal linkSung-huai Wang1-9/+16
[Why] TCON data is corrupted after electro static discharge test. Once the TCON data get corrupted, they will get themselves reset and send HPD_IRQ to source side. [How] Support HPD_IRQ for internal link, and restore the PSR/Replay setup. Reviewed-by: Robin Chen <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Sung-huai Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Reuse the modified power sequenceSung Joon Kim1-4/+4
[why & how] Need to update the function pointers that perform the power up and down sequence to reuse the modified sequence as a requirement. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Add dtbclk access to dcn315Swapnil Patel1-0/+8
[Why & How] Currently DCN315 clk manager is missing code to enable/disable dtbclk. Because of this, "optimized_required" flag is constantly set and this prevents FreeSync from engaging for certain high bandwidth display Modes which require DTBCLK. Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Swapnil Patel <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Add null check in resource_log_pipe_topology_updateNatanel Roizenman1-0/+4
[WHY] When switching from "Extend" to "Second Display Only" we sometimes call resource_get_otg_master_for_stream on a stream for the eDP, which is disconnected. This leads to a null pointer dereference. [HOW] Added a null check in dc_resource.c/resource_log_pipe_topology_update. CC: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Natanel Roizenman <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Fix Replay Desync Error TestDennis Chan1-0/+1
When PHY power off, the DP_SEC_CNTL cannot be configured and cause disable Adaptive sync SDP failed. Regarding the issue, the driver will disabled AS-SDP in replay state machine. Reviewed-by: ChunTao Tso <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Dennis Chan <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Drop unnecessary semicolonRodrigo Siqueira1-2/+1
Drop unnecessary semicolon that can create a problem of double semicolon in some compilers. Reviewed-by: Martin Leung <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Add missing IRQ typesRodrigo Siqueira1-0/+8
This commit add some DPCX IRQ types. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Ensure that dmcub support flag is set for DCN20Rodrigo Siqueira1-0/+1
In the DCN20 resource initialization, ensure that DMCUB support starts configured as true. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amd/display: Update comments in DCRodrigo Siqueira5-5/+15
This commit adds, updates, and removes some of the comments used in the DC code. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amdgpu: Support contiguous VRAM allocationPhilip Yang1-0/+4
RDMA device with limited scatter-gather ability requires contiguous VRAM buffer allocation for RDMA peer direct support. Add a new KFD alloc memory flag and store as bo alloc flag AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS. When pin this bo to export for RDMA peerdirect access, this will set TTM_PL_FLAG_CONTIFUOUS flag, and ask VRAM buddy allocator to get contiguous VRAM. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/amdgpu: Fix uninitialized variable warning in amdgpu_afmt_acrMa Jun1-0/+1
Assign value to clock to fix the warning below: "Using uninitialized value res. Field res.clock is uninitialized" Signed-off-by: Ma Jun <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-30drm/xe: Remove uninitialized end var from xe_gt_tlb_invalidation_range()Nirmoy Das1-1/+1
This fixes commit c4f18703629d ("drm/xe: Add xe_gt_tlb_invalidation_range and convert PT layer to use this") which added the end variable as part of the function param. v2: Add fixes tag(Matt) Fixes: c4f18703629d ("drm/xe: Add xe_gt_tlb_invalidation_range and convert PT layer to use this") Cc: Matthew Brost <[email protected]> Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-30drm/i915/gt: Automate CCS Mode setting during engine resetsAndi Shyti3-5/+7
We missed setting the CCS mode during resume and engine resets. Create a workaround to be added in the engine's workaround list. This workaround sets the XEHP_CCS_MODE value at every reset. The issue can be reproduced by running: $ clpeak --kernel-latency Without resetting the CCS mode, we encounter a fence timeout: Fence expiration time out i915-0000:03:00.0:clpeak[2387]:2! Fixes: 2bebae0112b1 ("drm/i915/gt: Enable only one CCS for compute workload") Reported-by: Gnattu OC <[email protected]> Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895 Signed-off-by: Andi Shyti <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Matt Roper <[email protected]> Cc: <[email protected]> # v6.2+ Tested-by: Gnattu OC <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Tested-by: Krzysztof Gibala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C22Jani Nikula2-3/+3
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_WGC_C22 register macro. Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/0a07f615c574040094b37c861078e41daf53c706.1714399071.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C21_C20Jani Nikula2-3/+3
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_WGC_C21_C20 register macro. Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/af39047d304f8a5c3c7a643f702f66c06ea5d638.1714399071.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C12Jani Nikula2-3/+3
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_WGC_C12 register macro. Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/62a748b685f253151b17c101dec75351577f30c0.1714399071.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C11_C10Jani Nikula2-3/+3
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_WGC_C11_C10 register macro. Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/3f7aae89cf63760bca43b54102c76b3ed2cf8735.1714399071.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C02Jani Nikula2-3/+3
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_WGC_C02 register macro. Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/550d4e787445802236f0bf89e4d2f4f32cbd6d75.1714399071.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-30drm/i915: pass dev_priv explicitly to PIPE_WGC_C01_C00Jani Nikula2-3/+3
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_WGC_C01_C00 register macro. Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/85b3db6e666a7a629b10b482b7e7043d52d30511.1714399071.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-30drm/i915: pass dev_priv explicitly to PALETTEJani Nikula2-11/+20
Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PALETTE register macro. Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/bf07d29cefef23ebd5d54fbb0d3bf7e41d132d93.1714399071.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-30Merge tag 'amd-drm-next-6.10-2024-04-26' of ↵Dave Airlie185-286/+1650
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.10-2024-04-26: amdgpu: - Misc code cleanups and refactors - Support setting reset method at runtime - Report OD status - SMU 14.0.1 fixes - SDMA 4.4.2 fixes - VPE fixes - MES fixes - Update BO eviction priorities - UMSCH fixes - Reset fixes - Freesync fixes - GFXIP 9.4.3 fixes - SDMA 5.2 fixes - MES UAF fix - RAS updates - Devcoredump updates for dumping IP state - DSC fixes - JPEG fix - Fix VRAM memory accounting - VCN 5.0 fixes - MES fixes - UMC 12.0 updates - Modify contiguous flags handling - Initial support for mapping kernel queues via MES amdkfd: - Fix rescheduling of restore worker - VRAM accounting for SVM migrations - mGPU fix - Enable SQ watchpoint for gfx10 Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-30Merge tag 'drm-intel-gt-next-2024-04-26' of ↵Dave Airlie53-156/+399
https://anongit.freedesktop.org/git/drm/drm-intel into drm-next UAPI Changes: - drm/i915/guc: Use context hints for GT frequency Allow user to provide a low latency context hint. When set, KMD sends a hint to GuC which results in special handling for this context. SLPC will ramp the GT frequency aggressively every time it switches to this context. The down freq threshold will also be lower so GuC will ramp down the GT freq for this context more slowly. We also disable waitboost for this context as that will interfere with the strategy. We need to enable the use of SLPC Compute strategy during init, but it will apply only to contexts that set this bit during context creation. Userland can check whether this feature is supported using a new param- I915_PARAM_HAS_CONTEXT_FREQ_HINT. This flag is true for all guc submission enabled platforms as they use SLPC for frequency management. The Mesa usage model for this flag is here - https://gitlab.freedesktop.org/sushmave/mesa/-/commits/compute_hint - drm/i915/gt: Enable only one CCS for compute workload Enable only one CCS engine by default with all the compute sices allocated to it. While generating the list of UABI engines to be exposed to the user, exclude any additional CCS engines beyond the first instance *** NOTE: This W/A will make all DG2 SKUs appear like single CCS SKUs by default to mitigate a hardware bug. All the EUs will still remain usable, and all the userspace drivers have been confirmed to be able to dynamically detect the change in number of CCS engines and adjust. For the smaller percent of applications that get perf benefit from letting the userspace driver dispatch across all 4 CCS engines we will be introducing a sysfs control as a later patch to choose 4 CCS each with 25% EUs (or 50% if 2 CCS). NOTE: A regression has been reported at https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895 However Andi has been triaging the issue and we're closing in a fix to the gap in the W/A implementation: https://lists.freedesktop.org/archives/intel-gfx/2024-April/348747.html Driver Changes: - Add new and fix to existing workarounds: Wa_14018575942 (MTL), Wa_16019325821 (Gen12.70), Wa_14019159160 (MTL), Wa_16015675438, Wa_14020495402 (Gen12.70) (Tejas, John, Lucas) - Fix UAF on destroy against retire race and remove two earlier partial fixes (Janusz) - Limit the reserved VM space to only the platforms that need it (Andi) - Reset queue_priority_hint on parking for execlist platforms (Chris) - Fix gt reset with GuC submission is disabled (Nirmoy) - Correct capture of EIR register on hang (John) - Remove usage of the deprecated ida_simple_xx() API - Refactor confusing __intel_gt_reset() (Nirmoy) - Fix the fix for GuC reset lock confusion (John) - Simplify/extend platform check for Wa_14018913170 (John) - Replace dev_priv with i915 (Andi) - Add and use gt_to_guc() wrapper (Andi) - Remove bogus null check (Rodrigo, Dan) . Selftest improvements (Janusz, Nirmoy, Daniele) Signed-off-by: Dave Airlie <[email protected]> From: Joonas Lahtinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-29Merge v6.9-rc6 into drm-nextDaniel Vetter23-195/+89
Thomas needs the defio fixes, Maíra needs the vkms fixes and Joonas has some fun with i915-gem conflicts. Signed-off-by: Daniel Vetter <[email protected]>
2024-04-29drm/xe: Merge 16021540221 and 18034896535 WAsLucas De Marchi1-6/+1
In order to detect duplicate implementations for the same workaround, early in the implementation of RTP it was decided to error out even if the values set are exactly the same. With the introduction of 18034896535 in commit 74671d23ca18 ("drm/xe/xe2: Add workaround 18034896535"), LNL stepping with graphics stepping A1 now gives the following error on module load: xe 0000:00:02.0: [drm] *ERROR* GT0: [GT OTHER] \ discarding save-restore reg e48c (clear: 00000200, set: 00000200,\ masked: yes, mcr: yes): ret=-22 RTP may be improved in the future, but for now simply join the entries like done with e.g. "1607297627, 1607030317, 1607186500". Fixes: 74671d23ca18 ("drm/xe/xe2: Add workaround 18034896535") Cc: Bommu Krishnaiah <[email protected]> Cc: Tejas Upadhyay <[email protected]> Cc: Matt Roper <[email protected]> Reviewed-by: Himal Prasad Ghimiray <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-29drm/xe/xe2hpg: Add Wa_14021490052Shekhar Chauhan1-0/+9
Add Wa_14021490052 for Xe2HPG 20.01. Signed-off-by: Shekhar Chauhan <[email protected]> Reviewed-by: Gustavo Sousa <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-29drm: ci: fix the xfails for apq8016Abhinav Kumar1-12/+1
After IGT migrating to dynamic sub-tests, the pipe prefixes in the expected fails list are incorrect. Lets drop those to accurately match the expected fails. In addition, update the xfails list to match the current passing list. This should have ideally failed in the CI run because some tests were marked as fail even though they passed but due to the mismatch in test names, the matching didn't correctly work and was resulting in those failures not being seen. Here is the passing pipeline for apq8016 with this change: https://gitlab.freedesktop.org/drm/msm/-/jobs/57050562 Signed-off-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Acked-by: Helen Koike <[email protected]> Signed-off-by: Helen Koike <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-29drm/imagination: Ensure PVR_MIPS_PT_PAGE_COUNT is never zeroMatt Coster1-2/+3
When the host page size was more than 4 times larger than the FW page size, this macro evaluated to zero resulting in zero-sized arrays. Use DIV_ROUND_UP() to ensure the correct behavior. Reported-by: [email protected] Closes: https://lore.kernel.org/dri-devel/[email protected] Link: https://lore.kernel.org/dri-devel/[email protected] Fixes: 927f3e0253c1 ("drm/imagination: Implement MIPS firmware processor and MMU support") Cc: [email protected] Signed-off-by: Matt Coster <[email protected]> Reviewed-by: Frank Binns <[email protected]>
2024-04-29Revert "drm/bridge: ti-sn65dsi83: Fix enable error path"Luca Ceresoli1-1/+0
This reverts commit 8a91b29f1f50ce7742cdbe5cf11d17f128511f3f. The regulator_disable() added by the original commit solves one kind of regulator imbalance but adds another one as it allows the regulator to be disabled one more time than it is enabled in the following scenario: 1. Start video pipeline -> sn65dsi83_atomic_pre_enable -> regulator_enable 2. PLL lock fails -> regulator_disable 3. Stop video pipeline -> sn65dsi83_atomic_disable -> regulator_disable The reason is clear from the code flow, which looks like this (after removing unrelated code): static void sn65dsi83_atomic_pre_enable() { regulator_enable(ctx->vcc); if (PLL failed locking) { regulator_disable(ctx->vcc); <---- added by patch being reverted return; } } static void sn65dsi83_atomic_disable() { regulator_disable(ctx->vcc); } The use case for introducing the additional regulator_disable() was removing the module for debugging (see link below for the discussion). If the module is removed after a .atomic_pre_enable, i.e. with an active pipeline from the DRM point of view, .atomic_disable is not called and thus the regulator would not be disabled. According to the discussion however there is no actual use case for removing the module with an active pipeline, except for debugging/development. On the other hand, the occurrence of a PLL lock failure is possible due to any physical reason (e.g. a temporary hardware failure for electrical reasons) so handling it gracefully should be supported. As there is no way for .atomic[_pre]_enable to report an error to the core, the only clean way to support it is calling regulator_disabled() only in .atomic_disable, unconditionally, as it was before. Link: https://lore.kernel.org/all/15244220.uLZWGnKmhe@steina-w/ Fixes: 8a91b29f1f50 ("drm/bridge: ti-sn65dsi83: Fix enable error path") Reviewed-by: Alexander Stein <[email protected]> Signed-off-by: Luca Ceresoli <[email protected]> Signed-off-by: Robert Foss <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-29drm/i915/display: split out intel_sprite_regs.h from i915_reg.hJani Nikula8-341/+357
Clean up i915_reg.h. v2: Drop a redundant comment (Ville) Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/679b7395a78c53006ac07448706f1809b74810de.1714128645.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-29drm/i915/display: split out intel_fbc_regs.h from i915_reg.hJani Nikula6-123/+125
Clean up i915_reg.h. v2: Drop chicken regs and comments (Ville) Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/aa9b5d8adefbe97e1e37c9cfada3ab1581b0e8d5.1714128645.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-29drm/i915/color: move palette registers to intel_color_regs.hJani Nikula2-31/+29
For some reason the paletter registers were missed when adding intel_color_regs.h. Finish the job. Adjust some comments while at it. v2: Fix comments (Ville) Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/1322f577b113b8fc1a6c2ef35340fc3c599b4bcb.1714128645.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-29drm/i915/audio: move LPE audio regs to intel_audio_regs.hJani Nikula3-17/+17
There are too few registers to warrant a dedicated file for LPE audio regs, but the audio reg file is better than i915_reg.h. v2: Rebase Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/b5ee35309b2e0905aaa12d944b3d379c45a8a0bd.1714128645.git.jani.nikula@intel.com Signed-off-by: Jani Nikula <[email protected]>
2024-04-27drm: xlnx: zynqmp_dpsub: Fix compilation errorAnatoliy Klymenko1-1/+1
Fix W=1 clang 19 compilation error in zynqmp_disp_layer_drm_formats(). Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Anatoliy Klymenko <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-27drm: xlnx: zynqmp_dpsub: Fix few function commentsAnatoliy Klymenko1-2/+2
Fix arguments description for zynqmp_disp_layer_find_live_format() and zynqmp_disp_layer_set_live_format(). Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Anatoliy Klymenko <[email protected]> Signed-off-by: Tomi Valkeinen <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-26drm/amd/display: Fix CFLAGS for dml2_core_dcn4_calcs.oNathan Chancellor1-2/+2
-Wframe-larger-than=2048 is a part of both CFLAGS and CFLAGS_REMOVE for dml2_core_dcn4_calcs.o, which means that it ultimately gets removed altogether for 64-bit targets, as 2048 is the default FRAME_WARN value for 64-bit platforms, resulting in no -Wframe-larger-than coverage for this file. Remove -Wframe-larger-than from CFLAGS_REMOVE_dml2_core_dcn4_calcs.o and move to $(frame_warn_flag) for CFLAGS_dml2_core_dcn4_calcs.o, as that accounts for the fact that -Wframe-larger-than may need to be larger than 2048 in certain situations, such as when the sanitizers are enabled. Fixes: 00c391102abc ("drm/amd/display: Add misc DC changes for DCN401") Signed-off-by: Nathan Chancellor <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Add frame_warn_flag to dml2_core_shared.oNathan Chancellor1-1/+1
When building with tip of tree Clang, there are some new instances of -Wframe-larger-than from the new display code (which become fatal with CONFIG_WERROR=y): drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c:754:6: error: stack frame size (2488) exceeds limit (2048) in 'dml2_core_shared_mode_support' [-Werror,-Wframe-larger-than] 754 | bool dml2_core_shared_mode_support(struct dml2_core_calcs_mode_support_ex *in_out_params) | ^ drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.c:9834:6: error: stack frame size (2152) exceeds limit (2048) in 'dml2_core_shared_mode_programming' [-Werror,-Wframe-larger-than] 9834 | bool dml2_core_shared_mode_programming(struct dml2_core_calcs_mode_programming_ex *in_out_params) | ^ 2 errors generated. These warnings do not occur when CONFIG_K{A,C,M}SAN are disabled, so add $(frame_warn_flag) to dml2_core_shared.o's CFLAGS, which was added in commit 6740ec97bcdb ("drm/amd/display: Increase frame warning limit with KASAN or KCSAN in dml2") to account for this situation. Fixes: 00c391102abc ("drm/amd/display: Add misc DC changes for DCN401") Signed-off-by: Nathan Chancellor <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-26drm/amd/display: Address kdoc for 'Enable CRTC' in optc401_enable_crtcSrinivasan Shanmugam1-2/+6
This commit fixes the kdoc for 'Enable CRTC' in `optc401_enable_crtc` function. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/optc/dcn401/dcn401_optc.c:177: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Enable CRTC Fixes: 70839da63605 ("drm/amd/display: Add new DCN401 sources") Cc: Rodrigo Siqueira <[email protected]> Cc: Roman Li <[email protected]> Cc: Qingqing Zhuo <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Tom Chung <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Tom Chung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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