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2023-04-12drm/amd/pm: correct SMU13.0.7 pstate profiling clock settingsHoratio Zhang1-7/+15
Correct the pstate standard/peak profiling mode clock settings for SMU13.0.7. Signed-off-by: Horatio Zhang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.1.x
2023-04-12drm/amd/display: Pass the right info to drm_dp_remove_payloadWayne Lin1-7/+50
[Why & How] drm_dp_remove_payload() interface was changed. Correct amdgpu dm code to pass the right parameter to the drm helper function. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-12drm/i915/vrr: Allow VRR to be toggled during fastsetsVille Syrjälä1-1/+2
Now that VRR enable/disable are called from convenient places it is trivial to allow it to change state during fastsets. Make it so. Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7542 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mitul Golani <[email protected]>
2023-04-12drm/i915/vrr: Relocate VRR enable/disableVille Syrjälä5-27/+58
Move VRR enabling/disabling into a place where it also works for fastsets. With this we always start the transcoder up in non-VRR mode. Granted we already did that but for a very short period of time. But now that we might end up doing a bit more with the transcoder in non-VRR mode it seems prudent to also update the active timings as the transcoder changes its operating mode. crtc_state->vrr.enable still tracks whether VRR is actually enabled or not, but now we configure all the other VRR timing registers whenever VRR is possible (whether we actually enable it or not). crtc_state->vrr.flipline can now serve as our "is VRR possible" bit of state. I decided to leave the MSA timing ignore bit set all the time whether VRR is actually enabled or not. If the sink can figure out the timings with that information when VRR is active then surely it can also do it when VRR is inactive. v2: Protect intel_vrr_set_transcoder_timings() with HAS_VRR() Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mitul Golani <[email protected]>
2023-04-12drm/i915/vrr: Tell intel_crtc_update_active_timings() about VRR explicitlyVille Syrjälä5-7/+17
In order to move VRR enable/disable to a place where it's also applicable to fastsets we need to be prepared to configure the pipe into non-VRR mode initially, and then later switch to VRR mode. To that end allow the active timings to be configured in non-VRR mode temporarily even when the crtc_state says we're going to be using VRR. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mitul Golani <[email protected]>
2023-04-12drm/i915/vrr: Make delayed vblank operational in VRR mode on adl/dg2Ville Syrjälä2-2/+9
On adl/dg2 a chicken bit needs to be set for TRANS_SET_CONTENXT_LATENCY to take effect in VRR mode. Can't really think of a reason why we'd ever disable that chicken bit, so let's just always set it. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mitul Golani <[email protected]>
2023-04-12drm/i915/vrr: Eliminate redundant function argumentsVille Syrjälä4-15/+8
Some of the VRR functions take redundant arguments. Get rid of them to make life simpler. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mitul Golani <[email protected]>
2023-04-12drm/i915: Generalize planes_{enabling,disabling}()Ville Syrjälä1-4/+12
I want to use the same logic that planes_{enabling,disabling}() are using for other features as well. Generlize the thing into a pair of macros. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mitul Golani <[email protected]>
2023-04-12Merge tag 'drm-misc-next-2023-04-12' of ↵Daniel Vetter18-211/+209
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v6.4-rc1: Cross-subsystem Changes: - Convert MIPI DSIM bridge dt to yaml. Core Changes: - Fix UAF race in drm scheduler. Driver Changes: - Add primary plane positioning support to VKMS. - Convert omapdrm fbdev emulation to in-kernel client. - Assorted small fixes to vkms, vc4, nouveau, vmwgfx. Signed-off-by: Daniel Vetter <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-04-12drm/vkms: Use drmm_mode_config_init()Maíra Canal1-1/+5
Use drmm_mode_config_init() instead of drm_mode_config_init(), as it allows us to assure that the resource will be properly cleaned. Signed-off-by: Maíra Canal <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Signed-off-by: Maíra Canal <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-04-12drm/vkms: Use drmm_crtc_init_with_planes()Maíra Canal1-3/+2
Use drmm_crtc_init_with_planes() instead of drm_crtc_init_with_planes() to get rid of the explicit destroy hook in struct drm_crtc_funcs. Signed-off-by: Maíra Canal <[email protected]> Reviewed-by: Javier Martinez Canillas <[email protected]> Signed-off-by: Maíra Canal <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-04-12drm/i915/display: remove unnecessary i915_debugfs.h includesJani Nikula2-2/+0
Leftovers from before display debugfs was separated to its own file. Signed-off-by: Jani Nikula <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-04-12Merge remote-tracking branch 'drm/drm-fixes' into drm-misc-fixesMaarten Lankhorst70-333/+874
We were stuck on rc2, should at least attempt to track drm-fixes slightly. Signed-off-by: Maarten Lankhorst <[email protected]>
2023-04-12drm/i915: disable sampler indirect state in bindless heapLionel Landwerlin2-0/+20
By default the indirect state sampler data (border colors) are stored in the same heap as the SAMPLER_STATE structure. For userspace drivers that can be 2 different heaps (dynamic state heap & bindless sampler state heap). This means that border colors have to copied in 2 different places so that the same SAMPLER_STATE structure find the right data. This change is forcing the indirect state sampler data to only be in the dynamic state pool (more convenient for userspace drivers, they only have to have one copy of the border colors). This is reproducing the behavior of the Windows drivers. BSpec: 46052 Signed-off-by: Lionel Landwerlin <[email protected]> Cc: [email protected] Reviewed-by: Haridhar Kalvala <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 16fc9c08f0ec7b1c95f1ea4a16097acdb3fc943d) Signed-off-by: Joonas Lahtinen <[email protected]>
2023-04-11drm/amdgpu: Enable GFX11 SDMA context empty interruptGraham Sider2-10/+22
Enable SDMA queue empty context switching. SDMA context switch due to quantum programming no longer done here (as of sdma v6), so re-name sdma_v6_0_ctx_switch_enable to sdma_v6_0_ctxempty_int_enable to reflect this. Also program SDMAx_QUEUEx_SCHEDULE_CNTL for context switch due to quantum in KFD. Set to amdgpu_sdma_phase_quantum (defaults to 32 i.e. 3200us). Signed-off-by: Graham Sider <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Reviewed-by: Stanley Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdkfd: Check PCIe atomics support on GFX11 to set CP_HQD_HQ_STATUS0[29]Sreekant Somasekharan3-1/+16
CP_HQD_HQ_STATUS0[29] bit will be used by CPFW to acknowledge whether PCIe atomics are supported. The default value of this bit is set to 0. Driver will check whether PCIe atomics are supported and set the bit to 1 if supported. This will force CPFW to use real atomic ops. If the bit is not set, CPFW will default to read/modify/write using the firmware itself. This is applicable only to GFX11 RS64 CP with MEC FW >= 509. If MEC FW < 509 and for all GFX11 F32 CP, PCIe atomics needs to be supported else it will skip the device. This commit also involves moving amdgpu_amdkfd_device_probe() function call after per-IP early_init loop in amdgpu_device_ip_early_init() function so as to check for RS64 enabled device. Signed-off-by: Sreekant Somasekharan <[email protected]> Reviewed-by: Graham Sider <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Add logging for DP link traning Test Pattern SeqeuncesSrinivasan Shanmugam1-0/+9
Add some more logging for DP link traning test pattern seqeunces for better debugging. Cc: Fangzhi Zuo <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Fangzhi Zuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: correct ras enabled flagStanley.Yang1-0/+7
XGMI RAS should be according to the gmc xgmi physical nodes number, XGMI RAS should not be enabled if xgmi num_physical_nodes is zero. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: fix unexpected block idStanley.Yang2-0/+6
Aldebaran supports VCN and JPEG RAS, it reports unexpected block id message during VCN and JPEG RAS initialization if VCN and JPEG block id not defined. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: use sdma_v6 single packet invalidationPierre-Eric Pelloux-Prayer1-1/+22
This achieves the same result as the sequence used in emit_flush_gpu_tlb but the invalidation is now a single packet instead of the 3 packets required to implement reg_write_reg_wait. Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display : Log DP link training downspread infoSrinivasan Shanmugam1-6/+8
Update the existing log with DP LT downspread info: [Downstream devices shall support down spreading of the link clock. The down-spread amplitude shall either be disabled (0.0%) or up to 0.5%, as written by the upstream device to the DOWNSPREAD_CTRL register (DPCD 00107h). The modulation frequency range shall be 30 to 33 kHz] Besides, fix checkpatch warning: CHECK: Alignment should match open parenthesis Cc: Mario Limonciello <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: remove unused matching_stream_ptrs variableTom Rix1-4/+1
clang with W=1 reports drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_enc_cfg.c:625:6: error: variable 'matching_stream_ptrs' set but not used [-Werror,-Wunused-but-set-variable] int matching_stream_ptrs = 0; ^ This variable is not used so remove it. Reviewed-by: Nick Desaulniers <[email protected]> Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: set variables dml*_funcs storage-class-specifier to staticTom Rix1-12/+12
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:44:24: warning: symbol 'dml20_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:51:24: warning: symbol 'dml20v2_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:58:24: warning: symbol 'dml21_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:65:24: warning: symbol 'dml30_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:72:24: warning: symbol 'dml31_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:79:24: warning: symbol 'dml314_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.c:86:24: warning: symbol 'dml32_funcs' was not declared. Should it be static? These variables are only used in one file so should be static. Cleanup whitespace, use tabs consistently for indents. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: set variables aperture_default_system and ↵Tom Rix1-2/+2
context0_default_system storage-class-specifier to static smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.c:758:10: warning: symbol 'aperture_default_system' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn10/dcn10_hubp.c:759:10: warning: symbol 'context0_default_system' was not declared. Should it be static? These variables are only used in one file so should be static. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: set variable dcn3_14_soc storage-class-specifier to staticTom Rix1-1/+1
smatch reports drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.c:100:37: warning: symbol 'dcn3_14_soc' was not declared. Should it be static? This variable is only used in one file so should be static. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: Fix warningsLijo Lazar1-1/+1
Fix below warning due to incompatible types in conditional operator ../pm/swsmu/smu13/smu_v13_0_6_ppt.c:315:17: sparse: sparse: incompatible types in conditional expression (different base types): Signed-off-by: Lijo Lazar <[email protected]> Reported-by: kernel test robot <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/pm: correct SMU13.0.7 max shader clock reportingHoratio Zhang1-1/+60
Correct the max shader clock reporting on SMU 13.0.7. Signed-off-by: Horatio Zhang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/pm: correct SMU13.0.7 pstate profiling clock settingsHoratio Zhang1-7/+15
Correct the pstate standard/peak profiling mode clock settings for SMU13.0.7. Signed-off-by: Horatio Zhang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: refine get gpu clock counter methodTong Liu011-2/+15
[why] regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER are protected and unaccessible under sriov. The clock counter high bit may update during reading process. [How] Replace regGOLDEN_TSC_COUNT_LOWER/regGOLDEN_TSC_COUNT_UPPER with regCP_MES_MTIME_LO/regCP_MES_MTIME_HI to get gpu clock under sriov. Refine get gpu clock counter method to make the result more precise. Signed-off-by: Tong Liu01 <[email protected]> Acked-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: optimize redundant code in umc_v6_7YiPeng Chai1-91/+70
Optimize redundant code in umc_v6_7. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: Fix sdma v4 sw fini errorlyndonli1-1/+1
Fix sdma v4 sw fini error for sdma 4.2.2 to solve the following general protection fault [ +0.108196] general protection fault, probably for non-canonical address 0xd5e5a4ae79d24a32: 0000 [#1] PREEMPT SMP PTI [ +0.000018] RIP: 0010:free_fw_priv+0xd/0x70 [ +0.000022] Call Trace: [ +0.000012] <TASK> [ +0.000011] release_firmware+0x55/0x80 [ +0.000021] amdgpu_ucode_release+0x11/0x20 [amdgpu] [ +0.000415] amdgpu_sdma_destroy_inst_ctx+0x4f/0x90 [amdgpu] [ +0.000360] sdma_v4_0_sw_fini+0xce/0x110 [amdgpu] Signed-off-by: lyndonli <[email protected]> Reviewed-by: Likun Gao <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: DROP redundant drm_prime_sg_to_dma_addr_arrayShane Xiao1-3/+0
For DMA-MAP userptr on other GPUs, the dma address array will be populated in amdgpu_ttm_backend_bind. Remove the redundant call from the driver. v2: update the comment Signed-off-by: Shane Xiao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: optimize redundant code in umc_v8_10YiPeng Chai3-120/+115
Optimize redundant code in umc_v8_10 Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11amd/amdgpu: Inherit coherence flags base on original BO flagsShane Xiao1-4/+8
For SG BO to DMA-map userptrs on other GPUs, the SG BO need inherit MTYPEs in PTEs from original BO. If we set the flags, the device can be coherent with the CPUs and other GPUs. v2: 1. Drop unnecessary flags check 2. Remove local variable align Signed-off-by: Shane Xiao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/pm: Fix incorrect comment about Vangogh power cap supportGuilherme G. Piccoli1-2/+2
The comment mentions that power1 cap attributes are not supported on Vangogh, but the opposite is indeed valid: for APUs, only Vangogh is supported. While at it, also fixed the Renoir comment below (thanks Melissa for noticing that!). Cc: Lijo Lazar <[email protected]> Cc: Melissa Wen <[email protected]> Signed-off-by: Guilherme G. Piccoli <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: Add userptr bo support for mGPUs when iommu is onShane Xiao1-4/+23
For userptr bo with iommu on, multiple GPUs use same system memory dma mapping address when both adev and bo_adev are in identity mode or in the same iommu group. If RAM direct map to one GPU, other GPUs can share the original BO in order to reduce dma address array usage when RAM can direct map to these GPUs. However, we should explicit check whether RAM can direct map to all these GPUs. This patch fixes a potential issue that where RAM is direct mapped on some but not all GPUs. v2: 1. Update comment 2. Add helper function reuse_dmamap Signed-off-by: Shane Xiao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/amdgpu: Drop the hang limit parameterSrinivasan Shanmugam3-10/+1
The driver doesn't resubmit jobs on hangs any more, hence drop the hang limit parameter - amdgpu_job_hang_limit, wherever it is used. Suggested-by: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Kent Russell <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Fix potential null dereferenceIgor Artemiev1-1/+2
The adev->dm.dc pointer can be NULL and dereferenced in amdgpu_dm_fini() without checking. Add a NULL pointer check before calling dc_dmub_srv_destroy(). Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 9a71c7d31734 ("drm/amd/display: Register DMUB service with DC") Signed-off-by: Igor Artemiev <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: 3.2.230Aric Cyr1-1/+1
This DC version brings along: - FW Release 0.0.161.0 - Improvements on FPO/FAMS - Correction to DML calculation - Fix to multiple clock related issues Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd: Fix an out of bounds error in BIOS parserMario Limonciello1-5/+2
The array is hardcoded to 8 in atomfirmware.h, but firmware provides a bigger one sometimes. Deferencing the larger array causes an out of bounds error. commit 4fc1ba4aa589 ("drm/amd/display: fix array index out of bound error in bios parser") fixed some of this, but there are two other cases not covered by it. Fix those as well. Reported-by: [email protected] Link: https://bugzilla.kernel.org/show_bug.cgi?id=214853 Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2473 Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: [FW Promotion] Release 0.0.161.0Anthony Koo1-2/+26
- Add command to idle opt. - Rename d3 entry event and add idle trigger param on notify event. - Add bit to fw boot status to notify status when hardware is powered up. Reviewed-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Improve robustness of FIXED_VS link training at DP1 ratesMichael Strauss6-3/+396
[WHY] New sequence for transparent mode DP1.x link training was provided by LTTPR vendor [HOW] Implement new FIXED_VS sequence, increase LT retry count to minimize any potential intermittent lightup failures Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: Add MES KIQ clear to tell RLC that KIQ is dequeuedYifan Zha1-2/+12
[Why] As MES KIQ is dequeued, tell RLC that KIQ is inactive [How] Clear the RLC_CP_SCHEDULERS Active bit which RLC checks KIQ status In addition, driver can halt MES under SRIOV when unloading driver v2: Use scheduler0 mask to clear KIQ portion of RLC_CP_SCHEDULERS Signed-off-by: Yifan Zha <[email protected]> Reviewed-by: Horace Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: add dscclk instance offset checkCharlene Liu3-0/+30
[why] based on dscclk instance offset check conditiona program dscclk Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: On clock init, maintain DISPCLK freqAlvin Lee6-5/+45
[Description] - On init if a display is connected, we need to maintain the DISPCLK frequency - Even though DPG_EN=1, the display still requires the correct timing or it could cause audio corruption (if DISPCLK freq is reduced) - Read the current DISPCLK freq and request the same value to ensure the timing is valid and unchanged - However, add option to do a full pipe power down (including link) which will also avoid audio related issues - Disabled for the time being on dcn32 Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Add FPO + VActive supportAlvin Lee8-3/+267
[Description] - When determining FPO support, include FPO + VActive support - Support FPO + VActive if one display meets regular requirements for FPO and the second display is able to switch in VACTIVE with a given amount of margin Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Correct DML calculation to follow HW SPECPaul Hsieh4-4/+4
[Why] In 2560x1600@240p eDP panel, driver use lowest voltage level to play 1080p video cause underflow. According to HW SPEC, the senario should use high voltage level. [How] ChromaPre value is zero when bandwidth validation. Correct ChromaPre calculation. Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: prep work for root clock optimization enablement for DCN314Hamza Mahfooz2-1/+33
To enable root clock optimizations, we need a number of register writes and need to account for the difference in DPSTREAMCLK between DCN31 and DCN314. To prevent issues, add a number of register writes to DCCG_MASK_SH_LIST_DCN314_COMMON(), and define dccg314_init() which is mostly in alignment with dccg31_init() but accounts for the new DPSTREAMCLK sequence. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: add scaler control for dcn32Zhikai Zhai1-0/+1
[WHY] It will introduce the extra warnning log on some asic that doesn't register [HOW] Add the register on dcn32 Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Zhikai Zhai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amd/display: Clear FAMS flag if FAMS doesn't reduce vlevelAlvin Lee1-0/+4
[Description] - If we find that applying FAMS doesn't reduce the voltage level, we will not use it - Ensure to clear the stream flags indicating FAMS if we hit this case Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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