| Age | Commit message (Collapse) | Author | Files | Lines |
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Fix the following errors & warnings reported by checkpatch:
ERROR: space required before the open brace '{'
ERROR: space required before the open parenthesis '('
ERROR: that open brace { should be on the previous line
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: else should follow close brace '}'
ERROR: open brace '{' following function definitions go on the next line
ERROR: code indent should use tabs where possible
WARNING: braces {} are not necessary for single statement blocks
WARNING: void function return statements are not generally useful
WARNING: Block comments use * on subsequent lines
WARNING: Block comments use a trailing */ on a separate line
Cc: Rodrigo Siqueira <[email protected]>
Cc: Aurabindo Pillai <[email protected]>
Cc: Alex Deucher <[email protected]>
Signed-off-by: Srinivasan Shanmugam <[email protected]>
Reviewed-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This contains SOC specific functions, rename to a more generic format
<soc>.c => aqua_vanjaram.c
Signed-off-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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As of commit 6c80a93be62d398e ("drm/fb-helper: Initialize fb-helper's
preferred BPP in prepare function"), the preferred_bpp parameter of
drm_fb_helper_prepare() defaults to 32 instead of
drm_mode_config.preferred_depth. Hence this also applies to
drm_fbdev_dma_setup(), which just passes its own preferred_bpp
parameter.
Fixes: b79fe9abd58bab73 ("drm/fbdev-dma: Implement fbdev emulation for GEM DMA helpers")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Thomas Zimmermann <[email protected]>
Signed-off-by: Thomas Zimmermann <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/91f093ffe436a9f94d58fb2bfbc1407f1ebe8bb0.1688656591.git.geert+renesas@glider.be
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Pull drm fixes from Dave Airlie:
"Lots of fixes, mostly i915 and amdgpu. It's two weeks of i915, and I
think three weeks of amdgpu.
fbdev:
- Fix module infos on sparc
panel:
- Fix mode on Starry-ili9882t
i915:
- Allow DC states along with PW2 only for PWB functionality [adlp+]
- Fix SSC selection for MPLLA [mtl]
- Use hw.adjusted mode when calculating io/fast wake times [psr]
- Apply min softlimit correctly [guc/slpc]
- Assign correct hdcp content type [hdcp]
- Add missing forward declarations/includes to display power headers
- Fix BDW PSR AUX CH data register offsets [psr]
- Use mock device info for creating mock device
amdgpu:
- Misc cleanups
- GFX 9.4.3 fixes
- DEBUGFS build fix
- Fix LPDDR5 reporting
- ASPM fixes
- DCN 3.1.4 fixes
- DP MST fixes
- DCN 3.2.x fixes
- Display PSR TCON fixes
- SMU 13.x fixes
- RAS fixes
- Vega12/20 SMU fixes
- PSP flashing cleanup
- GFX9 MCBP fixes
- SR-IOV fixes
- GPUVM clear mappings fix for always valid BOs
- Add FAMS quirk for problematic monitor
- Fix possible UAF
- Better handle monentary temperature fluctuations
- SDMA 4.4.2 fixes
- Fencing fix"
* tag 'drm-next-2023-07-07' of git://anongit.freedesktop.org/drm/drm: (83 commits)
drm/i915: use mock device info for creating mock device
drm/i915/psr: Fix BDW PSR AUX CH data register offsets
drm/amdgpu: Fix potential fence use-after-free v2
drm/amd/pm: avoid unintentional shutdown due to temperature momentary fluctuation
drm/amd/pm: expose swctf threshold setting for legacy powerplay
drm/amd/display: 3.2.241
drm/amd/display: Take full update path if number of planes changed
drm/amd/display: Create debugging mechanism for Gaming FAMS
drm/amd/display: Add monitor specific edid quirk
drm/amd/display: For new fast update path, loop through each surface
drm/amd/display: Remove Phantom Pipe Check When Calculating K1 and K2
drm/amd/display: Limit new fast update path to addr and gamma / color
drm/amd/display: Fix the delta clamping for shaper LUT
drm/amdgpu: Keep non-psp path for partition switch
drm/amd/display: program DPP shaper and 3D LUT if updated
Revert "drm/amd/display: edp do not add non-edid timings"
drm/amdgpu: share drm device for pci amdgpu device with 1st partition device
drm/amd/pm: Add GFX v9.4.3 unique id to sysfs
drm/amd/pm: Enable pp_feature attribute
drm/amdgpu/vcn: Need to unpause dpg before stop dpg
...
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git://anongit.freedesktop.org/drm/drm-misc into drm-next
Short summary of fixes pull:
* panel: Fix mode on Starry-ili9882t
Signed-off-by: Dave Airlie <[email protected]>
From: Thomas Zimmermann <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/20230706112203.GA30555@linux-uq9g
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git://anongit.freedesktop.org/drm/drm-intel into drm-next
- Fix BDW PSR AUX CH data register offsets [psr] (Ville Syrjälä)
- Use mock device info for creating mock device (Jani Nikula)
Signed-off-by: Dave Airlie <[email protected]>
From: Tvrtko Ursulin <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/ZKZ6VIeInBYrBuph@tursulin-desk
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https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-fixes-6.5-2023-06-30-1:
amdgpu:
- Misc cleanups
- GFX 9.4.3 fixes
- DEBUGFS build fix
- Fix LPDDR5 reporting
- ASPM fixes
- DCN 3.1.4 fixes
- DP MST fixes
- DCN 3.2.x fixes
- Display PSR TCON fixes
- SMU 13.x fixes
- RAS fixes
- Vega12/20 SMU fixes
- PSP flashing cleanup
- GFX9 MCBP fixes
- SR-IOV fixes
- GPUVM clear mappings fix for always valid BOs
- Add FAMS quirk for problematic monitor
- Fix possible UAF
- Better handle monentary temperature fluctuations
- SDMA 4.4.2 fixes
- Fencing fix
Signed-off-by: Dave Airlie <[email protected]>
From: Alex Deucher <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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GuC load takes longer sometimes due to GT frequency not ramping up.
Add perf_limit_reasons to the existing warn print to see if frequency
is being throttled.
v2: Review comments (Ashutosh)
Signed-off-by: Vinay Belgaumkar <[email protected]>
Reviewed-by: Ashutosh Dixit <[email protected]>
Signed-off-by: Daniele Ceraolo Spurio <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Signed-off-by: Karol Herbst <[email protected]>
Reviewed-by: Ben Skeggs <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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RM complains very loudly at the aux transaction attempts.
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Karol Herbst <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Karol Herbst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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DRM cleanup paths unconditionally call nvif_mmu_dtor() for clients,
which would result in a double-free if nvif_mmu_ctor()'d previously
failed.
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Karol Herbst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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GSP-RM will enforce this, so implement on HW too so we can share code.
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Karol Herbst <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Karol Herbst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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We're adding better support for the non-stall interrupt, which will need
to fetch the interrupt vector from the runlist's primary engine.
NVKM doesn't support all target engines (ie. NVDEC etc), and it wouldn't
be ideal to completely fail initialisation in this case.
Instead. Remove runlists where we can't determine all the needed info.
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Karol Herbst <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Karol Herbst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Callers expect this - not NULL.
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Karol Herbst <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Karol Herbst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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This was renamed to nvkm_chan in the host rework.
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Karol Herbst <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Karol Herbst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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No need for custom implementation anymore.
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Karol Herbst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Also exposes this for use by upcoming GSP-RM initialisation code.
v2: add SPDX header
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Karol Herbst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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This can be completely normal in some situations (ie. non-stall intrs
when nothing is waiting on them).
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Karol Herbst <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Karol Herbst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Turns out, we're currently tearing down the disp core channel *before*
the satellite channels (wndw, etc) during suspend.
This makes RM return NV_ERR_NOT_SUPPORTED on attempting to reallocate
the core channel on resume for some reason, but we probably shouldn't
be doing it on HW either.
Tear down children in the reverse of allocation order instead.
Signed-off-by: Ben Skeggs <[email protected]>
Reviewed-by: Karol Herbst <[email protected]>
Reviewed-by: Lyude Paul <[email protected]>
Signed-off-by: Karol Herbst <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Smatch detected potential error pointer dereference.
drivers/gpu/drm/drm_syncobj.c:888 drm_syncobj_transfer_to_timeline()
error: 'fence' dereferencing possible ERR_PTR()
The error pointer comes from dma_fence_allocate_private_stub(). One
caller expected error pointers and one expected NULL pointers. Change
it to return NULL and update the caller which expected error pointers,
drm_syncobj_assign_null_handle(), to check for NULL instead.
Fixes: f781f661e8c9 ("dma-buf: keep the signaling time of merged fences v3")
Signed-off-by: Dan Carpenter <[email protected]>
Reviewed-by: Christian König <[email protected]>
Reviewed-by: Sumit Semwal <[email protected]>
Signed-off-by: Sumit Semwal <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Commit 2caffbf11762 ("drm/i915: Revoke mmaps and prevent access to fence
registers across reset") removed the temporary implementation of a reset
under stop machine but forgot to remove this one commented out define.
Signed-off-by: Tvrtko Ursulin <[email protected]>
Reviewed-by: Jani Nikula <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Try to deal with duplicate child devices for the same DDI port
by attempting to initialize them in VBT defined order The first
on to succeed for a specific DDI port will be the one we use.
We'll also get rid of i915->display.vbt.ports[] here as any conflicts
will now be handled at encoder registration time rather than during
VBT parsing. Note that intel_bios_encoder_data_lookup() still remaims
for pre-DDI DP/HDMI ports as those don't (at least yet) use VBT
driven initialization.
TODO: DSI dual link handling is sketchy at best
v2: Leave intel_bios_encoder_port() to the encoder callback (Jani)
Cc: Jani Nikula <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Jani Nikula <[email protected]>
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We'll have a few places where we need to do the full (incl. ICL+ DSI)
DVO port->port conversion, so extract the code for that into a helper.
Suggested-by: Jani Nikula <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Jani Nikula <[email protected]>
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Stop with the VBT AUX CH sanitation, and instead just check
that the appropriate AUX CH is still available when initializing
a DP/TC port.
The reason being that we want to start initializing ports in
VBT order to deal with VBTs that declare child devices with
seemingly conflicting ports. As the encoder initialization can
fail for other reasons (at least for eDP+AUX) we can't know
upfront which way the conflicts should be resolved.
Note that the old way of sanitizing gave priority to the last
port declared in the VBT, but now we sort of do the opposite by
favoring the first encoder to successfully initialize. The reason
for the old "last port wins" preference was eg. Asrock B250M-HDV
where port A (eDP) and port E (DP->VGA) have an AUX CH conflict
and we need to prefer port E. However with the new way port A (eDP)
will be probed first, but will fail to probe due to HPD and thus
port E will still win in the end.
v2: Pimp the commit message (Jani)
Reviewed-by: Jani Nikula <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Stop with the VBT DDC pin sanitation, and instead just check
that the appropriate DDC pin is still available when initializing
a HDMI connector.
The reason being that we want to start initializing ports in
VBT order to deal with VBTs that declare child devices with
seemingly conflicting ports. As the encoder initialization can
fail for other reasons (at least for eDP+AUX) we can't know
upfront which way the conflicts should be resolved.
Note that the old way of sanitizing gave priority to the last
port declared in the VBT, but now we sort of do the opposite by
favoring the first encoder to successfully initialize. So far
we're not aware of HDMI/DDC use cases where this would matter
but for AUX CH (will be subject to a similar change) there are
known cases where it matters.
Also note that the old code fell back to the platform default DDC
pin if the VBT pin was populated but invalid. That doesn't seem like
such a great idea because the VBT might have later declared another
port using that platform default pin, and so we might just be
creating more DDC pin conflicts here. So lets not second guess the
VBT and simply reject the entire HDMI encoder if the VBT DDC pin is
invalid.
v2: Pimp the commit message (Jani)
Cc: Jani Nikula <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Jani Nikula <[email protected]>
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Mixing VBT based AUX CH with platform defaults seems like
a recipe for conflicts. Let's only populate AUX CH if we
absolutely need it, that is only if we are dealing with
a DP output or a TC port (which need it due to some power
well shenanigans).
TODO: double check that real VBTs do in fact populate
the AUX CH for HDMI TC legacy ports...
Reviewed-by: Jani Nikula <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Make sure dig_port->aux_ch is trustworthy by initializing it
to NONE (-1) at the start. The encoder init will later fill in
the actual value, if appropriate.
Reviewed-by: Jani Nikula <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Currently we just clamp that value to the highest supported one, however that
means, we are not able to fit this into our available bandwidth range, so we
might see glitches or FIFO underruns.
While choosing less compressed bpp than min bpp required to handle the mode is
harmless and might even save some bandwidth, choosing higher compressed bpp than
min bpp required to handle the required mode config, can cause issues.
So in that case lets just conclude that even with DSC, we are not able to comply
with bandwidth requirements and fail.
v2: - s/clamp_t/min_t/ (Luca Coelho)
Signed-off-by: Stanislav Lisovskiy <[email protected]>
Reviewed-by: Luca Coelho <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Loongson display controller IP has been integrated in both Loongson north
bridge chipset (ls7a1000/ls7a2000) and Loongson SoCs (ls2k1000/ls2k2000).
It has even been included in Loongson's BMC products. It has two display
pipes, and each display pipe supports a primary plane and a cursor plane.
For the DC in the LS7a1000, each display pipe has a DVO output interface,
which is able to support 1920x1080@60Hz. For the DC in the LS7A2000, each
display pipe is equipped with a built-in HDMI encoder, which is compliant
with the HDMI 1.4 specification. The first display pipe is also equipped
with a transparent VGA encoder, which is parallel with the HDMI encoder.
To get a decent performance for writing framebuffer data to the VRAM, the
write combine support should be enabled.
v1 -> v2:
1) Use hpd status reg when polling for ls7a2000.
2) Fix all warnings that emerged when compiling with W=1.
v2 -> v3:
1) Add COMPILE_TEST to Kconfig and make the driver off by default
2) Alphabetical sorting headers (Thomas)
3) Untangle register access functions as much as possible (Thomas)
4) Switch to TTM-based memory manager (Thomas)
5) Add the chip ID detection function which can be used to distinguish
chip models
6) Revise the built-in HDMI phy driver, nearly all main stream mode below
4K@30Hz is tested, and this driver supports clone(mirror) display mode
and extend(joint) display mode.
v3 -> v4:
1) Quickly fix a small mistake.
v4 -> v5:
1) Add per display pipe debugfs support to the builtin HDMI encoder.
v5 -> v6:
1) Remove stray code which didn't get used, say lsdc_of_get_reserved_ram
2) Fix all typos I could found, make sentences and code more readable
3) Untangle lsdc_hdmi*_connector_detect() function according to the pipe
4) Rename this driver as loongson.
v6 -> v7:
1) Add prime support for buffer self-sharing, sharing buffer with
drm/etnaviv is also tested and it works with limitations.
2) Implement buffer object tracking with list_head.
3) Add S3(sleep to RAM) support
4) Rewrite lsdc_bo_move since TTM core stop allocating resources
during BO creation. Patch V1 ~ V6 of this series no longer work.
Thus, we send V7.
v7 -> v8:
1) Zero a compile warning on a 32-bit platform, compile with W=1
2) Revise lsdc_bo_gpu_offset() and make minor cleanups.
3) Pageflip tested on the virtual terminal with the following commands:
modetest -M loongson -s 32:1920x1080 -v
modetest -M loongson -s 34:1920x1080 -v -F tiles
It works like a charm, when running the pageflip test with dual screens
configuration, another two additional BOs were created by the modetest,
VRAM usage up to 40+ MB, well we have at least 64MB, still enough.
# cat bos
bo[0000]: size: 8112kB VRAM
bo[0001]: size: 16kB VRAM
bo[0002]: size: 16kB VRAM
bo[0003]: size: 16208kB VRAM
bo[0004]: size: 8112kB VRAM
bo[0005]: size: 8112kB VRAM
v8 -> v9:
1) Select I2C and I2C_ALGOBIT in Kconfig, should depend on MMU.
2) Using pci_get_domain_bus_and_slot to get the GPU device.
v9 -> v10:
1) Revise lsdc_drm_freeze() to implement S3 correctly. We realized that
the pinned BO could not be moved, the VRAM lost power when sleeping
to RAM. Thus, the data in the buffer who is pinned in VRAM will get
lost when resumed. Yet it's not a big problem because this driver
relies on the CPU to update the front framebuffer. We can see the
garbage data when resume from S3, but the screen will show the right
image as I move the cursor. This is due to the CPU repaint. v10 of
this patch makes S3 perfect by unpin all of the BOs in VRAM, evict
them all to system RAM in lsdc_drm_freeze().
v10 -> v11:
1) On a double-screen case, The buffer object backing the single giant
framebuffer is referenced by two GEM objects; hence, it will be
pinned at least twice by prepare_fb() function. This causes its pin
count > 1. V10 of this patch only unpins VRAM BOs once when suspend,
which is not correct on double-screen case. V11 of this patch unpin
the BOs until its pin count reaches zero when suspend. Then, we make
the S3 support complete finally. With v11, I can't see any garbage
data when resume.
2) Fix vblank wait timeout when disable CRTC.
3) Test against IGT, at least fbdev test and kms_flip test passed.
4) Rewrite pixel PLL update function, magic numbers eliminated (Emil)
5) Drop a few common hardware features description in lsdc_desc (Emil)
6) Drop lsdc_mode_config_mode_valid(), instead add restrictions in dumb
create function. (Emil)
7) Untangle the ls7a1000 case and ls7a2000 case completely (Thomas)
v11 -> v12:
none
v12 -> v13:
1) Add benchmarks to figure out the bandwidth of the hardware platform.
Usage:
# cd /sys/kernel/debug/dri/0/
# cat benchmark
2) VRAM is filled with garbage data if uninitialized, add a buffer
clearing procedure (lsdc_bo_clear), clear the BO on creation time.
3) Update copyrights and adjust coding style (Huacai)
v13 -> v14:
1) Trying to add async update support for cursor plane.
v14 -> v15:
1) Add lsdc_vga_set_decode() funciton, which allow us remove multi-video
cards workaround, now it allow drm/loongson, drm/amdgpu, drm/etnaviv
co-exist in the system, more is also possible (Emil and Xuerui)
2) Fix typos and grammar mistakes as much as possible (Xuerui)
3) Unify copyrights as GPL-2.0+ (Xuerui)
4) Fix a bug introduce since V13, TTM may import BO from other drivers,
we shouldn't clear it on such a case.
Cc: Maarten Lankhorst <[email protected]>
Cc: Maxime Ripard <[email protected]>
Cc: Thomas Zimmermann <[email protected]>
Cc: David Airlie <[email protected]>
Cc: Daniel Vetter <[email protected]>
Cc: Sumit Semwal <[email protected]>
Cc: "Christian König" <[email protected]>
Cc: Nathan Chancellor <[email protected]>
Cc: Emil Velikov <[email protected]>
Cc: Geert Uytterhoeven <[email protected]>
Cc: [email protected]
Tested-by: Liu Peibao <[email protected]>
Tested-by: Li Yi <[email protected]>
Acked-by: Thomas Zimmermann <[email protected]>
Signed-off-by: Sui Jingfeng <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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else is not generally useful after return
Signed-off-by: Sui Jingfeng <[email protected]>
Reviewed-by: Thomas Zimmermann <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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The __raw_uncore_* interface is supposed to be intel_uncore.[ch]
internal only. Replace the remaining outside user with
intel_uncore_read_fw(), which is essentially the same thing.
Signed-off-by: Jani Nikula <[email protected]>
Reviewed-by: Lucas De Marchi <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Add a helper for accessing uncore->regs instead of doing it
directly. This will help display code reuse with the xe driver.
Cc: Andi Shyti <[email protected]>
Signed-off-by: Jani Nikula <[email protected]>
Reviewed-by: Lucas De Marchi <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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If we are using Bigjoiner dpll_hw_state is supposed to be exactly
same as for master crtc, so no need to save it's state for slave crtc.
Signed-off-by: Stanislav Lisovskiy <[email protected]>
Fixes: 0ff0e219d9b8 ("drm/i915: Compute clocks earlier")
Reviewed-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Use vmalloc_array and vcalloc to protect against
multiplication overflows.
The changes were done using the following Coccinelle
semantic patch:
// <smpl>
@initialize:ocaml@
@@
let rename alloc =
match alloc with
"vmalloc" -> "vmalloc_array"
| "vzalloc" -> "vcalloc"
| _ -> failwith "unknown"
@@
size_t e1,e2;
constant C1, C2;
expression E1, E2, COUNT, x1, x2, x3;
typedef u8;
typedef __u8;
type t = {u8,__u8,char,unsigned char};
identifier alloc = {vmalloc,vzalloc};
fresh identifier realloc = script:ocaml(alloc) { rename alloc };
@@
(
alloc(x1*x2*x3)
|
alloc(C1 * C2)
|
alloc((sizeof(t)) * (COUNT), ...)
|
- alloc((e1) * (e2))
+ realloc(e1, e2)
|
- alloc((e1) * (COUNT))
+ realloc(COUNT, e1)
|
- alloc((E1) * (E2))
+ realloc(E1, E2)
)
// </smpl>
Signed-off-by: Julia Lawall <[email protected]>
Reviewed-by: Thomas Zimmermann <[email protected]>
Signed-off-by: Noralf Trønnes <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Instead of modifying the device info on the fly, use static const mock
device info.
It's not okay to modify device info at runtime; we've added separate
runtime info for info that needs to be modified at runtime. We've added
safeguards to device info to prevent it from being modified, but commit
5e352e32aec2 ("drm/i915: preparation for using PAT index") just cast the
const away and modified it anyway. This prevents device info from being
moved to rodata.
Fixes: 5e352e32aec2 ("drm/i915: preparation for using PAT index")
Suggested-by: Tvrtko Ursulin <[email protected]>
Cc: Fei Yang <[email protected]>
Cc: Andi Shyti <[email protected]>
Cc: Andrzej Hajda <[email protected]>
Cc: Matt Roper <[email protected]>
Signed-off-by: Jani Nikula <[email protected]>
Reviewed-by: Tvrtko Ursulin <[email protected]>
Reviewed-by: Andi Shyti <[email protected]>
Reviewed-by: Andrzej Hajda <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/b0db62045a96a3fd4cf123685da88cc777f9b485.1687878757.git.jani.nikula@intel.com
(cherry picked from commit ecc7a3ce078a209a62af4c53ffb7370620f65c24)
Signed-off-by: Tvrtko Ursulin <[email protected]>
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The multiplication got replaced by an addition in some cleanup.
This means we never write the correct data to some of the BDW
PSR data registers and thus we fail to actually wake up the
panel from PSR.
Fixes: 4ab4fa103217 ("drm/i915/psr: Make PSR registers relative to transcoders")
Signed-off-by: Ville Syrjälä <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by: Jouni Högander <[email protected]>
(cherry picked from commit 460dc4ba1442b3e5e543328d11db2702b98d3d7c)
Signed-off-by: Tvrtko Ursulin <[email protected]>
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When checking if the workarounds were applied successfully, the
read-back mask should also contain the bits being set: it's possible
that in a call to wa_write_clr_set(), the cleared bits are not a
superset of the set bits.
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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The comment on the parameter being 0 to avoid the read back doesn't
apply as this is not a call to wa_add(), but rather to
wa_write_clr_set(). So, this register is actually checked and it's
according to the Bspec that the register is RW, not RO.
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Contrary to GEN12_FF_MODE2, platforms using XEHP_FF_MODE2 are not
affected by Wa_1608008084, hence read back can be enabled.
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Now that non-masked registers are already read before programming the
context reads, the additional read became redudant, so remove it.
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Most of the context workarounds tweak masked registers, but not all. For
masked registers, when writing the value it's sufficient to just write
the wa->set_bits since that will take care of both the clr and set bits
as well as not overwriting other bits.
However there are some workarounds, the registers are non-masked. Up
until now the driver was simply emitting a MI_LOAD_REGISTER_IMM with the
set_bits to program the register via the GPU in the WA bb. This has the
side effect of overwriting the content of the register outside of bits
that should be set and also doesn't handle the bits that should be
cleared.
Kenneth reported that on DG2, mesa was seeing a weird behavior due to
the kernel programming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With
the GPU idle, that register could be read via intel_reg as 0x00e001ff,
but during a 3D workload it would change to 0x0000007f. So the
programming of that tuning was affecting more than the bits in
L3_PWM_TIMER_INIT_VAL_MASK. Matt Roper noticed the lack of rmw for the
context workarounds due to the use of MI_LOAD_REGISTER_IMM.
So, for registers that are not masked, read its value via mmio, modify
and then set it in the buffer to be written by the GPU. This should take
care in a simple way of programming just the bits required by the
tuning/workaround. If in future there are registers that involved that
can't be read by the CPU, a more complex approach may be required like
a) issuing additional instructions to read and modify; or b) scan the
golden context and patch it in place before saving it; or something
else. But for now this should suffice.
Scanning the context workarounds for all platforms, these are the
impacted ones with the respective registers
mtl: DRAW_WATERMARK
mtl/dg2: XEHP_L3SQCREG5, XEHP_FF_MODE2
ICL has some non-masked registers in the context workarounds:
GEN8_L3CNTLREG, IVB_FBC_RT_BASE and VB_FBC_RT_BASE_UPPER, but there
shouldn't be an impact. The first is already being manually read and the
other 2 are intentionally overwriting the entire register. Same
reasoning applies to GEN12_FF_MODE2: the WA is intentionally
overwriting all the bits to avoid a read-modify-write.
v2: Reword commit message wrt GEN12_FF_MODE2 and the changed behavior
on preparatory patches.
v3: Also skip reading if clear|set bits covers everything
Cc: Kenneth Graunke <[email protected]>
Cc: Matt Roper <[email protected]>
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23783#note_1968971
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Right now context workarounds don't do a rmw and instead only write to
the register. Since 2 separate programmings to the same register are
coalesced into a single write, this is not problematic for
GEN12_FF_MODE2 since both TDS and GS timer are going to be written
together and the other remaining bits be zeroed.
However in order to fix other workarounds that may want to preserve the
unrelated bits in the same register, context workarounds need to
be changed to a rmw. To prepare for that, move the programming of
GEN12_FF_MODE2 to a single place so the value passed for "clear" can
be all the bits. Otherwise the second workaround would be dropped as
it'd be detected as overwriting a previously programmed workaround.
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Move helper function to get all the forcewakes required by the wa list
to the top, so it can be re-used by other functions.
Signed-off-by: Lucas De Marchi <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Some Android CTS is testing if the signaling time keeps consistent
during merges.
v2: use the current time if the fence is still in the signaling path and
the timestamp not yet available.
v3: improve comment, fix one more case to use the correct timestamp
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Luben Tuikov <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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Wait until the command transfer FIFO is empty before loading in the next
command. The previous behavior where the code waited until command transfer
FIFO was not full suffered from transfer corruption, where the last command
in the FIFO could be overwritten in case the FIFO indicates not full, but
also does not have enough space to store another transfer yet.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Tested-by: Jagan Teki <[email protected]> # imx8mm-icore
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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fence Decrements the reference count before exiting.
Avoid Race Vulnerabilities for fence use-after-free.
v2 (chk): actually fix the use after free and not just move it.
Signed-off-by: shanzhulig <[email protected]>
Signed-off-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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fluctuation
An intentional delay is added on soft ctf triggered. Then there will
be a double check for the GPU temperature before taking further
action. This can avoid unintended shutdown due to temperature
momentary fluctuation.
Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Preparation for coming optimization which eliminates the influence of
GPU temperature momentary fluctuation.
Signed-off-by: Evan Quan <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This version brings along the following:
- Improve debugging mechanism for Gaming FAMS
- Add monitor specific edid quirks
- Fixes for Phantom pipe
- Fixes for Shapper LUT
- Clean up asserts
Acked-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Aric Cyr <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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[Description]
- A full update is required if the number of planes for a given
stream changes
- The new fast update path only checked for stream and plane updates,
but there could be a plane addition or removal without one of the
stream and plane updates triggering a full update
- Add an explicit check for number of planes changing for a full update
Reviewed-by: Samson Tam <[email protected]>
Acked-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alvin Lee <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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