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2023-07-27drm/msm/dpu: Refactor printing of main blocks in device core dumpRyan McCann1-8/+8
Currently, the names of main blocks are hardcoded into the msm_disp_snapshot_add_block function rather than using the name that already exists in the catalog. Change this to take the name directly from the catalog instead of hardcoding it. Signed-off-by: Ryan McCann <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/546194/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2023-07-27drm/msm/dpu: Remove redundant prefix/suffix in name of sub-blocksRyan McCann1-25/+25
For a device core dump, the registers of sub-blocks are printed under a title formatted as <mainBlkName_sblkName>. For example, the csc sub-block for an SSPP main block "sspp_0" would be printed "sspp_0_sspp_csc0". The title is clearly redundant due to the duplicate "sspp" and "0" that exist in both the mainBlkName and sblkName. To eliminate this redundancy, remove the secondary "sspp" and "0" that exist in the sub-block name by elimanting the "sspp_" prefix and the concatenation of "num" that results in the redundant "0" suffix. Remove num parameter altogether from relevant macros as a consequence of it no longer being used. Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Ryan McCann <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/546198/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2023-07-27drm/msm/dpu: Define names for unnamed sblksRyan McCann1-10/+10
Some sub-blocks in the hw catalog have not been given a name, so when the registers from that block are dumped, there is no name to reference. Define names for relevant sub-blocks to fix this. Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Ryan McCann <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/546199/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2023-07-27drm/msm/dpu: Drop unused num argument from relevant macrosRyan McCann1-10/+10
Drop unused parameter "num" from VIG_SBLK_NOSCALE and DMA sub-block macros. Update calls to relevant macros to reflect change. Reviewed-by: Abhinav Kumar <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Ryan McCann <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/546196/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2023-07-27drm/msm: Update dev core dump to not print backwardsRyan McCann1-1/+1
Device core dump add block method adds hardware blocks to dumping queue with stack behavior which causes the hardware blocks to be printed in reverse order. Change the addition to dumping queue data structure from "list_add" to "list_add_tail" for FIFO queue behavior. Fixes: 98659487b845 ("drm/msm: add support to take dpu snapshot") Reviewed-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Abhinav Kumar <[email protected]> Signed-off-by: Ryan McCann <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/546200/ Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dmitry Baryshkov <[email protected]>
2023-07-27drm/ttm: check null pointer before accessing when swappingGuchun Chen1-1/+2
Add a check to avoid null pointer dereference as below: [ 90.002283] general protection fault, probably for non-canonical address 0xdffffc0000000000: 0000 [#1] PREEMPT SMP KASAN NOPTI [ 90.002292] KASAN: null-ptr-deref in range [0x0000000000000000-0x0000000000000007] [ 90.002346] ? exc_general_protection+0x159/0x240 [ 90.002352] ? asm_exc_general_protection+0x26/0x30 [ 90.002357] ? ttm_bo_evict_swapout_allowable+0x322/0x5e0 [ttm] [ 90.002365] ? ttm_bo_evict_swapout_allowable+0x42e/0x5e0 [ttm] [ 90.002373] ttm_bo_swapout+0x134/0x7f0 [ttm] [ 90.002383] ? __pfx_ttm_bo_swapout+0x10/0x10 [ttm] [ 90.002391] ? lock_acquire+0x44d/0x4f0 [ 90.002398] ? ttm_device_swapout+0xa5/0x260 [ttm] [ 90.002412] ? lock_acquired+0x355/0xa00 [ 90.002416] ? do_raw_spin_trylock+0xb6/0x190 [ 90.002421] ? __pfx_lock_acquired+0x10/0x10 [ 90.002426] ? ttm_global_swapout+0x25/0x210 [ttm] [ 90.002442] ttm_device_swapout+0x198/0x260 [ttm] [ 90.002456] ? __pfx_ttm_device_swapout+0x10/0x10 [ttm] [ 90.002472] ttm_global_swapout+0x75/0x210 [ttm] [ 90.002486] ttm_tt_populate+0x187/0x3f0 [ttm] [ 90.002501] ttm_bo_handle_move_mem+0x437/0x590 [ttm] [ 90.002517] ttm_bo_validate+0x275/0x430 [ttm] [ 90.002530] ? __pfx_ttm_bo_validate+0x10/0x10 [ttm] [ 90.002544] ? kasan_save_stack+0x33/0x60 [ 90.002550] ? kasan_set_track+0x25/0x30 [ 90.002554] ? __kasan_kmalloc+0x8f/0xa0 [ 90.002558] ? amdgpu_gtt_mgr_new+0x81/0x420 [amdgpu] [ 90.003023] ? ttm_resource_alloc+0xf6/0x220 [ttm] [ 90.003038] amdgpu_bo_pin_restricted+0x2dd/0x8b0 [amdgpu] [ 90.003210] ? __x64_sys_ioctl+0x131/0x1a0 [ 90.003210] ? do_syscall_64+0x60/0x90 Fixes: a2848d08742c ("drm/ttm: never consider pinned BOs for eviction&swap") Tested-by: Mikhail Gavrilov <[email protected]> Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Christian König <[email protected]>
2023-07-26drm/msm: Disallow submit with fence id 0Rob Clark1-1/+1
A fence id of zero is expected to be invalid, and is not removed from the fence_idr table. If userspace is requesting to specify the fence id with the FENCE_SN_IN flag, we need to reject a zero fence id value. Fixes: 17154addc5c1 ("drm/msm: Add MSM_SUBMIT_FENCE_SN_IN") Signed-off-by: Rob Clark <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/549180/
2023-07-26drm/ssd130x: Allocate buffer in the plane's .atomic_check() callbackJavier Martinez Canillas2-40/+121
Drivers are not allowed to fail after drm_atomic_helper_swap_state() has been called and the new atomic state is stored into the current sw state. Since the struct ssd130x_device .data_array is allocated in the encoder's .atomic_enable callback, the operation can fail and this is after the new state has been stored. So it can break an atomic mode settings assumption. Fix this by having custom helpers to allocate, duplicate and destroy the plane state, that will take care of allocating and freeing these buffers. Suggested-by: Maxime Ripard <[email protected]> Signed-off-by: Javier Martinez Canillas <[email protected]> Acked-by: Maxime Ripard <[email protected]> Tested-by: Geert Uytterhoeven <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-26drm/ssd130x: Inline the ssd130x_buf_{alloc, free}() function helpersJavier Martinez Canillas1-35/+20
There is only a single caller for both helper functions and these don't do much other than allocate and free two buffers, so let's just inline them. Suggested-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Javier Martinez Canillas <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-26drm/i915/gt: Support aux invalidation on all enginesAndi Shyti3-45/+41
Perform some refactoring with the purpose of keeping in one single place all the operations around the aux table invalidation. With this refactoring add more engines where the invalidation should be performed. Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Signed-off-by: Andi Shyti <[email protected]> Cc: Jonathan Cavitt <[email protected]> Cc: Matt Roper <[email protected]> Cc: <[email protected]> # v5.8+ Reviewed-by: Andrzej Hajda <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-26drm/i915/gt: Poll aux invalidation register bit on invalidationJonathan Cavitt2-5/+13
For platforms that use Aux CCS, wait for aux invalidation to complete by checking the aux invalidation register bit is cleared. Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Signed-off-by: Jonathan Cavitt <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Cc: <[email protected]> # v5.8+ Reviewed-by: Nirmoy Das <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Reviewed-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-26drm/i915/gt: Enable the CCS_FLUSH bit in the pipe control and in the CSAndi Shyti2-0/+12
Enable the CCS_FLUSH bit 13 in the control pipe for render and compute engines in platforms starting from Meteor Lake (BSPEC 43904 and 47112). For the copy engine add MI_FLUSH_DW_CCS (bit 16) in the command streamer. Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Requires: 8da173db894a ("drm/i915/gt: Rename flags with bit_group_X according to the datasheet") Signed-off-by: Andi Shyti <[email protected]> Cc: Jonathan Cavitt <[email protected]> Cc: Nirmoy Das <[email protected]> Cc: <[email protected]> # v5.8+ Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-26drm/i915/gt: Rename flags with bit_group_X according to the datasheetAndi Shyti2-23/+29
In preparation of the next patch align with the datasheet (BSPEC 47112) with the naming of the pipe control set of flag values. The variable "flags" in gen12_emit_flush_rcs() is applied as a set of flags called Bit Group 1. Define also the Bit Group 0 as bit_group_0 where currently only PIPE_CONTROL0_HDC_PIPELINE_FLUSH bit is set. Signed-off-by: Andi Shyti <[email protected]> Cc: <[email protected]> # v5.8+ Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-26drm/i915/gt: Ensure memory quiesced before invalidationJonathan Cavitt1-1/+5
All memory traffic must be quiesced before requesting an aux invalidation on platforms that use Aux CCS. Fixes: 972282c4cf24 ("drm/i915/gen12: Add aux table invalidate for all engines") Requires: a2a4aa0eef3b ("drm/i915: Add the gen12_needs_ccs_aux_inv helper") Signed-off-by: Jonathan Cavitt <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Cc: <[email protected]> # v5.8+ Reviewed-by: Nirmoy Das <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-26drm/i915: Add the gen12_needs_ccs_aux_inv helperAndi Shyti1-3/+15
We always assumed that a device might either have AUX or FLAT CCS, but this is an approximation that is not always true, e.g. PVC represents an exception. Set the basis for future finer selection by implementing a boolean gen12_needs_ccs_aux_inv() function that tells whether aux invalidation is needed or not. Currently PVC is the only exception to the above mentioned rule. Requires: 059ae7ae2a1c ("drm/i915/gt: Cleanup aux invalidation registers") Signed-off-by: Andi Shyti <[email protected]> Cc: Matt Roper <[email protected]> Cc: Jonathan Cavitt <[email protected]> Cc: <[email protected]> # v5.8+ Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-26drm/i915/gt: Cleanup aux invalidation registersAndi Shyti3-15/+15
Fix the 'NV' definition postfix that is supposed to be INV. Take the chance to also order properly the registers based on their address and call the GEN12_GFX_CCS_AUX_INV address as GEN12_CCS_AUX_INV like all the other similar registers. Remove also VD1, VD3 and VE1 registers that don't exist and add BCS0 and CCS0. Signed-off-by: Andi Shyti <[email protected]> Cc: <[email protected]> # v5.8+ Reviewed-by: Nirmoy Das <[email protected]> Reviewed-by: Andrzej Hajda <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-26drm/i915: Use the i915_vma_flush_writes helperTvrtko Ursulin1-4/+2
We can use the existing helper in flush_write_domain() and save some lines of code. Signed-off-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-26drm/i915/hotplug: Reduce SHPD_FILTER to 250usSuraj Kandpal2-1/+4
On TGP, the RTC (always running) was reduced from 3MHz to 32KHz. As a result of this change, when HPD active going low pulse or HPD IRQ is presented and the refclk (19.2MHz) is not toggling already toggling, there is a 60 to 90us synchronization delay which effectively reduces the duration of the IRQ pulse to less than the programmed 500us filter value and the hot plug interrupt is NOT registered. Solution was to Reduce SHPD_FILTER to 250us for ADL and above. This solution was derived when the below patch was floated. [1]https://patchwork.freedesktop.org/patch/532187 and after some internal discussion Ville's suggestion made sense. Bspec: 68970 Cc: Uma Shankar <[email protected]> Cc: Ville Syrjala <[email protected]> Suggested-by: Ville Syrjala <[email protected]> Signed-off-by: Suraj Kandpal <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Uma Shankar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-25drm/amdgpu: Restore HQD persistent state registerLijo Lazar1-1/+2
On GFX v9.4.3, compute queue MQD is populated using the values in HQD persistent state register. Hence don't clear the values on module unload, instead restore it to the default reset value so that MQD is initialized correctly during next module load. In particular, preload flag needs to be set on compute queue MQD, otherwise it could cause uninitialized values being used at device reset state resulting in EDC. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Unlock on error path in ↵Dan Carpenter1-1/+1
dm_handle_mst_sideband_msg_ready_event() This error path needs to unlock the "aconnector->handle_mst_msg_ready" mutex before returning. Fixes: 4f6d9e38c4d2 ("drm/amd/display: Add polling method to handle MST reply packet") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Exit idle optimizations before attempt to access PHYLeo Chen1-0/+3
[Why & How] DMUB may hang when powering down pixel clocks due to no dprefclk. It is fixed by exiting idle optimization before the attempt to access PHY. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Leo Chen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Don't apply FIFO resync W/A if rdivider = 0Alvin Lee1-1/+4
[Description] It is not valid to set the WDIVIDER value to 0, so do not re-write to DISPCLK_WDIVIDER if the current value is 0 (i.e., it is at it's initial value and we have not made any requests to change DISPCLK yet). Reviewed-by: Saaem Rizvi <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Guard DCN31 PHYD32CLK logic against chip familyGeorge Shen1-1/+2
[Why] Current yellow carp B0 PHYD32CLK logic is incorrectly applied to other ASICs. [How] Add guard to check chip family is yellow carp before applying logic. Reviewed-by: Hansen Dsouza <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/smu: use AverageGfxclkFrequency* to replace previous GFX Curr ClockJane Jian1-1/+1
Report current GFX clock also from average clock value as the original CurrClock data is not valid/accurate any more as per FW team Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd: Fix an error handling mistake in psp_sw_init()Mario Limonciello1-3/+3
If the second call to amdgpu_bo_create_kernel() fails, the memory allocated from the first call should be cleared. If the third call fails, the memory from the second call should be cleared. Fixes: b95b5391684b ("drm/amdgpu/psp: move PSP memory alloc from hw_init to sw_init") Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Fix infinite loop in gfxhub_v1_2_xcc_gart_enable (v2)Victor Lu1-4/+1
An instance of for_each_inst() was not changed to match its new behaviour and is causing a loop. v2: remove tmp_mask variable Fixes: b579ea632fca ("drm/amdgpu: Modify for_each_inst macro") Signed-off-by: Victor Lu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdkfd: fix trap handling work around for debuggingJonathan Kim3-7/+10
Update the list of devices that require the cwsr trap handling workaround for debugging use cases. Signed-off-by: Jonathan Kim <[email protected]> Acked-by: Ruili Ji <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/ast: Do not enable PCI resources multiple timesThomas Zimmermann1-21/+0
Remove ast_init_pci_config() as the ast driver already enables the PCI resources by calling pcim_enable_device(). Suggested-by: Sui Jingfeng <[email protected]> Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Tested-by: Sui Jingfeng <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-07-25drm/amdgpu: Restore HQD persistent state registerLijo Lazar1-1/+2
On GFX v9.4.3, compute queue MQD is populated using the values in HQD persistent state register. Hence don't clear the values on module unload, instead restore it to the default reset value so that MQD is initialized correctly during next module load. In particular, preload flag needs to be set on compute queue MQD, otherwise it could cause uninitialized values being used at device reset state resulting in EDC. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/radeon: add missing spaces before ';'Ran Sun1-2/+2
ERROR: space required after that ';' (ctx:BxV) Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/radeon/si_dpm: open brace '{' following struct go on the same lineRan Sun1-34/+17
ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4 to acquire gpu_metricsWenyou Yang3-9/+172
To acquire the voltage and current info from gpu_metrics interface, but gpu_metrics_v2_3 doesn't contain them, and to be backward compatible, add new gpu_metrics_v2_4 structure. Reviewed-by: Mario Limonciello <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Wenyou Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: load sdma ucode in the guest machineYuanShang3-8/+14
[why] User mode driver need to check the sdma ucode version to see whether the sdma engine supports a new type of PM4 packet. In SRIOV, sdma is loaded by the host. And, there is no way to check the sdma ucode version of CHIP_NAVI12 and CHIP_SIENNA_CICHLID of the host in the guest machine. [how] Load the sdma ucode for CHIP_NAVI12 and CHIP_SIENNA_CICHLID in the guest machine. Signed-off-by: YuanShang <[email protected]> Reviewed-By: Horace Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Use seq_puts() instead of seq_printf()Srinivasan Shanmugam1-11/+11
For a constant format without additional arguments, use seq_puts() instead of seq_printf(). Also, it fixes the following warning. WARNING: Prefer seq_puts to seq_printf And other style fixes: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: Block comments should align the * on each line Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Update min() to min_t() in 'amdgpu_info_ioctl'Srinivasan Shanmugam1-6/+8
Fixes the following: WARNING: min() should probably be min_t(size_t, size, sizeof(ip)) + ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip))); And other style fixes: WARNING: Prefer 'unsigned int' to bare use of 'unsigned' WARNING: Missing a blank line after declarations Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Remove else after return in 'is_fru_eeprom_supported'Srinivasan Shanmugam1-4/+5
Expressions under 'else' branch under case 'CHIP_SIENNA_CICHLID' in function 'is_fru_eeprom_supported' are executed whenever the expression in 'if' is False. Otherwise, return from case occurs. Therefore, there is no need in 'else', and it has been removed. Fixes the following: WARNING: else is not generally useful after a break or return + return false; + } else { Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Remove else after return in 'dm_vblank_get_counter' & ↵Srinivasan Shanmugam1-14/+17
'amdgpu_dm_backlight_get_level' Expressions under 'else' branch in function 'dm_vblank_get_counter' & 'amdgpu_dm_backlight_get_level' are executed whenever the expression in 'if' is False. Otherwise, return from function occurs. Therefore, there is no need in 'else', and it has been removed. Fixes the following: WARNING: else is not generally useful after a break or return + return 0; + else { WARNING: else is not generally useful after a break or return + return convert_brightness_to_user(&caps, avg); + } else { Cc: Rodrigo Siqueira <[email protected]> Cc: Aurabindo Pillai <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Add -ENOMEM error handling when there is no memorySrinivasan Shanmugam4-9/+17
Return -ENOMEM, when there is no sufficient dynamically allocated memory Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: Check APU flag to disable RASStanley.Yang1-1/+2
Only disable RAS by default for aqua vanjaram on APU platform. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: fix the indexing issue during rlcg access ctrl initShiwu Zhang1-4/+3
In case that the GET_INST() is used for looping, only loops for the times of actual num of xcc, otherwise GET_INST() will return the invalid index, a.k.a -1 And also remove the redundant mask checking in case of GET_INST() Signed-off-by: Shiwu Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: add VISIBLE info in amdgpu_bo_print_infoPierre-Eric Pelloux-Prayer1-13/+21
This allows tools to distinguish between VRAM and visible VRAM. Use the opportunity to fix locking before accessing bo. v2: squash in unused variable fix Reviewed-by: Christian König <[email protected]> Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdkfd: avoid svm dump when dynamic debug disabledAlex Sierra1-1/+3
Set dynamic_svm_range_dump macro to avoid iterating over SVM lists from svm_range_debug_dump when dynamic debug is disabled. Otherwise, it could drop performance, specially with big number of SVM ranges. Make sure both svm_range_set_attr and svm_range_debug_dump functions are dynamically enabled to print svm_range_debug_dump debug traces. Signed-off-by: Alex Sierra <[email protected]> Tested-by: Alex Sierra <[email protected]> Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/radeon: ERROR: "foo * bar" should be "foo *bar"Ran Sun1-2/+2
Fix two occurrences of the checkpatch.pl error: ERROR: "foo * bar" should be "foo *bar" Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdgpu: open brace '{' following struct go on the same lineRan Sun1-2/+1
ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/pm: open brace '{' following struct go on the same lineRan Sun1-14/+7
ERROR: open brace '{' following struct go on the same line Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd: open brace '{' following struct go on the same lineRan Sun1-4/+2
Fix the checkpatch error as open brace '{' following struct should go on the same line. Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Unlock on error path in ↵Dan Carpenter1-1/+1
dm_handle_mst_sideband_msg_ready_event() This error path needs to unlock the "aconnector->handle_mst_msg_ready" mutex before returning. Fixes: bb4fa525f327 ("drm/amd/display: Add polling method to handle MST reply packet") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: 3.2.244Aric Cyr1-1/+1
This version brings along following fixes: - Fix underflow issue on 175hz timing - Add interface to modify DMUB panel power options - Remove check for default eDP panel_mode - Add new sequence for 4-lane HBR3 on vendor specific retimers - Update DPG test pattern programming - Correct unit conversion for vstartup - Exit idle optimizations before attempt to access PHY - Refactor recout calculation with a more generic formula - Read down-spread percentage from lut to adjust dprefclk. - Don't apply FIFO resync W/A if rdivider = 0 - Prevent invalid pipe connections - Rearrange dmub_cmd defs order - Add VESA SCR case for default aux backlight - Guard DCN31 PHYD32CLK logic against chip family - Correct grammar mistakes Acked-by: Alex Hung <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Fix underflow issue on 175hz timingLeo Ma1-1/+6
[Why] Screen underflows happen on 175hz timing for 3 plane overlay case. [How] Based on dst y prefetch value clamp to equ or oto for bandwidth calculation. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Leo Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/display: Add interface to modify DMUB panel power optionsPaul Hsieh2-0/+15
[Why] This option can vary depending on the panel and may be required to be called during sink detection phase before transmitter control. [How] Allow modify the bit depending on the eDP panel connected with a new interface. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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