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2023-09-20drm/amdgpu: update IP count INFO querySathishkumar S1-29/+61
update the query to return the number of functional instances where there is more than an instance of the requested type and for others continue to return one. v2: count must reflect the actual number of engines (Alex) v3: fix wrong number of engines for vcn (Alex) Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Fix false positive error logStanley.Yang1-5/+5
It should first check block ras obj whether be set, it should return 0 directly if block ras obj or hw_ops is not set. If block doesn't support RAS just return 0 is fine. Changed from V1: return 0 directly if block ras obj or hw ops is not set Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu/jpeg: skip set pg for sriovVignesh Chander2-11/+12
Host handles PG. Signed-off-by: Vignesh Chander <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdkfd: Use gpu_offset for user queue's wptrYuBiao Wang1-1/+1
Directly use tbo's start address will miss the domain start offset. Need to use gpu_offset instead. Signed-off-by: YuBiao Wang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: 3.2.251Aric Cyr1-1/+1
Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: [FW Promotion] Release 0.0.183.0Anthony Koo1-0/+31
- Add new IPS ALLOW masks - Add new Replay power configuration options Tested-by: Daniel Wheeler <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Fix MST recognizes connected displays as oneMuhammad Ahmed2-25/+74
MST now recognizes both connected displays Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: fix some non-initialized register mask and settingCharlene Liu6-160/+33
Fix some non-initialized register mask and update golden setting. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Duncan Ma <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Enable replay for dcn35Roman Li1-0/+1
Enable the display replay feature for DCN35. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Qingqing Zhuo <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Add option to flip ODM optimizationGabe Teeger1-0/+1
Add a config option to disable odm dispclk optimization for debug purpose. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: disable IPSMuhammad Ahmed1-0/+1
Disable IPS by default till it is ready. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Duncan Ma <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Add IPS control flagSung Joon Kim5-35/+51
[why] Currently, driver is not aware if IPS is supported. After PMFW helps implement new message query functionality, driver will set IPS capability flag. [how] Create new SMU hook function to query IPS capability. Based on the cap, set appropriate flags to false for power-gating purposes. This will avoid keeping SMU busy and offloading tasks to DMUB/driver. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Update driver and IPS interopDuncan Ma2-0/+6
[Why] Two issues fixed: 1. Currently, driver does not allow idle prior to PSR entry. Once PSR1+IPS is enabled, there is intermittent hang due to DCN access from IrqMgr during IPS2. 2. Driver is sending multiple commands to PMFW and dmcub to exit IPS even during IPS0. [How] 1. Set driver allow optimization prior to entering PSR mode with the condition for eDP display only. Unregister all interrupts before allowing driver idle and re-register interrupts when exiting from idle. This will prevent IrqMgr to access DCN during IPS2. 2. Block sending PMFW and dmcub exit low power state commands when driver is not in idle state. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Reviewed-by: Jun Lei <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Correct z8 watermark maskCharlene Liu2-10/+8
Correct z8_watermark mask from 16bit to 20bit. Also, do not set dcn35 dprefclk in clk_mgr_construct. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Muhammad Ahmed <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: STREAM_MAPPER_CONTROL register offset on DCN35Artem Grishin1-1/+2
[Why] The STREAM_MAPPER_CONTROL register offset was left uninitialized, causing warning in the driver log at runtime [How] A temporary solution to add it into dcn35_create_resource_pool. [TODO] Remove duplication between SE_DCN35_REG_LIST_RI in dcn35_resource.h and SE_DCN35_REG_LIST in dcn35_dio_stream_encoder.h Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Artem Grishin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Update pipe resource interfaces for DCN35Wenjing Liu1-0/+1
Pipe resource interfaces were changed. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Add DPIA Link Encoder Assignment Fix for DCN35Mustapha Ghaddar1-0/+23
For DPIA we should have preferred DIG assignment based on DPIA selected as per the ASIC design Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Mustapha Ghaddar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: fix static screen detection setting for DCN35Sung-huai Wang1-1/+1
set_static_screen_control has been updated for DCN3 series. Update it for DCN35. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung-huai Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Add pointer check before function callSung Joon Kim1-1/+3
Call to immediate_disable_crtc was not checked before calling, exposing a potential null pointer hang. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Enable DCLK_DS from driver by defaultMuhammad Ahmed1-3/+0
PMFW ungate this feature, this can be enabled now Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Add DCN35 case for dc_clk_mgr_createQingqing Zhuo1-0/+13
Add DCN 35 case for dc_clk_mgr_create. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Add z8_marks related in dml for DCN35Charlene Liu2-1/+36
Add z8 watermarks to struct for DCN35. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Fix dig register undefinedDuncan Ma1-1/+1
[Why] Some of the stream encoder registers have register offset address 0. It is causing no display in some scenarios due to DIG_FE was not setup correctly and was not enabled. [How] Fix stream encoder register define list. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: fix the ability to use lower resolution modes on eDPHamza Mahfooz1-2/+2
On eDP we can receive invalid modes from dm_update_crtc_state() for entirely new streams for which drm_mode_set_crtcinfo() shouldn't be called on. So, instead of calling drm_mode_set_crtcinfo() from within create_stream_for_sink() we can instead call it from amdgpu_dm_connector_mode_valid(). Since, we are guaranteed to only call drm_mode_set_crtcinfo() for valid modes from that function (invalid modes are rejected by that callback) and that is the only user of create_validate_stream_for_sink() that we need to call drm_mode_set_crtcinfo() for (as before commit cb841d27b876 ("drm/amd/display: Always pass connector_state to stream validation"), that is the only place where create_validate_stream_for_sink()'s dm_state was NULL). Cc: [email protected] Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2693 Fixes: cb841d27b876 ("drm/amd/display: Always pass connector_state to stream validation") Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Temporarily disable clock gatingCharlene Liu1-0/+1
Temporarily disable dchubbub clock gating, registers: .DISPCLK_R_DCHUBBUB_GATE_DIS .DCFCLK_R_DCHUBBUB_GATE_DIS need to follow up with sequence issue. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Leo Chen <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: disable clock gating logicMuhammad Ahmed1-2/+2
Disable clock gating logic. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Add reset for SYMCLKC_FE_SRC_SELTaimur Hassan1-10/+15
To prevent confusion after symclk has already been disabled. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Rework coredump to use memory dynamicallyAndré Almeida2-28/+49
Instead of storing coredump information inside amdgpu_device struct, move if to a proper separated struct and allocate it dynamically. This will make it easier to further expand the logged information. Signed-off-by: André Almeida <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Remove unused display_content_supportJoshua Ashton2-15/+0
This was never filled in and thus never truly used. Checking the EDID for content_type support is not required for sending the avi infoframe packet. v2: - rebase to amd-staging-drm-next Reviewed-by: Melissa Wen <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Hook up 'content type' property for HDMIJoshua Ashton3-48/+54
Implements the 'content type' property for HDMI connectors. Verified by checking the avi infoframe on a connected TV. This also simplifies a lot of the code in that area as well, there were a lot of temp variables doing very little and unnecessary logic that was quite confusing. It is not necessary to check for support in the EDID before sending a 'content type' value in the avi infoframe also. v2: - rebase to amd-staging-drm-next - mark CRTC state for reset if content_type differs Reviewed-by: Harry Wentland <[email protected]> (v1) Signed-off-by: Joshua Ashton <[email protected]> Co-developed-by: Melissa Wen <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: fix a memory leak in amdgpu_ras_feature_enableCong Liu1-0/+1
This patch fixes a memory leak in the amdgpu_ras_feature_enable() function. The leak occurs when the function sends a command to the firmware to enable or disable a RAS feature for a GFX block. If the command fails, the kfree() function is not called to free the info memory. Fixes: 9f051d6ff13f ("drm/amdgpu: Free ras cmd input buffer properly") Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Cong Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Fix vbios version string searchLijo Lazar1-1/+18
Search for vbios version string in STRING_OFFSET-ATOM_ROM_HEADER region first. If those offsets are not populated, use the hardcoded region. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20Revert "drm/amdgpu: Report vbios version instead of PN"Lijo Lazar1-1/+1
This reverts commit 7748ce5b69581325cae40c2134088820f0957902. vbios_version sysfs node is used to identify Part Number also. Revert to the same so that it doesn't break scripts/software which parse this. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/pm: add smu_13_0_6 mca dump supportYang Wang2-0/+559
v1: implement smu_v13_0_6 mca bank interface. v2: - remove unnecessary lock - move MCMP1_* macros to mp_13_0_6_sh_mask.h file Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/pm: update smu_v13_0_6 ppsmc headerYang Wang4-2/+100
update smu header to support mca dump interface. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Add EXT_COHERENT memory allocation flagsDavid Francis6-2/+18
These flags (for GEM and SVM allocations) allocate memory that allows for system-scope atomic semantics. On GFX943 these flags cause caches to be avoided on non-local memory. On all other ASICs they are identical in functionality to the equivalent COHERENT flags. Corresponding Thunk patch is at https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/pull/88 Reviewed-by: David Yat Sin <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdkfd: fix add queue process context clear without runtime enableJonathan Kim1-2/+4
There are cases where HSA runtime is not enabled through the AMDKFD_IOC_RUNTIME_ENABLE call when adding queues and the MES ADD_QUEUE API should clear the MES process context instead of SET_SHADER_DEBUGGER. Such examples are legacy HSA runtime builds that do not support the current exception handling and running KFD tests. The only time ADD_QUEUE.skip_process_ctx_clear is required is for debugger use cases where a debugged process is always runtime enabled when adding a queue. Tested-by: Shikai Guo <[email protected]> Signed-off-by: Jonathan Kim <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/i915: Implement transcoder LRR for TGL+Ville Syrjälä6-11/+70
Implement low refresh rate (LRR) where we change the vblank length by hand as requested, but otherwise keep the timing generator running in non-VRR mode (ie. fixed refresh rate). The panel itself must support VRR for this to work, and only TGL+ has the double buffred TRANS_VTOTAL.VTOTAL that we need to make the switch properly. The double buffer latching happens at the start of transcoders undelayed vblank. The other thing that we change is TRANS_VBLANK.VBLANK_END but the hardware entirely ignores that in DP mode. But I decided to keep writing it anyway just to avoid more special cases in readout/state check. v2: Document that TRANS_VBLANK.VBLANK_END is ignored by the hardware v3: Reconcile with VRR fastset Adjust update_lrr flag behaviour Make sure timings stay within VRR range v4: Fix up update_m_n vs. update_lrr rebase fail (Manasi) Drop DOUBLE_BUFFER_VACTIVE define as it's not needed (Manasi) TODO: Hook LRR into the automatic DRRS downclocking stuff? Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]>
2023-09-20drm/i915: Assert that VRR is off during vblank evasion if necessaryVille Syrjälä1-0/+4
Whenever we change the actual transcoder timings (clock via seamless M/N, full modeset, (or soon) vtotal via LRR) we want the timing generator to be in non-VRR during the commit. Warn if we forgot to turn VRR off prior to vblank evasion. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Update VRR parameters in fastsetVille Syrjälä1-8/+26
We should be able to change any of the VRR parameters during fastsets as long as we toggle VRR off at the start and then back on at the end. The transcoder will be running in non-VRR mode during the transition. Co-developed-by: Manasi Navare <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Sean Paul <[email protected]>
2023-09-20drm/i915: Disable VRR during seamless M/N changesVille Syrjälä1-2/+4
Make life less confusing by making sure VRR is disabled whenever we do any drastic changes to the display timings, such as seamless M/N changes. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Validate that the timings are within the VRR rangeVille Syrjälä1-2/+2
Let's assume there are some crazy displays where the high end of the VRR range ends up being lower than the refresh rate as determined by the actual timings. In that case when we toggle VRR on/off we would step outside the VRR range when toggling VRR on/off. Let's just make sure that never happens by not using VRR in such cases. If the user really wants VRR they should then select the timings to land within the VRR range. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Relocate is_in_vrr_range()Ville Syrjälä3-13/+14
Move is_in_vrr_range() into intel_vrr.c in anticipation of more users, and rename it accordingly. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Optimize out redundant M/N updatesVille Syrjälä1-1/+3
Don't perform a seamless M/N update if the values aren't actually changing. This avoids doing extra shenanigans during vblank evasion needlessly. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]>
2023-09-20drm/i915: Adjust seamless_m_n flag behaviourVille Syrjälä5-12/+17
Make the seamless_m_n flag more like the update_pipe fastset flag, ie. the flag will only be set if we need to do the seamless M/N update, and in all other cases the flag is cleared. Also rename the flag to update_m_n to make it more clear it's similar to update_pipe. I believe special casing seamless_m_n like this makes sense as it also affects eg. vblank evasion. We can potentially avoid some vblank evasion tricks, simplify some checks, and hopefully will help with the VRR vs. M/N mess. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]>
2023-09-20drm/i915: Enable VRR later during fastsetsVille Syrjälä2-20/+36
In order to reconcile seamless M/N updates with VRR we'll need to defer the fastset VRR enable to happen after the seamless M/N update (which happens during the vblank evade critical section). So just push the VRR enable to be the last thing during the update. This will also affect the vblank evasion as the transcoder will now still be running with the old VRR state during the vblank evasion. So just grab the timings always from the old crtc state during any non-modeset commit, and also grab the current state of VRR from the active timings (as we disable VRR before vblank evasion during fastsets). This also fixes vblank evasion for seamless M/N updates as we now properly account for the fact that the M/N update happens after vblank evasion. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Extract intel_crtc_vblank_evade_scanlines()Ville Syrjälä1-22/+31
Pull the vblank evasion scanline calculations into their own helper to declutter intel_pipe_update_start() a bit. Reviewed-by: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Change intel_pipe_update_{start,end}() calling conventionVille Syrjälä3-10/+18
We'll need to also look at the old crtc state in intel_pipe_update_start() so change the calling convention to just plumb in the full atomic state instead. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915: Move psr unlock out from the pipe update critical sectionVille Syrjälä1-4/+5
Do the PSR unlock after the vblank evade critcal section is fully over, not before. Cc: Manasi Navare <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Manasi Navare <[email protected]> Reviewed-by: Mitul Golani <[email protected]>
2023-09-20drm/i915/dsi: let HW maintain CLK_POSTWilliam Tseng1-12/+1
This change is to adjust TCLK-POST timing so DSI signaling can meet CTS specification. For clock lane, the TCLK-POST timing may be changed from 133.44 ns to 178.72 ns, which is greater than (60 ns+52*UI) and is conformed to the CTS standard. The computed UI is around 1.47 ns. v2: remove the change of HS-TRAIL. Cc: Ville Syrjala <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Vandita Kulkarni <[email protected]> Cc: Suraj Kandpal <[email protected]> Cc: Lee Shawn C <[email protected]> Signed-off-by: William Tseng <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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