aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu
AgeCommit message (Collapse)AuthorFilesLines
2023-10-19drm/ast: Move register constants to ast_reg.hThomas Zimmermann2-81/+101
Improve readability by putting all register constants into a separate header file. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_MISC_PORT_READ to AST_IO_VGAMR_RThomas Zimmermann2-2/+2
Rename AST_IO_MISC_PORT_READ to AST_IO_VGAMR_R to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_INPUT_STATUS1_READ to AST_IO_VGAIR1_RThomas Zimmermann2-4/+4
Rename AST_IO_INPUT_STATUS1_READ to AST_IO_VGAIR1_R to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_CRTC_PORT to AST_IO_VGACRIThomas Zimmermann8-162/+162
Rename AST_IO_CRTC_PORT to AST_IO_VGACRI to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_GR_PORT to AST_IO_VGAGRIThomas Zimmermann2-2/+2
Rename AST_IO_GR_PORT to AST_IO_VGAGRI to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_DAC_DATA to AST_IO_VGAPDRThomas Zimmermann2-4/+4
Rename AST_IO_DAC_DATA to AST_IO_VGAPDR to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_DAC_INDEX_WRITE to AST_IO_VGADWRThomas Zimmermann2-2/+2
Rename AST_IO_DAC_INDEX_WRITE to AST_IO_VGADWR to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_DAC_INDEX_READ to AST_IO_VGADRRThomas Zimmermann1-1/+1
Rename AST_IO_DAC_INDEX_READ to AST_IO_VGADRR to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_SEQ_PORT to AST_IO_VGASRIThomas Zimmermann2-12/+12
Rename AST_IO_VGA_SEQ_PORT to AST_IO_VGASRI to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_VGA_ENABLE_PORT to AST_IO_VGAERThomas Zimmermann2-3/+3
Rename AST_IO_VGA_ENABLE_PORT to AST_IO_VGAER to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_MISC_PORT_WRITE to AST_IO_VGAMR_WThomas Zimmermann3-4/+4
Rename AST_IO_MISC_PORT_WRITE to AST_IO_VGAMR_W to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/ast: Rename AST_IO_AR_PORT_WRITE to AST_IO_VGAARI_WThomas Zimmermann2-6/+6
Rename AST_IO_AR_PORT_WRITE to AST_IO_VGAARI_W to align naming in the driver with documentation. No functional changes. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Jocelyn Falempe <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19drm/amdgpu: ignore duplicate BOs againChristian König1-1/+2
Looks like RADV is actually hitting this. Signed-off-by: Christian König <[email protected]> Fixes: ca6c1e210aa7 ("drm/amdgpu: use the new drm_exec object for CS v3") Acked-by: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-19file: convert to SLAB_TYPESAFE_BY_RCUChristian Brauner1-3/+1
In recent discussions around some performance improvements in the file handling area we discussed switching the file cache to rely on SLAB_TYPESAFE_BY_RCU which allows us to get rid of call_rcu() based freeing for files completely. This is a pretty sensitive change overall but it might actually be worth doing. The main downside is the subtlety. The other one is that we should really wait for Jann's patch to land that enables KASAN to handle SLAB_TYPESAFE_BY_RCU UAFs. Currently it doesn't but a patch for this exists. With SLAB_TYPESAFE_BY_RCU objects may be freed and reused multiple times which requires a few changes. So it isn't sufficient anymore to just acquire a reference to the file in question under rcu using atomic_long_inc_not_zero() since the file might have already been recycled and someone else might have bumped the reference. In other words, callers might see reference count bumps from newer users. For this reason it is necessary to verify that the pointer is the same before and after the reference count increment. This pattern can be seen in get_file_rcu() and __files_get_rcu(). In addition, it isn't possible to access or check fields in struct file without first aqcuiring a reference on it. Not doing that was always very dodgy and it was only usable for non-pointer data in struct file. With SLAB_TYPESAFE_BY_RCU it is necessary that callers first acquire a reference under rcu or they must hold the files_lock of the fdtable. Failing to do either one of this is a bug. Thanks to Jann for pointing out that we need to ensure memory ordering between reallocations and pointer check by ensuring that all subsequent loads have a dependency on the second load in get_file_rcu() and providing a fixup that was folded into this patch. Cc: Jann Horn <[email protected]> Suggested-by: Linus Torvalds <[email protected]> Signed-off-by: Christian Brauner <[email protected]>
2023-10-18drm/i915/perf: Determine context valid in OA reportsUmesh Nerlige Ramappa1-2/+2
When supporting OA for TGL, it was seen that the context valid bit in the report ID was not defined, however revisiting the spec seems to have this bit defined. The bit is used to determine if a context is valid on a context switch and is essential to determine active and idle periods for a context. Re-enable the context valid bit for gen12 platforms. BSpec: 52196 (description of report_id) v2: Include BSpec reference (Ashutosh) Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL") Signed-off-by: Umesh Nerlige Ramappa <[email protected]> Reviewed-by: Ashutosh Dixit <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/i915/mtl: Don't set PIPE_CONTROL_FLUSH_L3Vinay Belgaumkar1-2/+5
This bit does not cause an explicit L3 flush. We already use PIPE_CONTROL_DC_FLUSH_ENABLE for that purpose. v2: Use FLUSH_L3 only pre-MTL since spec will likely remain the same going forward. Cc: Nirmoy Das <[email protected]> Cc: Mika Kuoppala <[email protected]> Acked-by: Mika Kuoppala <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Signed-off-by: Vinay Belgaumkar <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm: mediatek: mtk_dsi: Fix NO_EOT_PACKET settings/handlingAngeloGioacchino Del Regno1-2/+2
Due to the initial confusion about MIPI_DSI_MODE_EOT_PACKET, properly renamed to MIPI_DSI_MODE_NO_EOT_PACKET, reflecting its actual meaning, both the DSI_TXRX_CON register setting for bit (HSTX_)DIS_EOT and the later calculation for horizontal sync-active (HSA), back (HBP) and front (HFP) porches got incorrect due to the logic being inverted. This means that a number of settings were wrong because....: - DSI_TXRX_CON register setting: bit (HSTX_)DIS_EOT should be set in order to disable the End of Transmission packet; - Horizontal Sync and Back/Front porches: The delta used to calculate all of HSA, HBP and HFP should account for the additional EOT packet. Before this change... - Bit (HSTX_)DIS_EOT was being set when EOT packet was enabled; - For HSA/HBP/HFP delta... all three were wrong, as words were added when EOT disabled, instead of when EOT packet enabled! Invert the logic around flag MIPI_DSI_MODE_NO_EOT_PACKET in the MediaTek DSI driver to fix the aforementioned issues. Fixes: 8b2b99fd7931 ("drm/mediatek: dsi: Fine tune the line time caused by EOTp") Fixes: c87d1c4b5b9a ("drm/mediatek: dsi: Use symbolized register definition") Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Alexandre Mergnat <[email protected]> Tested-by: Michael Walle <[email protected]> Link: https://patchwork.kernel.org/project/dri-devel/patch/[email protected]/ Signed-off-by: Chun-Kuang Hu <[email protected]>
2023-10-18drm/i915: Prevent potential null-ptr-deref in engine_init_commonNirmoy Das1-1/+2
If measure_breadcrumb_dw() returns an error and bce isn't created, this commit ensures that intel_engine_destroy_pinned_context() is not called with a NULL bce. v2: Fix the subject s/UAF/null-ptr-deref(Jani) Fixes: b35274993680 ("drm/i915: Create a kernel context for GGTT updates") Cc: Oak Zeng <[email protected]> Cc: Andi Shyti <[email protected]> Cc: Jani Nikula <[email protected]> Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18mei: update mei-pxp's component interface with timeoutsAlan Previn1-2/+6
In debugging platform or firmware related MEI-PXP connection issues, having a timeout when clients (such as i915) calling into mei-pxp's send/receive functions have proven useful as opposed to blocking forever until the kernel triggers a watchdog panic (when platform issues are experienced). Update the mei-pxp component interface send and receive functions to take in timeouts. Signed-off-by: Alan Previn <[email protected]> Signed-off-by: Alexander Usyskin <[email protected]> Signed-off-by: Tomas Winkler <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-10-18drm/ssd130x: Add support for the SSD132x OLED controller familyJavier Martinez Canillas5-27/+449
The Solomon SSD132x controllers (such as the SSD1322, SSD1325 and SSD1327) are used by 16 grayscale dot matrix OLED panels, extend the driver to also support this chip family. Instead adding an indirection level to allow the same modesetting pipeline to be used by both controller families, add another pipeline for SSD132x. This leads to some code duplication but it makes the driver easier to read and reason about. Once other controller families are added (e.g: SSD133x), some common code can be factored out in driver helpers to be shared by the different families. But that can be done later once these patterns emerge. Signed-off-by: Javier Martinez Canillas <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/ssd130x: Rename commands that are shared across chip familiesJavier Martinez Canillas3-25/+30
There are some commands that are shared between the SSD130x and SSD132x controller families, define these as a common SSD13XX set of commands. Signed-off-by: Javier Martinez Canillas <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/ssd130x: Add a controller family id to the device info dataJavier Martinez Canillas4-0/+15
To allow the driver to have a per Solomon display controller modesetting pipeline and support aother controller families besides SSD130x. Signed-off-by: Javier Martinez Canillas <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/ssd130x: Replace .page_height field in device info with a constantJavier Martinez Canillas2-20/+18
This deemed useful to avoid hardcoding a page height and allow to support other Solomon controller families, but dividing the screen in pages seems to be something that is specific to the SSD130x chip family. For example, SSD132x chip family divides the screen in segments (columns) and common outputs (rows), so the concept of screen pages does not exist for the SSD132x family. Let's drop this field from the device info struct and just use a constant SSD130X_PAGE_HEIGHT macro to define the page height. While being there, replace hardcoded 8 values in places where it is used as the page height. Signed-off-by: Javier Martinez Canillas <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Acked-by: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18Merge tag 'amd-drm-next-6.7-2023-10-13' of ↵Dave Airlie565-5375/+266072
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-6.7-2023-10-13: amdgpu: - DC replay fixes - Misc code cleanups and spelling fixes - Documentation updates - RAS EEPROM Updates - FRU EEPROM Updates - IP discovery updates - SR-IOV fixes - RAS updates - DC PQ fixes - SMU 13.0.6 updates - GC 11.5 Support - NBIO 7.11 Support - GMC 11 Updates - Reset fixes - SMU 11.5 Updates - SMU 13.0 OD support - Use flexible arrays for bo list handling - W=1 Fixes - SubVP fixes - DPIA fixes - DCN 3.5 Support - Devcoredump fixes - VPE 6.1 support - VCN 4.0 Updates - S/G display fixes - DML fixes - DML2 Support - MST fixes - VRR fixes - Enable seamless boot in more cases - Enable content type property for HDMI - OLED fixes - Rework and clean up GPUVM TLB flushing - DC ODM fixes - DP 2.x fixes - AGP aperture fixes - SDMA firmware loading cleanups - Cyan Skillfish GPU clock counter fix - GC 11 GART fix - Cache GPU fault info for userspace queries - DC cursor check fixes - eDP fixes - DC FP handling fixes - Variable sized array fixes - SMU 13.0.x fixes - IB start and size alignment fixes for VCN - SMU 14 Support - Suspend and resume sequence rework - vkms fix amdkfd: - GC 11 fixes - GC 10 fixes - Doorbell fixes - CWSR fixes - SVM fixes - Clean up GC info enumeration - Rework memory limit handling - Coherent memory handling fixes - Use partial migrations in GPU faults - TLB flush fixes - DMA unmap fixes - GC 9.4.3 fixes - SQ interrupt fix - GTT mapping fix - GC 11.5 Support radeon: - Misc code cleanups - W=1 Fixes - Fix possible buffer overflow - Fix possible NULL pointer dereference UAPI: - Add EXT_COHERENT memory allocation flags. These allow for system scope atomics. Proposed userspace: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/pull/88 - Add support for new VPE engine. This is a memory to memory copy engine with advanced scaling, CSC, and color management features Proposed mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25713 - Add INFO IOCTL interface to query GPU faults Proposed Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23238 Proposed libdrm MR: https://gitlab.freedesktop.org/mesa/drm/-/merge_requests/298 Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/i915/mtl: Remove the 'force_probe' requirement for Meteor LakeRadhakrishna Sripada1-1/+0
Meteor Lake has demonstrated consistent stability for some time. All user-space API modifications tide to its core platform functions are operational. The necessary firmware components are set up and comprehensive testing has been condused over a period. Given the recent faborable CI results, as well, we believe it's time to eliminate the 'force_probe' prerequisite and activate the platform by default. Signed-off-by: Aditya Chauhan <[email protected]> Signed-off-by: Andrzej Hajda <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Janusz Krzysztofik <[email protected]> Signed-off-by: Jonathan Cavitt <[email protected]> Signed-off-by: Nirmoy Das <[email protected]> Signed-off-by: Radhakrishna Sripada <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Cc: Jani Nikula <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Acked-by: Lee Shawn C <[email protected]> Tested-by: Lee Shawn C <[email protected]> Tested-by: Karthik B S <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/i915: Enable GuC TLB invalidations for MTLJonathan Cavitt1-0/+1
Enable GuC TLB invalidations for MTL. Though more platforms than just MTL support GuC TLB invalidations, MTL is presently the only platform that requires it for any purpose, so only enable it there for now to minimize cross-platform impact. Signed-off-by: Jonathan Cavitt <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Acked-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheckJonathan Cavitt1-2/+9
For the gt_tlb live selftest, when operating on the GSC engine, increase the timeout from 10 ms to 200 ms because the GSC engine is a bit slower than the rest. Signed-off-by: Jonathan Cavitt <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Acked-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/i915: No TLB invalidation on wedged GTJonathan Cavitt1-1/+31
It is not an error for GuC TLB invalidations to fail when the GT is wedged or disabled, so do not process a wait failure as one in guc_send_invalidate_tlb. Signed-off-by: Fei Yang <[email protected]> Signed-off-by: Jonathan Cavitt <[email protected]> CC: John Harrison <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Acked-by: Tvrtko Ursulin <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/i915: No TLB invalidation on suspended GTJonathan Cavitt3-9/+23
In case of GT is suspended, don't allow submission of new TLB invalidation request and cancel all pending requests. The TLB entries will be invalidated either during GuC reload or on system resume. Signed-off-by: Fei Yang <[email protected]> Signed-off-by: Jonathan Cavitt <[email protected]> CC: John Harrison <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Acked-by: Tvrtko Ursulin <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/i915: Define and use GuC and CTB TLB invalidation routinesPrathap Kumar Valsan7-11/+299
The GuC firmware had defined the interface for Translation Look-Aside Buffer (TLB) invalidation. We should use this interface when invalidating the engine and GuC TLBs. Add additional functionality to intel_gt_invalidate_tlb, invalidating the GuC TLBs and falling back to GT invalidation when the GuC is disabled. The invalidation is done by sending a request directly to the GuC tlb_lookup that invalidates the table. The invalidation is submitted as a wait request and is performed in the CT event handler. This means we cannot perform this TLB invalidation path if the CT is not enabled. If the request isn't fulfilled in two seconds, this would constitute an error in the invalidation as that would constitute either a lost request or a severe GuC overload. With this new invalidation routine, we can perform GuC-based GGTT invalidations. GuC-based GGTT invalidation is incompatible with MMIO invalidation so we should not perform MMIO invalidation when GuC-based GGTT invalidation is expected. The additional complexity incurred in this patch will be necessary for range-based tlb invalidations, which will be platformed in the future. Signed-off-by: Prathap Kumar Valsan <[email protected]> Signed-off-by: Bruce Chang <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Signed-off-by: Umesh Nerlige Ramappa <[email protected]> Signed-off-by: Jonathan Cavitt <[email protected]> Signed-off-by: Aravind Iddamsetty <[email protected]> Signed-off-by: Fei Yang <[email protected]> CC: Andi Shyti <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Acked-by: Tvrtko Ursulin <[email protected]> Acked-by: Nirmoy Das <[email protected]> Reviewed-by: John Harrison <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/i915/guc: Add CT size delay helperJonathan Cavitt2-0/+29
As of now, there is no mechanism for tracking a given request's progress through the queue. Instead, add a helper that returns an estimated maximum time the queue should take to drain if completely full. Suggested-by: John Harrison <[email protected]> Signed-off-by: Jonathan Cavitt <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Acked-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Reviewed-by: John Harrison <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-18drm/i915: Add GuC TLB Invalidation device info flagsJonathan Cavitt2-0/+3
Add device info flags for if GuC TLB Invalidation is enabled. Signed-off-by: Jonathan Cavitt <[email protected]> Reviewed-by: Andi Shyti <[email protected]> Acked-by: Tvrtko Ursulin <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Signed-off-by: Andi Shyti <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-17drm/i915: Retry gtt fault when out of fence registersVille Syrjälä1-0/+1
If we can't find a free fence register to handle a fault in the GMADR range just return VM_FAULT_NOPAGE without populating the PTE so that userspace will retry the access and trigger another fault. Eventually we should find a free fence and the fault will get properly handled. A further improvement idea might be to reserve a fence (or one per CPU?) for the express purpose of handling faults without having to retry. But that would require some additional work. Looks like this may have gotten broken originally by commit 39965b376601 ("drm/i915: don't trash the gtt when running out of fences") as that changed the errno to -EDEADLK which wasn't handle by the gtt fault code either. But later in commit 2feeb52859fc ("drm/i915/gt: Fix -EDEADLK handling regression") I changed it again to -ENOBUFS as -EDEADLK was now getting used for the ww mutex dance. So this fix only makes sense after that last commit. Cc: [email protected] Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/9479 Fixes: 2feeb52859fc ("drm/i915/gt: Fix -EDEADLK handling regression") Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Andi Shyti <[email protected]> (cherry picked from commit 7f403caabe811b88ab0de3811ff3f4782c415761) Signed-off-by: Rodrigo Vivi <[email protected]>
2023-10-17drm/i915/cx0: Only clear/set the Pipe Reset bit of the PHY Lanes OwnedKhaled Almahallawy1-2/+1
Currently, with MFD/pin assignment D, the driver clears the pipe reset bit of lane 1 which is not owned by display. This causes the display to block S0iX. By not clearing this bit for lane 1 and keeping whatever default, S0ix started to work. This is already what the driver does at the end of the phy lane reset sequence (Step#8) Bspec: 65451 Fixes: 619a06dba6fa ("drm/i915/mtl: Reset only one lane in case of MFD") Cc: Mika Kahola <[email protected]> Cc: Gustavo Sousa <[email protected]> Signed-off-by: Khaled Almahallawy <[email protected]> Reviewed-by: Gustavo Sousa <[email protected]> Signed-off-by: Radhakrishna Sripada <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 4a07f063d20c46524f00976f4537de72d9f31c4e) Signed-off-by: Rodrigo Vivi <[email protected]>
2023-10-17gpu/drm: Eliminate DRM_SCHED_PRIORITY_UNSETLuben Tuikov1-1/+2
Eliminate DRM_SCHED_PRIORITY_UNSET, value of -2, whose only user was amdgpu. Furthermore, eliminate an index bug, in that when amdgpu boots, it calls drm_sched_entity_init() with DRM_SCHED_PRIORITY_UNSET, which uses it to index sched->sched_rq[]. Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alex Deucher <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-10-17drm/amdgpu: Unset context priority is now invalidLuben Tuikov1-1/+1
A context priority value of AMD_CTX_PRIORITY_UNSET is now invalid--instead of carrying it around and passing it to the Direct Rendering Manager--and it becomes AMD_CTX_PRIORITY_NORMAL in amdgpu_ctx_ioctl(), the gateway to context creation. Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Acked-by: Alex Deucher <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2023-10-17drm/i915/pxp: Clean up zero initializersVille Syrjälä3-10/+10
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2023-10-17drm/i915/guc: Clean up zero initializersVille Syrjälä1-2/+2
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2023-10-17drm/gpuvm: Dual-licence the drm_gpuvm code GPL-2.0 OR MITThomas Hellström1-1/+1
Dual-licence in order to make it possible for other non-GPL os'es to re-implement the code. The use of EXPORT_SYMBOL_GPL() is intentionally left untouched to prevent use of drm_gpuvm as a proxy for non-GPL drivers to access GPL-only kernel symbols. Much of the ideas and algorithms used in the drm_gpuvm code is already present in one way or another in MIT-licensed code. Cc: Danilo Krummrich <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Thomas Hellström <[email protected]> Acked-by: Danilo Krummrich <[email protected]> Reviewed-by: Francois Dugast <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-17hyperv: avoid dependency on screen_infoArnd Bergmann1-3/+4
The two hyperv framebuffer drivers (hyperv_fb or hyperv_drm_drv) access the global screen_info in order to take over from the sysfb framebuffer, which in turn could be handled by simplefb, simpledrm or efifb. Similarly, the vmbus_drv code marks the original EFI framebuffer as reserved, but this is not required if there is no sysfb. As a preparation for making screen_info itself more local to the sysfb helper code, add a compile-time conditional in all three files that relate to hyperv fb and just skip this code if there is no sysfb that needs to be unregistered. Reviewed-by: Javier Martinez Canillas <[email protected]> Acked-by: Helge Deller <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2023-10-17Merge tag 'drm-intel-gt-next-2023-10-12' of ↵Dave Airlie34-130/+577
git://anongit.freedesktop.org/drm/drm-intel into drm-next Driver Changes: Fixes/improvements/new stuff: - Register engines early to avoid type confusion (Mathias Krause) - Suppress 'ignoring reset notification' message [guc] (John Harrison) - Update 'recommended' version to 70.12.1 for DG2/ADL-S/ADL-P/MTL [guc] (John Harrison) - Enable WA 14018913170 [guc, dg2] (Daniele Ceraolo Spurio) Future platform enablement: - Clean steer semaphore on resume (Nirmoy Das) - Skip MCR ops for ring fault register [mtl] (Nirmoy Das) - Make i915_gem_shrinker multi-gt aware [gem] (Jonathan Cavitt) - Enable GGTT updates with binder in MTL (Nirmoy Das, Chris Wilson) - Invalidate the TLBs on each GT (Chris Wilson) Miscellaneous: - Clarify type evolution of uabi_node/uabi_engines (Mathias Krause) - Annotate struct ct_incoming_msg with __counted_by [guc] (Kees Cook) - More use of GT specific print helpers [gt] (John Harrison) Signed-off-by: Dave Airlie <[email protected]> From: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ZSfKotZVdypU6NaX@tursulin-desk
2023-10-16drm/panel: st7703: Add Powkiddy RGB30 Panel SupportChris Morgan1-0/+89
The Powkiddy RGB30 4 inch panel is a 4 inch 720x720 DSI panel used in the Powkiddy RGB30 handheld gaming device. Add support for it. Signed-off-by: Chris Morgan <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2023-10-16drm/msm/a7xx: actually use a7xx state registersDmitry Baryshkov2-10/+17
Make a6xx_get_registers() use a7xx registers instead of a6xx ones if the detected Adreno is from the A7xx family. Fixes: e997ae5f45ca ("drm/msm/a6xx: Mostly implement A7xx gpu_state") Signed-off-by: Dmitry Baryshkov <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/562233/ Signed-off-by: Rob Clark <[email protected]>
2023-10-16drm/msm/dpu: enable writeback on SM8550Neil Armstrong1-0/+16
Enable WB2 hardware block, enabling writeback support on this platform. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/562328/ Signed-off-by: Rob Clark <[email protected]>
2023-10-16drm/msm/dpu: sm8550: remove unused VIG and DMA clock controls entriesNeil Armstrong1-20/+0
The SM8550 has the SSPP clk_ctrl in the SSPP registers, remove the duplicate clock controls from the MDP top. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/562330/ Signed-off-by: Rob Clark <[email protected]>
2023-10-16drm/msm/dpu: move setup_force_clk_ctrl handling into plane and wbNeil Armstrong4-36/+77
Now SSPP and WB can have setup_force_clk_ctrl() ops, it's simpler to call them from the plane and wb code and call into the mdp ops if not present. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/562325/ Signed-off-by: Rob Clark <[email protected]>
2023-10-16drm/msm/dpu: add setup_clk_force_ctrl() op to sspp & wbNeil Armstrong5-10/+54
Starting from SM8550, the SSPP & WB clock controls are moved the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT" downstream. Implement setup_clk_force_ctrl() only starting from major version 9 which corresponds to SM8550 MDSS. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/562322/ Signed-off-by: Rob Clark <[email protected]>
2023-10-16drm/msm/dpu: create a dpu_hw_clk_force_ctrl() helperNeil Armstrong3-22/+26
Add an helper to setup the force clock control as it will be used in multiple HW files. Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Patchwork: https://patchwork.freedesktop.org/patch/562323/ Signed-off-by: Rob Clark <[email protected]>
2023-10-16drm/i915/pci: Clean up zero initializersVille Syrjälä1-1/+1
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
2023-10-16drm/i915/hdcp: Clean up zero initializersVille Syrjälä1-23/+21
Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Jani Nikula <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.