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2013-08-30drm/radeon/dpm: use multiple UVD power states (v3)Alex Deucher4-12/+57
Use the UVD handle information to determine which which power states to select when using UVD. For example, decoding a single SD stream requires much lower clocks than multiple HD streams. v2: switch to a cleaner dpm/uvd interface v3: change the uvd power state while streams are active if need be Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: add UVD->DPM helper function (v5)Alex Deucher2-0/+36
Add a helper function for counting the number of open stream handles. v2: fix copy-pasta in comments and whitespace error v3: make function static since it's only used in radeon_uvd.c at the moment v4: make non-static again for future changes v5: make static again for new rework of dpm uvd changes Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon/kms: remove r6xx+ blit copy routinesAlex Deucher14-1764/+33
No longer used now that we use the async dma engines or CP DMA for bo copies. Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/radeon: switch r6xx+ to using CP DMA for the blit copy callbackAlex Deucher1-9/+9
CP DMA is lighter weight than using the 3D engine. Signed-off-by: Alex Deucher <[email protected]>
2013-08-30drm/edid: add quirk for Medion MD30217PGAlex Deucher1-0/+3
This LCD monitor (1280x1024 native) has a completely bogus detailed timing (640x350@70hz). User reports that 1280x1024@60 has waves so prefer 1280x1024@75. Manufacturer: MED Model: 7b8 Serial#: 99188 Year: 2005 Week: 5 EDID Version: 1.3 Analog Display Input, Input Voltage Level: 0.700/0.700 V Sync: Separate Max Image Size [cm]: horiz.: 34 vert.: 27 Gamma: 2.50 DPMS capabilities: Off; RGB/Color Display First detailed timing is preferred mode redX: 0.645 redY: 0.348 greenX: 0.280 greenY: 0.605 blueX: 0.142 blueY: 0.071 whiteX: 0.313 whiteY: 0.329 Supported established timings: 720x400@70Hz 640x480@60Hz 640x480@72Hz 640x480@75Hz 800x600@56Hz 800x600@60Hz 800x600@72Hz 800x600@75Hz 1024x768@60Hz 1024x768@70Hz 1024x768@75Hz 1280x1024@75Hz Manufacturer's mask: 0 Supported standard timings: Supported detailed timing: clock: 25.2 MHz Image Size: 337 x 270 mm h_active: 640 h_sync: 688 h_sync_end 784 h_blank_end 800 h_border: 0 v_active: 350 v_sync: 350 v_sync_end 352 v_blanking: 449 v_border: 0 Monitor name: MD30217PG Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 83 kHz, PixClock max 145 MHz Serial No: 501099188 EDID (in hex): 00ffffffffffff0034a4b80774830100 050f010368221b962a0c55a559479b24 125054afcf00310a0101010101018180 000000000000d60980a0205e63103060 0200510e1100001e000000fc004d4433 3032313750470a202020000000fd0038 4c1e530e000a202020202020000000ff 003530313039393138380a2020200078 Signed-off-by: Alex Deucher <[email protected]> Reported-by: [email protected] Cc: [email protected]
2013-08-30OMAPDSS: rename omap_dss_device's 'output' to 'src'Tomi Valkeinen1-1/+1
In the old panel device model we had "outputs", which were the encoders inside OMAP DSS block, and panel devices (omap_dss_device). The panel devices had a reference to the source of the video data, i.e. reference to an "output", in a field named "output". That was somewhat confusing even in the old panel device model, but even more so with the panel device model where we can have longer chains of display entities. This patch renames the "output" field to "src", which much better tells what the field points to. Signed-off-by: Tomi Valkeinen <[email protected]> Reviewed-by: Archit Taneja <[email protected]>
2013-08-30Merge tag 'drm-intel-next-2013-08-23' of ↵Dave Airlie25-385/+1035
git://people.freedesktop.org/~danvet/drm-intel into drm-next Need to get my stuff out the door ;-) Highlights: - pc8+ support from Paulo - more vma patches from Ben. - Kconfig option to enable preliminary support by default (Josh Triplett) - Optimized cpu cache flush handling and support for write-through caching of display planes on Iris (Chris) - rc6 tuning from Stéphane Marchesin for more stability - VECS seqno wrap/semaphores fix (Ben) - a pile of smaller cleanups and improvements all over Note that I've ditched Ben's execbuf vma conversion for 3.12 since not yet ready. But there's still other vma conversion stuff in here. * tag 'drm-intel-next-2013-08-23' of git://people.freedesktop.org/~danvet/drm-intel: (62 commits) drm/i915: Print seqnos as unsigned in debugfs drm/i915: Fix context size calculation on SNB/IVB/VLV drm/i915: Use POSTING_READ in lcpll code drm/i915: enable Package C8+ by default drm/i915: add i915.pc8_timeout function drm/i915: add i915_pc8_status debugfs file drm/i915: allow package C8+ states on Haswell (disabled) drm/i915: fix SDEIMR assertion when disabling LCPLL drm/i915: grab force_wake when restoring LCPLL drm/i915: drop WaMbcDriverBootEnable workaround drm/i915: Cleaning up the relocate entry function drm/i915: merge HSW and SNB PM irq handlers drm/i915: fix how we mask PMIMR when adding work to the queue drm/i915: don't queue PM events we won't process drm/i915: don't disable/reenable IVB error interrupts when not needed drm/i915: add dev_priv->pm_irq_mask drm/i915: don't update GEN6_PMIMR when it's not needed drm/i915: wrap GEN6_PMIMR changes drm/i915: wrap GTIMR changes drm/i915: add the FCLK case to intel_ddi_get_cdclk_freq ...
2013-08-30drm: Advertise async page flip ability through GETCAP ioctlKeith Packard2-0/+6
Let applications know whether the kernel supports asynchronous page flipping. Signed-off-by: Keith Packard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm: Pass page flip ioctl flags to driverKeith Packard14-22/+41
This lets drivers see the flags requested by the application [airlied: fixup for rcar/imx/msm] Signed-off-by: Keith Packard <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm/omap: tiler: clear buffer properlyDan Carpenter1-1/+1
We're taking the sizeof() the wrong thing so it doesn't clear the whole buffer. Signed-off-by: Dan Carpenter <[email protected]> Acked-by: Rob Clark <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm/prime: Remove PRIME handles only if supportedThierry Reding1-2/+4
Drivers that don't support PRIME will not have initialized the PRIME specific private component of struct drm_file. If called for such drivers, the drm_gem_remove_prime_handles() function will crash. Fix it by checking for PRIME support prior to removing the PRIME handles. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm/vmwgfx: Split GMR2_REMAP commands if they are to largeJakob Bornecrantz1-19/+39
This fixes the piglit test texturing/max-texture-size causing the VM to die due to a too large SVGA command. Signed-off-by: Jakob Bornecrantz <[email protected]> Reviewed-by: Biran Paul <[email protected]> Reviewed-by: Zack Rusin <[email protected]> Cc: [email protected] Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm/prime: double lock typoDan Carpenter1-1/+1
There is a typo so deadlocks on error instead of unlocking. Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm/vmwgfx: fix error return code in vmw_driver_load()Wei Yongjun1-1/+3
Fix to return -ENOMEM in the fence manager init error handling case instead of 0, as done elsewhere in this function. Signed-off-by: Wei Yongjun <[email protected]> Acked-by: Dmitry Torokhov <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm: implement experimental render nodesDavid Herrmann6-13/+51
Render nodes provide an API for userspace to use non-privileged GPU commands without any running DRM-Master. It is useful for offscreen rendering, GPGPU clients, and normal render clients which do not perform modesetting. Compared to legacy clients, render clients no longer need any authentication to perform client ioctls. Instead, user-space controls render/client access to GPUs via filesystem access-modes on the render-node. Once a render-node was opened, a client has full access to the client/render operations on the GPU. However, no modesetting or ioctls that affect global state are allowed on render nodes. To prevent privilege-escalation, drivers must explicitly state that they support render nodes. They must mark their render-only ioctls as DRM_RENDER_ALLOW so render clients can use them. Furthermore, they must support clients without any attached master. If filesystem access-modes are not enough for fine-grained access control to render nodes (very unlikely, considering the versaitlity of FS-ACLs), you may still fall-back to fd-passing from server to client (which allows arbitrary access-control). However, note that revoking access is currently impossible and unlikely to get implemented. Note: Render clients no longer have any associated DRM-Master as they are supposed to be independent of any server state. DRM core highly depends on file_priv->master to be non-NULL for modesetting/ctx/etc. commands. Therefore, drivers must be very careful to not require DRM-Master if they support DRIVER_RENDER. So far render-nodes are protected by "drm_rnodes". As long as this module-parameter is not set to 1, a driver will not create render nodes. This allows us to experiment with the API a bit before we stabilize it. v2: drop insecure GEM_FLINK to force use of dmabuf Signed-off-by: David Herrmann <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30video/hdmi: Rename HDMI_IDENTIFIER to HDMI_IEEE_OUILespiau, Damien1-1/+1
HDMI_IDENTIFIER was felt too generic, rename it to what it is, the IEEE OUI corresponding to HDMI Licensing, LLC. http://standards.ieee.org/develop/regauth/oui/oui.txt Cc: Thierry Reding <[email protected]> Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm/i915/hdmi: Write HDMI vendor specific infoframesLespiau, Damien2-0/+30
With all the common infoframe bits now in place, we can finally write the vendor specific infoframes in our driver. Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm: Add a helper to forge HDMI vendor infoframesLespiau, Damien1-0/+36
This can then be used by DRM drivers to setup their vendor infoframes. v2: Fix hmdi typo (Simon Farnsworth) v3: Adapt to the hdmi_vendor_infoframe rename Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Simon Farnsworth <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30video/hdmi: Use hdmi_vendor_infoframe for the HDMI specific infoframeLespiau, Damien1-3/+3
We just got rid of the version of hdmi_vendor_infoframe that had a byte array for anyone to poke at. It's now time to shuffle around the naming of hdmi_hdmi_infoframe to make hdmi_vendor_infoframe become the HDMI vendor specific structure. Cc: Thierry Reding <[email protected]> Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm/edid: Move HDMI_IDENTIFIER to hdmi.hLespiau, Damien1-1/+0
We'll need the HDMI OUI for the HDMI vendor infoframe data, so let's move the DRM one to hdmi.h, might as well use the hdmi header to store some hdmi defines. (Note that, in fact, infoframes are part of the CEA-861 standard, and only the HDMI vendor specific infoframe is special to HDMI, but details..) Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30gpu: host1x: Port the HDMI vendor infoframe code the common helpersLespiau, Damien1-20/+4
I just wrote the bits to define and pack HDMI vendor specific infoframe. Port the host1x driver to use those so I can refactor the infoframe code a bit more. This changes the length of the infoframe payload from 6 to 5, which is enough for the "frame packing" stereo format. v2: Pimp up the commit message with the note about the length (Ville Syrjälä) Cc: Thierry Reding <[email protected]> Cc: Terje Bergström <[email protected]> Cc: [email protected] Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30video/hdmi: Don't let the user of this API create invalid infoframesLespiau, Damien1-1/+0
To set the active aspect ratio value in the AVI infoframe today, you not only have to set the active_aspect field, but also the active_info_valid bit. Out of the 1 user of this API, we had 100% misuse, forgetting the _valid bit. This was fixed in: Author: Damien Lespiau <[email protected]> Date: Tue Aug 6 20:32:17 2013 +0100 drm: Don't generate invalid AVI infoframes for CEA modes We can do better and derive the _valid bit from the user wanting to set the active aspect ratio. v2: Fix multi-lines comment style (Thierry Reding) Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm: Add support for alternate clocks of 4k modesLespiau, Damien1-6/+62
v2: Fix hmdi typo (Simon Farnsworth, Ville Syrjälä) Suggested-by: Ville Syrjälä <[email protected]> Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: Simon Farnsworth <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm/edid: Parse the HDMI CEA block and look for 4k modesLespiau, Damien1-15/+109
HDMI 1.4 adds 4 "4k x 2k" modes in the the CEA vendor specific block. With this commit, we now parse this block and expose the 4k modes that we find there. v2: Fix the "4096x2160" string (nice catch!), add comments about do_hdmi_vsdb_modes() arguments and make it clearer that offset is relative to the end of the required fields of the HDMI VSDB (Ville Syrjälä) v3: Fix 'Unknow' typo (Simon Farnsworth) Signed-off-by: Damien Lespiau <[email protected]> Tested-by: Cancan Feng <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67030 Reviewed-by: Simon Farnsworth <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm/edid: Fix add_cea_modes() style issuesLespiau, Damien1-5/+7
A few styles issues have crept in here, fix them before touching this code again. v2: constify arguments that can be (Ville Syrjälä) v3: constify, but better (Ville Syrjälä) Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm: Don't export drm_find_cea_extension() any moreLespiau, Damien1-3/+2
This function is only used inside drm_edid.c. Signed-off-by: Damien Lespiau <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Reviewed-by: Thierry Reding <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-30drm/i915: ivb: fix edp voltage swing reg valImre Deak1-1/+1
Fix the typo introduced in commit 1a2eb4604b85c5efb343da8a4dcf41288fcfca85 Author: Keith Packard <[email protected]> Date: Wed Nov 16 16:26:07 2011 -0800 drm/i915: Hook up Ivybridge eDP This fixes eDP link-training failures and cases where all voltage swing /pre-emphasis levels were tried and failed during clock recovery and - as a fallback - we go on to do channel equalization with the last voltage swing/pre-emphasis level which will succeed. Both issues can lead to a blank screen. v2: - improve commit message CC: [email protected] Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64880 Tested-by: Jeremy Moles <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-08-29nouveau: add runtime PM support (v0.9)Dave Airlie13-43/+404
This hooks nouveau up to the runtime PM system to enable dynamic power management for secondary GPUs in switchable and optimus laptops. a) rewrite suspend/resume printks to hide them during dynamic s/r to avoid cluttering logs b) add runtime pm suspend to irq handler, crtc display, ioctl handler, connector status, c) handle hdmi audio dynamic power on/off using magic register. v0.5: make sure we hit D3 properly fix fbdev_set_suspend locking interaction, we only will poweroff if we have no active crtcs/fbcon anyways. add reference for active crtcs. sprinkle mark last busy for autosuspend timeout v0.6: allow more flexible debugging - to avoid log spam add option to enable/disable dynpm got to D3Cold v0.7: add hdmi audio support. v0.8: call autosuspend from idle, so pci config space access doesn't go straight back to sleep, this makes starting X faster. only signal usage if we actually handle the irq, otherwise usb keeps us awake. fix nv50 display active powerdown v0.9: use masking function to enable hdmi audio set busy when we fail to suspend Signed-off-by: Dave Airlie <[email protected]>
2013-08-29drm: allow open of dynamic off devices.Dave Airlie1-1/+1
Signed-off-by: Dave Airlie <[email protected]>
2013-08-29gpu/vga_switcheroo: add driver control power feature. (v3)Dave Airlie4-8/+145
For optimus and powerxpress muxless we really want the GPU driver deciding when to power up/down the GPU, not userspace. This adds the ability for a driver to dynamically power up/down the GPU and remove the switcheroo from controlling it, the switcheroo reports the dynamic state to userspace also. It also adds 2 power domains, one for machine where the power switch is controlled outside the GPU D3 state, so the powerdown ordering is done correctly, and the second for the hdmi audio device to make sure it can resume for PCI config space accesses. v1.1: fix build with switcheroo off v2: add power domain support for radeon and v1 nvidia dsms v2.1: fix typo in off case v3: add audio power domain for hdmi audio + misc audio fixes v4: use PCI_SLOT macro, drop power reference on hdmi audio resume failure also. Signed-off-by: Dave Airlie <[email protected]>
2013-08-28Merge branch 'drm-next' of git://people.freedesktop.org/~robclark/linux into ↵Dave Airlie45-0/+14636
drm-next Merge the MSM driver from Rob Clark * 'drm-next' of git://people.freedesktop.org/~robclark/linux: drm/msm: add basic hangcheck/recovery mechanism drm/msm: add a3xx gpu support drm/msm: add register definitions for gpu drm/msm: basic KMS driver for snapdragon drm/msm: add register definitions
2013-08-27gpu: host1x: returning success instead of -ENOMEMDan Carpenter1-2/+1
There is a mistake here so it returns PTR_ERR(NULL) which is success instead of -ENOMEM. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2013-08-27gpu: host1x: fix an integer overflow checkDan Carpenter1-6/+6
Tegra is a 32 bit arch. On 32 bit systems then size_t is 32 bits so "total" will never be higher than UINT_MAX because of integer overflows. We need cast to u64 first before doing the math. Also the addition earlier: unsigned int num_unpins = num_cmdbufs + num_relocs; That can overflow as well, but I think it's still safe because we check both "num_cmdbufs" and "num_relocs" again in this test. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2013-08-27drm/tegra: hdmi: Make sure clock is enabled before dumping registersMikko Perttunen1-0/+7
The debugfs register dumping function did not enable the HDMI clock. This led to a possible system hang when reading the debugfs entry while no HDMI cable was connected to the system. This patch makes sure that the clock is enabled during the read. Signed-off-by: Mikko Perttunen <[email protected]> Signed-off-by: Thierry Reding <[email protected]>
2013-08-27drm: verify vma access in TTM+GEM driversDavid Herrmann6-6/+18
GEM does already a good job in tracking access to gem buffers via handles and drm_vma access management. However, TTM drivers currently do not verify this during mmap(). TTM provides the verify_access() callback to test this. So fix all drivers to actually call into gem+vma to verify access instead of always returning 0. All drivers assume that user-space can only get access to TTM buffers via GEM handles. So whenever the verify_access() callback is called from ttm_bo_mmap(), the buffer must have a valid embedded gem object. This is true for all TTM+GEM drivers. But that's why this patch doesn't touch pure TTM drivers (ie, vmwgfx). v2: Switch to drm_vma_node_verify_access() to correctly return -EACCES if access was denied. Cc: Dave Airlie <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Ben Skeggs <[email protected]> Cc: Maarten Lankhorst <[email protected]> Cc: Jerome Glisse <[email protected]> Signed-off-by: David Herrmann <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-27drm/gem: implement vma access managementDavid Herrmann1-0/+17
We implement automatic vma mmap() access management for all drivers using gem_mmap. We use the vma manager to add each open-file that creates a gem-handle to the vma-node of the underlying gem object. Once the handle is destroyed, we drop the open-file again. This allows us to use drm_vma_node_is_allowed() on _any_ gem object to see whether an open-file is granted access. In drm_gem_mmap() we use this to verify that unprivileged users cannot guess gem offsets and map arbitrary buffers. Note that this manages access for _all_ gem users (also TTM+GEM), but the actual access checks are only done for drm_gem_mmap(). TTM drivers use the TTM mmap helpers, which need to do that separately. Signed-off-by: David Herrmann <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-27drm/vma: add access management helpersDavid Herrmann2-0/+156
The VMA offset manager uses a device-global address-space. Hence, any user can currently map any offset-node they want. They only need to guess the right offset. If we wanted per open-file offset spaces, we'd either need VM_NONLINEAR mappings or multiple "struct address_space" trees. As both doesn't really scale, we implement access management in the VMA manager itself. We use an rb-tree to store open-files for each VMA node. On each mmap call, GEM, TTM or the drivers must check whether the current user is allowed to map this file. We add a separate lock for each node as there is no generic lock available for the caller to protect the node easily. As we currently don't know whether an object may be used for mmap(), we have to do access management for all objects. If it turns out to slow down handle creation/deletion significantly, we can optimize it in several ways: - Most times only a single filp is added per bo so we could use a static "struct file *main_filp" which is checked/added/removed first before we fall back to the rbtree+drm_vma_offset_file. This could be even done lockless with rcu. - Let user-space pass a hint whether mmap() should be supported on the bo and avoid access-management if not. - .. there are probably more ideas once we have benchmarks .. v2: add drm_vma_node_verify_access() helper Signed-off-by: David Herrmann <[email protected]> Signed-off-by: Dave Airlie <[email protected]>
2013-08-24drm/msm: add basic hangcheck/recovery mechanismRob Clark5-5/+87
A basic, no-frills recovery mechanism in case the gpu gets wedged. We could try to be a bit more fancy and restart the next submit after the one that got wedged, but for now keep it simple. This is enough to recover things if, for example, the gpu hangs mid way through a piglit run. Signed-off-by: Rob Clark <[email protected]>
2013-08-24drm/msm: add a3xx gpu supportRob Clark14-16/+2487
Add initial support for a3xx 3d core. So far, with hardware that I've seen to date, we can have: + zero, one, or two z180 2d cores + a3xx or a2xx 3d core, which share a common CP (the firmware for the CP seems to implement some different PM4 packet types but the basics of cmdstream submission are the same) Which means that the eventual complete "class" hierarchy, once support for all past and present hw is in place, becomes: + msm_gpu + adreno_gpu + a3xx_gpu + a2xx_gpu + z180_gpu This commit splits out the parts that will eventually be common between a2xx/a3xx into adreno_gpu, and the parts that are even common to z180 into msm_gpu. Note that there is no cmdstream validation required. All memory access from the GPU is via IOMMU/MMU. So as long as you don't map silly things to the GPU, there isn't much damage that the GPU can do. Signed-off-by: Rob Clark <[email protected]>
2013-08-24drm/msm: add register definitions for gpuRob Clark4-0/+4317
Generated from rnndb files in: https://github.com/freedreno/envytools Keep this split out as a separate commit to make it easier to review the actual driver. Signed-off-by: Rob Clark <[email protected]>
2013-08-24drm/msm: basic KMS driver for snapdragonRob Clark26-0/+5483
The snapdragon chips have multiple different display controllers, depending on which chip variant/version. (As far as I can tell, current devices have either MDP3 or MDP4, and upcoming devices have MDSS.) And then external to the display controller are HDMI, DSI, etc. blocks which may be shared across devices which have different display controller blocks. To more easily add support for different display controller blocks, the display controller specific bits are split out into a "kms" module, which provides the kms plane/crtc/encoder objects. The external HDMI, DSI, etc. blocks are part encoder, and part connector currently. But I think I will pull in the drm_bridge patches from chromeos tree, and split them into a bridge+connector, with the registers that need to be set in modeset handled by the bridge. This would remove the 'msm_connector' base class. But some things need to be double checked to make sure I could get the correct ON/OFF sequencing.. This patch adds support for mdp4 crtc (including hw cursor), dtv encoder (part of MDP4 block), and hdmi. Signed-off-by: Rob Clark <[email protected]>
2013-08-24drm/msm: add register definitionsRob Clark6-0/+2283
Generated from rnndb files in: https://github.com/freedreno/envytools Keep this split out as a separate commit to make it easier to review the actual driver. Signed-off-by: Rob Clark <[email protected]>
2013-08-23drm/i915: Print seqnos as unsigned in debugfsVille Syrjälä1-1/+1
I don't like seeing signed seqnos. Make them unsigned. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Damien Lespiau <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-08-23drm/i915: Fix context size calculation on SNB/IVB/VLVVille Syrjälä1-8/+15
All the different context sizes reported in the CXT_SIZE register aren't meant to be simply added together. While BSpec is somewhat unclear on the topic of the actual context size, empirical tests have now revealed the truth. So let's add a big fat comment to remind people how it all works. As a result of correctly interpreting CXT_SIZE, the IVB context size is reduced from three pages to two, while SNB context size remains at two pages. Signed-off-by: Ville Syrjälä <[email protected]> Acked-by: Ben Widawsky <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-08-23drm/i915: Use POSTING_READ in lcpll codeDaniel Vetter1-1/+2
If we don't use the return value of a mmio read our coding style is to use the POSTING_READ macro. This avoids cluttering the mmio traces. While at it add the missing posting read in the lcpll enable function that Paulo spotted. v2: Drop the _NOTRACE changes, tracing such wait_for loops in the modeset code might actually be rather useful! Cc: Paulo Zanoni <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-08-23drm/i915: enable Package C8+ by defaultPaulo Zanoni1-2/+2
This should be working, so enable it by default. Also easy to revert. v2: Rebase, s/allow/enable/. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-08-23drm/i915: add i915.pc8_timeout functionPaulo Zanoni3-1/+6
We currently only enter PC8+ after all its required conditions are met, there's no rendering, and we stay like that for at least 5 seconds. I chose "5 seconds" because this value is conservative and won't make us enter/leave PC8+ thousands of times after the screen is off: some desktop environments have applications that wake up and do rendering every 1-3 seconds, even when the screen is off and the machine is completely idle. But when I was testing my PC8+ patches I set the default value to 100ms so I could use the bad-behaving desktop environments to stress-test my patches. I also thought it would be a good idea to ask our power management team to test different values, but I'm pretty sure they would ask me for an easy way to change the timeout. So to help these 2 cases I decided to create an option that would make it easier to change the default value. I also expect people making specific products that use our driver could try to find the perfect timeout for them. Anyway, fixing the bad-behaving applications will always lead to better power savings than just changing the timeout value: you need to stop waking the Kernel, not quickly put it back to sleep again after you wake it for nothing. Bad sleep leads to bad mood! Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-08-23drm/i915: add i915_pc8_status debugfs filePaulo Zanoni1-0/+26
Make it print the value of the variables on the PC8 struct. v2: Update to recent renames and add the new fields. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-08-23drm/i915: allow package C8+ states on Haswell (disabled)Paulo Zanoni10-2/+390
This patch allows PC8+ states on Haswell. These states can only be reached when all the display outputs are disabled, and they allow some more power savings. The fact that the graphics device is allowing PC8+ doesn't mean that the machine will actually enter PC8+: all the other devices also need to allow PC8+. For now this option is disabled by default. You need i915.allow_pc8=1 if you want it. This patch adds a big comment inside i915_drv.h explaining how it works and how it tracks things. Read it. v2: (this is not really v2, many previous versions were already sent, but they had different names) - Use the new functions to enable/disable GTIMR and GEN6_PMIMR - Rename almost all variables and functions to names suggested by Chris - More WARNs on the IRQ handling code - Also disable PC8 when there's GPU work to do (thanks to Ben for the help on this), so apps can run caster - Enable PC8 on a delayed work function that is delayed for 5 seconds. This makes sure we only enable PC8+ if we're really idle - Make sure we're not in PC8+ when suspending v3: - WARN if IRQs are disabled on __wait_seqno - Replace some DRM_ERRORs with WARNs - Fix calls to restore GT and PM interrupts - Use intel_mark_busy instead of intel_ring_advance to disable PC8 v4: - Use the force_wake, Luke! v5: - Remove the "IIR is not zero" WARNs - Move the force_wake chunk to its own patch - Only restore what's missing from RC6, not everything Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
2013-08-23drm/i915: fix SDEIMR assertion when disabling LCPLLPaulo Zanoni1-6/+2
This was causing WARNs in one machine, so instead of trying to guess exactly which hotplug bits should exist, just do the test on the non-HPD bits. We don't care about the state of the hotplug bits, we just care about the others, that need to be 1. Signed-off-by: Paulo Zanoni <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: Daniel Vetter <[email protected]>
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