Age | Commit message (Collapse) | Author | Files | Lines |
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Need to swap the data fetched over i2c properly. This
is the same fix as the endian fix for aux channel
transactions.
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
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According to the internal teams, we never hit the limit for
mclk switching on these asics, so we can disable the check.
Signed-off-by: Alex Deucher <[email protected]>
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The LCD has a relatively short vblank time (216us), but
the card is able to reclock memory fine in that time.
Signed-off-by: Alex Deucher <[email protected]>
Reported-by: [email protected]
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Disable the UVD block when not in use to save power.
The block is not actually powergated on CI, but we
switch between UVD DPM (where the uvd clocks are
adjusted on demand) and clocks off.
Signed-off-by: Alex Deucher <[email protected]>
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Powergate the UVD block when not in use to save power.
Signed-off-by: Alex Deucher <[email protected]>
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When we PG (powergate) UVD, we need to re-initialize it
before we can use it again.
v2: rebase on UVD stop fixes
Signed-off-by: Alex Deucher <[email protected]>
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Starting on CIK, multi-media blocks like UVD no longer
have special power state. Rather they have their own
DPM implementation which adjusts their clocks dynamically
when active. When they are not active, the blocks are
powergated to save power.
v2: add missing pm locks
v3: rebase on uvd state selection rework
v4: fix inverted logic typo noticed by Christian
Signed-off-by: Alex Deucher <[email protected]>
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Allows you to force the selected performance level via sysfs.
Signed-off-by: Alex Deucher <[email protected]>
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This allows you to look at the current DPM state via
debugfs.
Signed-off-by: Alex Deucher <[email protected]>
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Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.
Signed-off-by: Alex Deucher <[email protected]>
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Allows you to force the selected performance level via sysfs.
Signed-off-by: Alex Deucher <[email protected]>
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This allows you to look at the current DPM state via debugfs.
Signed-off-by: Alex Deucher <[email protected]>
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This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching
Set radeon.dpm=1 to enable.
v2: remove unused radeon_atombios.c changes,
make missing smc ucode non-fatal
Signed-off-by: Alex Deucher <[email protected]>
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This adds dpm support for KB/KV asics. This includes:
- dynamic engine clock scaling
- dynamic voltage scaling
- power containment
- shader power scaling
Set radeon.dpm=1 to enable.
Signed-off-by: Alex Deucher <[email protected]>
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Needed for DPM on CI.
Signed-off-by: Alex Deucher <[email protected]>
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convert from number of lanes to register setting.
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Used for vce power management.
Signed-off-by: Alex Deucher <[email protected]>
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Required for dpm on CI.
Signed-off-by: Alex Deucher <[email protected]>
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Needed for DPM on CI.
Signed-off-by: Alex Deucher <[email protected]>
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Uses a different table format if the board supports EVV.
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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This added support for the on-chip thermal sensors on
CIK asics.
v2: fix register offset.
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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No support for reading temperature back yet.
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Used for uvd power management.
Signed-off-by: Alex Deucher <[email protected]>
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Internally we switched to using a separate header for
atombios pplib definitions. Switch over the open source
driver.
Signed-off-by: Alex Deucher <[email protected]>
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Needed for DPM on KB/KV.
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Only the APUs support power gating.
v2: disable cgcg for now
v3: workaround hw issue in mgcg
Signed-off-by: Alex Deucher <[email protected]>
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and remove duplicate si_rlc functions.
Signed-off-by: Alex Deucher <[email protected]>
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This will eventually be shared with newer asics to
reduce code duplication.
Signed-off-by: Alex Deucher <[email protected]>
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Restructure rlc setup to handle clock and power
gating.
Signed-off-by: Alex Deucher <[email protected]>
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Enables PCIE ASPM (Active State Power Management) on
CIK asics.
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Alex Deucher <[email protected]>
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Required for DPM on CIK.
Signed-off-by: Alex Deucher <[email protected]>
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Calculate the low and high watermarks based on the low and high
clocks for the current power state. The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.
Signed-off-by: Alex Deucher <[email protected]>
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Newer asics don't have specific UVD states.
Signed-off-by: Alex Deucher <[email protected]>
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Newer asics have a lot of vram so it's less of an
issue to waste a little more space for the gart
page table. This gives us some additional gart space
before having to migrate to non-gart system ram
for games, etc. where we use up most of vram.
Signed-off-by: Alex Deucher <[email protected]>
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1. Handle the the thermal state directly in the work handler.
Remove the state selection function since nothing else uses it now.
2. On some asics there is no thermal state, so we just use a regular
state and force the low performance state.
Signed-off-by: Alex Deucher <[email protected]>
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