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2016-02-10drm/amdgpu: move more logic into amdgpu_vm_map_gart v3Christian König5-42/+33
No need to duplicate that code over and over again. Also stop using the flags to determine if we need to map the addresses. v2: constify the pages_addr v3: rebased, fix typo in commit message Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: remove nonsense IB size checksChristian König1-8/+0
Those are just leftovers from the time we wrote the VM updates directly to the ring. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: use WARN_ON_ONCE instead of BUG_ON in the SAChristian König1-2/+5
Crashing the system doesn't helps at all. Also properly return -EINVAL if size or alignment are outside valid ranges. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: drop a dummy wakeup schedulerMonk Liu1-1/+9
since the dependency job is also scheduled by the same scheduler with the job depended on it, no need to call wake up scheduler when the dep is scheduled. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd: add dce8 enum register headerAlex Deucher1-0/+1117
This adds the DCE8 enum header. Acked-by: Harry Wentland <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: add some hwmgr functions for sysfs interface on TongaEric Huang1-0/+123
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: add some hwmgr functions for sysfs interface on CarrizoEric Huang1-0/+51
These add the interfaces for manual clock control. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: add hwmgr's functions for Fiji sysfs interfaces.Eric Huang1-0/+123
These add the interfaces for manual clock control. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: add some sysfs interfaces for powerplay.Eric Huang5-2/+488
The new sysfs interfaces: pp_num_states: Read-only, return the number of all pp states, 0 if powerplay is not available. pp_cur_state: Read-only, return the index number of current pp state. pp_force_state: Read-write, to write a power state index will switch to selected state forcedly and enable forced state mode, disable forced state mode. such as "echo >...". pp_table: Read-write, binary output, to be used to read or write the dpm table, the maximum file size is 4KB of page size. pp_dpm_sclk: Read-write, reading will return a dpm levels list, to write an index number will force powerplay to set the corresponding dpm level. pp_dpm_mclk: same as sclk. pp_dpm_pcie: same as sclk. And add new setting "manual" to the existing interface power_dpm_force_performance_level. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: remove rptr checkingChristian König2-56/+26
With the scheduler enabled we don't need that any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: remove the ring lock v2Christian König15-132/+45
It's not needed any more because all access goes through the scheduler now. v2: Update commit message. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: use a global LRU list for VMIDsChristian König4-58/+55
With the scheduler enabled managing per ring LRUs don't make much sense any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: merge vm_grab_id and vm_fence v2Christian König3-45/+30
No need for an extra function any more. v2: comment cleanups Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: grab VMID before submitting job v5Christian König4-13/+35
This allows the scheduler to handle the dependencies on ID contention as well. v2: grab id only once v3: use a separate lock for the VMIDs v4: cleanup after semaphore removal v5: minor coding style change Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: add VM pointer to id traceChristian König2-6/+9
Because of the scheduler all traces come from the same thread now and can't be distincted otherwise. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: drop hard_reset module parameterAlex Deucher2-5/+0
It doesn't currently do anything and there's no need for it going forward since pci config reset will be required as a fallback even when we have fine grained reset implemented. Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: add a debugfs property to trigger a GPU resetAlex Deucher1-1/+19
Ported from similar code in radeon. Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: post card after hard resetAlex Deucher1-0/+3
Posting is required after a pci config reset. Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: clean up asic level reset for VIAlex Deucher1-381/+4
Drop soft reset, always use pci config reset. Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: clean up asic level reset for CIAlex Deucher1-304/+4
Drop soft reset, always use pci config reset. Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: cleanup sync_seq handlingChristian König3-90/+13
Not used any more without semaphores Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: remove sync_to from sync obj v2Christian König2-36/+9
Not needed any more without semaphores. v2: remove unused variables as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: remove some more semaphore leftoversAlex Deucher12-24/+0
No longer needed since semaphores were removed. Reviewed-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: clean up non-scheduler code path (v2)Chunming Zhou11-110/+64
Non-scheduler code is longer supported. v2: agd: rebased on upstream Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Ken Wang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: cleanup amdgpu_sync_rings V2Chunming Zhou3-51/+3
No longer needed now that semaphores are gone. V2: remove the first amdgpu_sync_wait in amdgpu_ib_schedule Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Ken Wang <[email protected]> (V1) Reviewed-by: Monk Liu <[email protected]> (V2) Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: clean up hw semaphore support in driverChunming Zhou19-724/+17
No longer used. Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Ken Wang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: try to find BO VAs only for the BOs in the listChristian König1-3/+13
The other ones don't have any VAs assigned anyway or are uninteresting to us. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: search only the BO list for VM mappingsChristian König1-7/+13
Make UVD/VCE VM emulation more efficient. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: keep the prefered/allowed domains in the BOChristian König6-34/+29
Stop copying that to the bo list entry, it doesn't change anyway. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: cleanup bo list bucket handlingChristian König3-50/+39
Move that into the BO list. No functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: cleanup amdgpu_cs_parser_relocsChristian König1-11/+10
Rename it to amdgpu_cs_parser_bos and move validation and bo list init there. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: cleanup amdgpu_cs_parser structureChristian König2-11/+11
Remove unused user_ptr field, group fields by usage. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: group VM mapping tree with its lock (v2)Christian König1-2/+3
And also update the comment. v2: agd: rebase on usptream. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: cleanup amdgpu_cs_list_validateChristian König1-35/+31
No need to actually check the current placement. Just use the allowed domains when the threshold is reached. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: fix amdgpu_cs_get_threshold_for_moves handlingChristian König2-9/+14
The threshold should only be computed once. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amd/powerplay: indent a couple if statementsDan Carpenter1-2/+2
We recently redid the indenting, but missed these two if statements. Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: fix issue with overlapping userptrsChristian König3-1/+23
Otherwise we could try to evict overlapping userptr BOs in get_user_pages(), leading to a possible circular locking dependency. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]>
2016-02-10drm/amdgpu: fix issue with overlapping userptrsChristian König3-1/+23
Otherwise we could try to evict overlapping userptr BOs in get_user_pages(), leading to a possible circular locking dependency. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Cc: [email protected]
2016-02-10drm/radeon: hold reference to fences in radeon_sa_bo_newNicolai Hähnle1-0/+5
An arbitrary amount of time can pass between spin_unlock and radeon_fence_wait_any, so we need to ensure that nobody frees the fences from under us. Based on the analogous fix for amdgpu. Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected]
2016-02-10drm/amdgpu: remove unnecessary forward declarationNicolai Hähnle1-2/+0
Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected]
2016-02-10drm/amdgpu: hold reference to fences in amdgpu_sa_bo_new (v2)Nicolai Hähnle1-1/+4
An arbitrary amount of time can pass between spin_unlock and fence_wait_any_timeout, so we need to ensure that nobody frees the fences from under us. A stress test (rapidly starting and killing hundreds of glxgears instances) ran into a deadlock in fence_wait_any_timeout after about an hour, and this race condition appears to be a plausible cause. v2: agd: rebase on upstream Signed-off-by: Nicolai Hähnle <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Cc: [email protected]
2016-02-10drm/amdgpu: fix s4 resumeFlora Cui1-4/+9
No need to re-init asic if it's already been initialized. Skip IB tests since kernel processes are frozen in thaw. Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: [email protected]
2016-02-10drm/i915: fix error path in intel_setup_gmbus()Rasmus Villemoes1-1/+1
This fails to undo the setup for pin==0; moreover, something interesting happens if the setup failed already at pin==0. Signed-off-by: Rasmus Villemoes <[email protected]> Fixes: f899fc64cda8 ("drm/i915: use GMBUS to manage i2c links") Cc: [email protected] Signed-off-by: Jani Nikula <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 2417c8c03f508841b85bf61acc91836b7b0e2560) Signed-off-by: Jani Nikula <[email protected]>
2016-02-10drm/i915/skl: Fix typo in DPLL_CFGCR1 definitionLyude1-1/+1
We accidentally point both cfgcr registers for the second shared DPLL to the same location in i915_reg.h. This results in a lot of hw pipe state mismatches whenever we try to do a modeset that requires allocating the DPLL to a CRTC: [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x80000168, found 0x000004a5) [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 108000, found 49500) [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 108000, found 49500) This usually ends up causing blank monitors, since the DPLL never can get set to the right clock. Fixes: 086f8e84a085 ("drm/i915: Prefix raw register defines with underscore") Signed-off-by: Lyude <[email protected]> Cc: [email protected] Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit da3b891b0fb88605bb2d16adaf1ef2a1f16403ba) Signed-off-by: Jani Nikula <[email protected]>
2016-02-10drm/i915/skl: Don't skip mst encoders in skl_ddi_pll_select()Lyude1-1/+2
We don't actually check for INTEL_OUTPUT_DP_MST at all in here, as a result we skip assigning a DPLL to any DP MST ports, which makes link training fail: [ 1442.933896] [drm:intel_power_well_enable] enabling DDI D power well [ 1442.933905] [drm:skl_set_power_well] Enabling DDI D power well [ 1442.933957] [drm:intel_mst_pre_enable_dp] 0 [ 1442.935474] [drm:intel_dp_set_signal_levels] Using signal levels 00000000 [ 1442.935477] [drm:intel_dp_set_signal_levels] Using vswing level 0 [ 1442.935480] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 0 [ 1442.936190] [drm:intel_dp_set_signal_levels] Using signal levels 05000000 [ 1442.936193] [drm:intel_dp_set_signal_levels] Using vswing level 1 [ 1442.936195] [drm:intel_dp_set_signal_levels] Using pre-emphasis level 1 [ 1442.936858] [drm:intel_dp_set_signal_levels] Using signal levels 08000000 [ 1442.936862] [drm:intel_dp_set_signal_levels] Using vswing level 2 … [ 1442.998253] [drm:intel_dp_link_training_clock_recovery [i915]] *ERROR* too many full retries, give up [ 1442.998512] [drm:intel_dp_start_link_train [i915]] *ERROR* failed to train DP, aborting After which the pipe state goes completely out of sync: [ 70.075596] [drm:check_crtc_state] [CRTC:25] [ 70.075696] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in ddi_pll_sel (expected 0x00000000, found 0x00000001) [ 70.075747] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in shared_dpll (expected -1, found 0) [ 70.075798] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.ctrl1 (expected 0x00000000, found 0x00000021) [ 70.075840] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr1 (expected 0x00000000, found 0x80400173) [ 70.075884] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in dpll_hw_state.cfgcr2 (expected 0x00000000, found 0x000003a5) [ 70.075954] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in base.adjusted_mode.crtc_clock (expected 262750, found 72256) [ 70.075999] [drm:intel_pipe_config_compare [i915]] *ERROR* mismatch in port_clock (expected 540000, found 148500) And if you're especially lucky, it keeps going downhill: [ 83.309256] Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast exception handler [ 83.309265] [ 83.309265] ================================= [ 83.309266] [ INFO: inconsistent lock state ] [ 83.309267] 4.5.0-rc1Lyude-Test #265 Not tainted [ 83.309267] --------------------------------- [ 83.309268] inconsistent {IN-HARDIRQ-W} -> {HARDIRQ-ON-W} usage. [ 83.309270] Xorg/1194 [HC0[1]:SC0[0]:HE1:SE1] takes: [ 83.309293] (&(&dev_priv->uncore.lock)->rlock){?.-...}, at: [<ffffffffa02a6073>] gen9_write32+0x63/0x400 [i915] [ 83.309293] {IN-HARDIRQ-W} state was registered at: [ 83.309297] [<ffffffff810e84f4>] __lock_acquire+0x9c4/0x1d00 [ 83.309299] [<ffffffff810ea1be>] lock_acquire+0xce/0x1c0 [ 83.309302] [<ffffffff8177d936>] _raw_spin_lock_irqsave+0x56/0x90 [ 83.309321] [<ffffffffa02a5492>] gen9_read32+0x52/0x3d0 [i915] [ 83.309332] [<ffffffffa024beea>] gen8_irq_handler+0x27a/0x6a0 [i915] [ 83.309337] [<ffffffff810fdbc1>] handle_irq_event_percpu+0x41/0x300 [ 83.309339] [<ffffffff810fdeb9>] handle_irq_event+0x39/0x60 [ 83.309341] [<ffffffff811010b4>] handle_edge_irq+0x74/0x130 [ 83.309344] [<ffffffff81009073>] handle_irq+0x73/0x120 [ 83.309346] [<ffffffff817805f1>] do_IRQ+0x61/0x120 [ 83.309348] [<ffffffff8177e6d6>] ret_from_intr+0x0/0x20 [ 83.309351] [<ffffffff815f5105>] cpuidle_enter_state+0x105/0x330 [ 83.309353] [<ffffffff815f5367>] cpuidle_enter+0x17/0x20 [ 83.309356] [<ffffffff810dbe1a>] call_cpuidle+0x2a/0x50 [ 83.309358] [<ffffffff810dc1dd>] cpu_startup_entry+0x26d/0x3a0 [ 83.309360] [<ffffffff817701da>] rest_init+0x13a/0x140 [ 83.309363] [<ffffffff81f2af8e>] start_kernel+0x475/0x482 [ 83.309365] [<ffffffff81f2a315>] x86_64_start_reservations+0x2a/0x2c [ 83.309367] [<ffffffff81f2a452>] x86_64_start_kernel+0x13b/0x14a Fixes: 82d354370189 ("drm/i915/skl: Implementation of SKL DPLL programming") Signed-off-by: Lyude <[email protected]> Cc: [email protected] Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 78385cb398748debb7ea2e36d6d2001830c172bc) Signed-off-by: Jani Nikula <[email protected]>
2016-02-10drm: fixes when i2c encoder slave mode_fixup is null.Carlos Palminha1-0/+3
Avoid i2c slave encoder drivers to copy/paste code to implement functions that will only return true. Signed-off-by: Carlos Palminha <[email protected]> [danvet: whitespace requested by Jani.] Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2016-02-10drm: Add support for ARM's HDLCD controller.Liviu Dudau8-0/+1038
The HDLCD controller is a display controller that supports resolutions up to 4096x4096 pixels. It is present on various development boards produced by ARM Ltd and emulated by the latest Fast Models from the company. Cc: David Airlie <[email protected]> Cc: Robin Murphy <[email protected]> Signed-off-by: Liviu Dudau <[email protected]> [Kconfig cleanup and !CONFIG_PM fixes] Signed-off-by: Arnd Bergmann <[email protected]> Acked-by: Daniel Vetter <[email protected]>
2016-02-10drm/imx: Add missing DRM_FORMAT_RGB565 to ipu_plane_formatsEnrico Jorns1-0/+1
DRM_FORMAT_RGB565 is missing from ipu_plane_formats. The support is there, just need to make it available to userspace. Signed-off-by: Enrico Jorns <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
2016-02-10drm/imx: notify DRM core about CRTC vblank stateLucas Stach1-0/+2
Make sure the DRM core is aware that there will be no vblank interrupts incoming if the CRTC is disabled. That way the core will reject any attempts from userspace to wait on a vblank event on a disabled CRTC. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
2016-02-10gpu: ipu-v3: Reset IPU before activating IRQDavid Jander1-5/+5
If we don't come out of a clean reset, make sure no IRQ is fired before everything is setup by resetting the IPU before activating the interrupt handlers. Signed-off-by: David Jander <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
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