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2022-06-21drm/amd/display: Fix in dp link-training when updating payload allocation tableDmytro Laktyushkin1-4/+9
[Why & How] Check if aux is not accessible before updating payload allocation table. Tested-by: Daniel Wheeler <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: extract update stream allocation to link_hwssWenjing Liu2-6/+10
[Why & How] Extract update stream allocation table into link hwss as part of the link hwss refactor work. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Remove unused vendor specific w/aGeorge Shen2-130/+4
[Why & How] Old vendor specific w/a are no longer needed and unused. Clean up codebase by removing them. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Handle downstream LTTPR with fixed VS sequenceGeorge Shen3-6/+40
[Why] Several issues were discovered that caused link training to fail when an LTTPR device is connected downstream for the fixed VS sequence. [How] The following were added: - workaround to configure AUX timeout for fixed VS sequence - additional delay before disabling fixed VS intercept - detection of fixed VS deadlock state and performing DPCD sequence to recover Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Fix typo in override_lane_settingsGeorge Shen1-1/+1
[Why] The function currently skips overriding the drive settings of the first lane. [How] Change for loop to start at 0 instead of 1. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Change initializer to single braceAric Cyr3-19/+19
[Why & How] Change struct initializer from multiple brace to single brace. Tested-by: Daniel Wheeler <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: rename lane_settings to hw_lane_settingsWenjing Liu4-15/+14
[why] This is one of the major steps to decouple hw lane settings from dpcd lane settings. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Fix in overriding DP drive settingsGeorge Shen1-2/+3
[Why & How] Check always_match_dpcd_with_hw_lane_settings bit before overriding the DP drive settings Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Enrich the log in MST payload updateWenjing Liu1-0/+6
[Why & How] Enrich the log to provide more informatio in MST payload update. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Ariel Bernstein <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Change HDMI judgement condition.JinZe.Xu1-1/+1
[Why & How] Use dc_is_hdmi_signal to determine signal type. Tested-by: Daniel Wheeler <[email protected]> Acked-by: Alan Liu <[email protected]> Signed-off-by: JinZe.Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Fix DC warning at driver loadQingqing Zhuo1-1/+1
[Why] Wrong index was checked for dcfclk_mhz, causing false warning. [How] Fix the assertion index. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Add SMU logging codeSaaem Rizvi5-0/+48
[WHY] Logging for SMU response value after the wait allows us to know immediately what the response value was. Makes it easier to debug should the value be anything other than OK. [HOW] Using the the already available DC SMU logging functions. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Saaem Rizvi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Turn off internal backlight when plugging external monitorSung Joon Kim1-2/+1
[why] For VG, we want to turn off power/backlight of the intenral panel when plugging in external monitor and going to "external monitor only" mode. [how] For turning off power of the internal panel, ignore the config flag whic bypasses power sequencing for eDP panels. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Fix eDP not light up on resumeSung Joon Kim3-1/+13
[why] Only on VG, if external display is disconnected during S3 suspend, the internal panel doesn't light up on resume because we set the power state using an unsupported DPCD register SET_POWER. To check the register is supported, we need to check SET_POWER_CAPABLE first which is eDP-specific DPCD register field. [how] Check the SET_POWER_CAPABLE register field and decide the control of the eDP power state based on the read register value. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Agustin Gutierrez <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: add mst port output bw checkhersen wu4-3/+48
[Why] when connect one 4k@144hz dp to dsc mst hub, 4k@144hz mode is in valid mode list. but some mst hub port output bandwidth does not support 4k@144hz. [How] add mst port output bandwidth checks, include full_pbn, branch max throughput mps. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: hersen wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Drop unnecessary detect link codeIan Chen1-5/+0
Delete unnecessary codes in detect_link_and_local_sink. We already have correct stop logic in dc_link_detect. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Ian Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Take emulated dc_sink into account for HDCPWayne Lin1-4/+10
[Why] While updating the config of hdcp, we use the sink_singal type of the dc_sink to decide the HDCP operation mode. However, it doesn't consider the case when the sink is a emulated one. [How] Take dc_em_sink into account while updating HDCP config. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aurabindo Jayamohanan Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Release remote dc_sink under mst scenarioWayne Lin3-22/+35
[Why] Observe that we have several problems while releasing remote dc_sink under mst cases. - When unplug mst branch device from the source, we now try to free all remote dc_sinks in dm_helpers_dp_mst_stop_top_mgr(). However, there are bugs while we're releasing dc_sinks here. First of all, link->remote_sinks[] array get shuffled within dc_link_remove_remote_sink(). As the result, increasing the array index within the releasing loop is wrong. Secondly, it tries to call dc_sink_release() to release the dc_sink of the same aconnector every time in the loop. Which can't release dc_sink of all aconnector in the mst topology. - There is no code path for us to release remote dc_sink for disconnected sst monitor which unplug event is notified by CSN sideband message. Which means we'll use stale dc_sink data to represent later on connected monitor. Also, has chance to break the maximum remote dc_sink number constraint. [How] Distinguish unplug event of mst scenario into 2 cases. * Unplug sst/legacy stream sink off the mst topology - Release related remote dc_sink in detec_ctx(). * Unplug mst branch device off the mst topology - Release related remote dc_sink in early_unregister() Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aurabindo Jayamohanan Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Acked-by: Lyude Paul <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Revert "drm/amd/display: turn DPMS off on connector unplug"Wayne Lin3-45/+0
This reverts commit 3c4d55c9b9becedd8d31a7c96783a364533713ab. Revert the commit because: - It's incomplete of the function dm_set_dpms_off() for mst case. For stream sinks whithin the same mst topology, they share the same dc_link. dm_set_dpms_off() tries to update one mst stream only which is incomplete. - Setting dpms off should be triggered by usermode. Besdies, it seems usermode does release relevant resource for mst & non-mst case when unplug connecotr now. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aurabindo Jayamohanan Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Acked-by: Lyude Paul <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Revert "drm/amd/display: Add flag to detect dpms force off ↵Wayne Lin3-25/+11
during HPD" This reverts commit 035f54969bb2c1a5ced52f43e4ef393e0c0f6bfa. The reverted commit was trying to fix side effect brought by commit 3c4d55c9b9be ("drm/amd/display: turn DPMS off on connector unplug") However, * This reverted commit will have mst case never call dm_set_dpms_off() which conflicts the idea of original commit 3c4d55c9b9be ("drm/amd/display: turn DPMS off on connector unplug") That's due to dm_crtc_state is always null since the input parameter aconnector is the root device (source) of mst topology. It's not an end stream sink within the mst topology. * Setting dpms off should be triggered by usermode. Besdies, it seems usermode does release relevant resource for mst & non-mst case when unplug connecotr now. Which means we no longer need both commits now: commit 3c4d55c9b9be ("drm/amd/display: turn DPMS off on connector unplug") commit 035f54969bb2 ("drm/amd/display: Add flag to detect dpms force off during HPD") Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aurabindo Jayamohanan Pillai <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Acked-by: Lyude Paul <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd: Revert "drm/amd/display: keep eDP Vdd on when eDP stream is already ↵Mario Limonciello1-22/+2
enabled" A variety of Lenovo machines with Rembrandt APUs and OLED panels have stopped showing the display at login. This behavior clears up after leaving it idle and moving the mouse or touching keyboard. It was bisected to be caused by commit 559e2655220d ("drm/amd/display: keep eDP Vdd on when eDP stream is already enabled"). Revert this commit to fix the issue. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2047 Reported-by: Aaron Ma <[email protected]> Fixes: 559e2655220d ("drm/amd/display: keep eDP Vdd on when eDP stream is already enabled") Signed-off-by: Mario Limonciello <[email protected]> Tested-by: Mark Pearson <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: Remove compiler warningCruise Hung1-1/+1
Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Cruise Hung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu: add LSDMA block for LSDMA v6.0.1Yifan Zhang1-0/+1
This patch adds LSDMA ip block for LSDMA v6.0.1. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: add missing reg defs for DCN3x HUBBUBAurabindo Pillai5-0/+13
[Why&How] The omitted register definition caused call traces like: [ 3.811215] WARNING: CPU: 7 PID: 794 at drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.c:120 set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu] [ 3.811406] Modules linked in: amdgpu(+) drm_ttm_helper ttm iommu_v2 gpu_sched drm_kms_helper cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea drm i2c_piix4 drm_panel_orientation_quirks [ 3.811419] CPU: 7 PID: 794 Comm: systemd-udevd Not tainted 5.16.0-kfd+ #132 [ 3.811422] Hardware name: System manufacturer System Product Name/ROG STRIX B450-F GAMING, BIOS 3003 12/09/2019 [ 3.811425] RIP: 0010:set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu] [ 3.811615] Code: 08 49 89 51 08 8b 08 48 8d 42 08 49 89 41 08 44 8b 02 48 8d 50 08 0f b6 c9 49 89 51 08 8b 00 45 85 c0 75 b3 0f 0b eb af 5d c3 <0f> 0b e9 48 ff ff ff 49 8b 51 08 eb d0 49 8b 41 08 eb d5 66 0f 1f [ 3.811619] RSP: 0018:ffffb8c1c04cf640 EFLAGS: 00010246 [ 3.811621] RAX: 0000000000000000 RBX: ffff96f2100d8800 RCX: 0000000000000000 [ 3.811623] RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffffb8c1c04cf650 [ 3.811625] RBP: ffffb8c1c04cf640 R08: 000000000000047f R09: ffffb8c1c04cf658 [ 3.811627] R10: ffff96f5161ff000 R11: ffff96f5161ff000 R12: ffff96f204afb9c0 [ 3.811629] R13: 0000000000000000 R14: ffff96f202b94c00 R15: ffffb8c1c04cf718 [ 3.811631] FS: 00007fe07c2e2880(0000) GS:ffff96f5059c0000(0000) knlGS:0000000000000000 [ 3.811634] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3.811636] CR2: 0000559634ab57b8 CR3: 0000000120674000 CR4: 00000000003506e0 [ 3.811637] Call Trace: [ 3.811640] <TASK> [ 3.811642] generic_reg_update_ex+0x69/0x200 [amdgpu] [ 3.811831] ? _printk+0x58/0x6f [ 3.811836] dcn32_init_crb+0x18f/0x1b0 [amdgpu] [ 3.812031] dcn32_init_hw+0x379/0x6a0 [amdgpu] [ 3.812223] dc_hardware_init+0xba/0x100 [amdgpu] [ 3.812415] amdgpu_dm_init.isra.0.cold+0x166/0x1867 [amdgpu] [ 3.812616] ? dev_vprintk_emit+0x139/0x15d [ 3.812621] ? dev_printk_emit+0x4e/0x65 [ 3.812624] dm_hw_init+0x12/0x30 [amdgpu] [ 3.812820] amdgpu_device_init.cold+0x130d/0x178c [amdgpu] [ 3.813017] ? pci_read_config_word+0x25/0x40 [ 3.813021] amdgpu_driver_load_kms+0x1a/0x130 [amdgpu] [ 3.813178] amdgpu_pci_probe+0x130/0x330 [amdgpu] Fixes: 4f29f9cf092b ("drm/amd: add register headers for DCN32/321") Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd: Don't show warning on reading vbios values for SMU13 3.1Mario Limonciello1-0/+2
Some APUs with SMU13 are showing the following message: `amdgpu 0000:63:00.0: amdgpu: Unexpected and unhandled version: 3.1` This warning isn't relevant for smu info 3.1, as no bootup information is present in the table. Fixes: 593a54f18031 ("drm/amd/pm: correct the way for retrieving bootup clocks") Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/pm: skip to set mp1 unload state in special caseYang Wang1-5/+6
set mp1 unload state will cause the SMC FW can't accept any SMU message, skip to set mp1 unload state to avoid following case fail: - runtime pm case. - gpu reset case. Fixes: 72aeb6ee0c78 ("drm/amd/pm: fix driver reload SMC firmware fail issue for smu13") Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu/gmc11: avoid cpu accessing registers to flush VMJack Xiao1-1/+50
Due to gfxoff on, cpu accessing registers is not expected. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu/pm: adjust EccInfo_t structStanley.Yang1-1/+2
The EccInfo_t struct in driver_if.h is as below in official release verion 68.55.0 typedef struct { uint64_t mca_umc_status; uint64_t mca_umc_addr; uint16_t ce_count_lo_chip; uint16_t ce_count_hi_chip; uint32_t eccPadding; uint64_t mca_ceumc_addr; } EccInfo_t; It's different from the debug version druing develop print correctable error address, so adjust EccInfo_t struct. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu: Adjust logic around GTT size (v3)Alex Deucher1-6/+14
Certain GL unit tests for large textures can cause problems with the OOM killer since there is no way to link this memory to a process. This was originally mitigated (but not necessarily eliminated) by limiting the GTT size. The problem is this limit is often too low for many modern games so just make the limit 1/2 of system memory. The OOM accounting needs to be addressed, but we shouldn't prevent common 3D applications from being usable just to potentially mitigate that corner case. Set default GTT size to max(3G, 1/2 of system ram) by default. v2: drop previous logic and default to 3/4 of ram v3: default to half of ram to align with ttm v4: fix spelling in comment (Kent) Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1942 Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/radeon: fix incorrrect SPDX-License-IdentifiersAlex Deucher3-3/+3
radeon is MIT. This were incorrectly changed in commit b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") and commit d198b34f3855 (".gitignore: add SPDX License Identifier") and: commit ec8f24b7faaf ("treewide: Add SPDX license identifier - Makefile/Kconfig") Fixes: d198b34f3855 (".gitignore: add SPDX License Identifier") Fixes: ec8f24b7faaf ("treewide: Add SPDX license identifier - Makefile/Kconfig") Fixes: b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2053 Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu: Remove break for VMID loop TLB flush on MESGraham Sider2-2/+2
Loop through all VMIDs for gmc_v10_0_flush_gpu_tlb_pasid and gmc_v11_0_flush_gpu_tlb_pasid (only if using MES for gmc_v10). This is required for MES due to use_different_vmid_compute causing SDMA queues to be assigned different VMIDs than compute for the same PASID. Signed-off-by: Graham Sider <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu/vcn: adjust unified queue code formatRuijing Dong2-10/+10
Fixed some errors and warnings found by checkpatch.pl. Acked-by: Christian König <[email protected]> Signed-off-by: Ruijing Dong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu/vcn: support unified queue only in vcn4Ruijing Dong1-423/+140
- remove multiple queue support - add unified queue related functions Acked-by: Leo Liu <[email protected]> Signed-off-by: Ruijing Dong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu/vcn: add unified queue ib testRuijing Dong2-3/+100
- add unified queue headers - add unified queue ib tests Acked-by: Leo Liu <[email protected]> Signed-off-by: Ruijing Dong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-15drm/amd/display: Drop unnecessary guard from DC resourceRodrigo Siqueira1-2/+0
Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amdgpu/display: make FP handling in Makefiles consistentAlex Deucher6-12/+16
Use the same pattern as the DML Makefile and while we are here add a missing x86 guard around the msse flags for DCN3.2.x. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14Revert "drm/amdgpu/display: Protect some functions with CONFIG_DRM_AMD_DC_DCN"Alex Deucher1-4/+0
This reverts commit d8e4fb9112e88d8d87ffbc38fa511e7118042d4f. This is no longer necessary as newer patches require these functions without CONFIG_DRM_AMD_DC_DCN. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amdkfd: fix warning when CONFIG_HSA_AMD_P2P is not setAlex Deucher1-2/+5
drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.c:1542:11: warning: variable 'i' set but not used [-Wunused-but-set-variable] Reviewed-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Reported-by: kernel test robot <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amdgpu: remove redundant enable_mes and enable_mes_kiqYifan Zhang1-8/+0
enable_mes and enable_mes_kiq are set in both device init and MES IP init. Leave the ones in MES IP init, since it is a more accurate way to judge from GC IP version. Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: Blank for uclk OC in dm instead of dcJoshua Aberback2-30/+14
[Why] All displays need to be blanked during the uclk OC interface so that we can guarantee pstate switching support. If the display config doesn't support pstate switching, only using core_link_disable_stream will not enable it as the front-end is untouched. We need to go through the full plane removal sequence to properly program the pipe to allow pstate switching. [How] - guard clk_mgr functions with non-NULL checks Acked-by: Alan Liu <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: Add null check to dc_submit_i2c_oemMartin Leung1-4/+7
[why] dc_submit_i2c_oem could be called with ddc null [how] add null check and fail the call instead Acked-by: Alan Liu <[email protected]> Signed-off-by: Martin Leung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: FVA timing adjustmentCharlene Liu1-0/+1
[why] need to add timing adjustment for fva. [how] add hook to optc and hwseq. Acked-by: Alan Liu <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: Add vrr_active_variable to dc_stream_updateHarry VanZyllDeJong4-3/+6
[WHY] The display driver on some OSes need to track it in order to perform memory clock switching decisions. [HOW] Propagate the vrr active state to dirty bit so that on mode set it disables dynamic memory clock switching. Acked-by: Alan Liu <[email protected]> Signed-off-by: Harry VanZyllDeJong <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: Pass vrr mode to dcnFelipe Clark1-0/+1
[WHY] New features will require knowing the vrr mode for their enablement. [HOW] Pass the state via a member of dc_stream. Acked-by: Alan Liu <[email protected]> Signed-off-by: Felipe Clark <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: Adding VTEM to dcAhmad Othman6-2/+23
[Why] Video Timing Extended Metadata packet (VTEM) is required for features like VRR and FVA [How] Adding support for VTEM transmission to stream encoders in DCN20 and DCN30 as part of FVA support Acked-by: Alan Liu <[email protected]> Signed-off-by: Ahmad Othman <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: Copy hfvsif_infopacket when stream updateNicholas Kazlauskas1-0/+3
[Why & How] Miss to copy hfvsif_infopacket when copying stream updates. Check and copy it. Acked-by: Alan Liu <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: Add support for HF-VSIFAhmad Othman4-4/+20
[Why] - Currently there is no support for HF-VSIF - The current support of VSIF is limited to H14b infoframe [How] - refactor VSIF - Added new builder for HF-VSIF - Added the HF-VSIF packet to DisplayTarget - Updates DC to apply HF-VSIF updates when updating streams Acked-by: Alan Liu <[email protected]> Signed-off-by: Ahmad Othman <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: Firmware assisted MCLK switch and FSFelipe Clark14-22/+51
[WHY] Memory clock switching has great potential for power savings. [HOW] The driver code was modified to notify the DMCUB firmware that it should stretch the vertical blank of frames when a memory clock switch is about to start so that no blackouts happen on the screen due to unavailability of the frame buffer. The driver logic to determine when such firmware assisted strategy can be initiated is also implemented and consists on checking prerequisites of the feature. Acked-by: Alan Liu <[email protected]> Signed-off-by: Felipe Clark <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: DAL ACR, dc part, fix missing dcn30Ian Chen2-8/+25
[Why] - missing in dcn30 function - Fix a divide by 0 when ACR trigger [How] - Add IS_SMU_TIMEOUT() to dcn30_smu_send_msg_with_param - Add zero check in dcn20_update_clocks_update_dentist Acked-by: Alan Liu <[email protected]> Signed-off-by: Ian Chen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-14drm/amd/display: Fix commentsSamson Tam5-25/+37
[Why & how] Fix format and typo of comments. Acked-by: Alan Liu <[email protected]> Signed-off-by: Samson Tam <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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