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2021-02-11drm/nouveau/engine: use refcount_t + private mutexBen Skeggs2-13/+25
nvkm_subdev.mutex is going away. Signed-off-by: Ben Skeggs <[email protected]> Reviewed-by: Lyude Paul <[email protected]>
2021-02-10Revert "drm/scheduler: Job timeout handler returns status (v3)"Maarten Lankhorst6-37/+25
This reverts commit c10983e14e8f5d7c8dab0415e0cb7fe8d10aa9e3. This commit is not meant for drm-misc-next-fixes, and was accidentally cherry picked over. Signed-off-by: Maarten Lankhorst <[email protected]>
2021-02-10drm/sun4i: dw-hdmi: Fix max. frequency for H6Jernej Skrabec1-4/+2
It turns out that reasoning for lowering max. supported frequency is wrong. Scrambling works just fine. Several now fixed bugs prevented proper functioning, even with rates lower than 340 MHz. Issues were just more pronounced with higher frequencies. Fix that by allowing max. supported frequency in HW and fix the comment. Fixes: cd9063757a22 ("drm/sun4i: DW HDMI: Lower max. supported rate for H6") Reviewed-by: Chen-Yu Tsai <[email protected]> Tested-by: Andre Heider <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-10drm/sun4i: Fix H6 HDMI PHY configurationJernej Skrabec1-17/+9
As it turns out, vendor HDMI PHY driver for H6 has a pretty big table of predefined values for various pixel clocks. However, most of them are not useful/tested because they come from reference driver code. Vendor PHY driver is concerned with only few of those, namely 27 MHz, 74.25 MHz, 148.5 MHz, 297 MHz and 594 MHz. These are all frequencies for standard CEA modes. Fix sun50i_h6_cur_ctr and sun50i_h6_phy_config with the values only for aforementioned frequencies. Table sun50i_h6_mpll_cfg doesn't need to be changed because values are actually frequency dependent and not so much SoC dependent. See i.MX6 documentation for explanation of those values for similar PHY. Fixes: c71c9b2fee17 ("drm/sun4i: Add support for Synopsys HDMI PHY") Tested-by: Andre Heider <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-10drm/sun4i: dw-hdmi: always set clock rateJernej Skrabec2-4/+1
As expected, HDMI controller clock should always match pixel clock. In the past, changing HDMI controller rate would seemingly worsen situation. However, that was the result of other bugs which are now fixed. Fix that by removing set_rate quirk and always set clock rate. Fixes: 40bb9d3147b2 ("drm/sun4i: Add support for H6 DW HDMI controller") Reviewed-by: Chen-Yu Tsai <[email protected]> Tested-by: Andre Heider <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-10drm/sun4i: tcon: set sync polarity for tcon1 channelJernej Skrabec2-0/+31
Channel 1 has polarity bits for vsync and hsync signals but driver never sets them. It turns out that with pre-HDMI2 controllers seemingly there is no issue if polarity is not set. However, with HDMI2 controllers (H6) there often comes to de-synchronization due to phase shift. This causes flickering screen. It's safe to assume that similar issues might happen also with pre-HDMI2 controllers. Solve issue with setting vsync and hsync polarity. Note that display stacks with tcon top have polarity bits actually in tcon0 polarity register. Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support") Reviewed-by: Chen-Yu Tsai <[email protected]> Tested-by: Andre Heider <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-02-10drm/i915: Fix overlay frontbuffer trackingVille Syrjälä1-9/+8
We don't have a persistent fb holding a reference to the frontbuffer object, so every time we do the get+put we throw the frontbuffer object immediately away. And so the next time around we get a pristine frontbuffer object with bits==0 even for the old vma. This confuses the frontbuffer tracking code which understandably expects the old frontbuffer to have the overlay's bit set. Fix this by hanging on to the frontbuffer reference until the next flip. And just to make this a bit more clear let's track the frontbuffer explicitly instead of just grabbing it via the old vma. Cc: [email protected] Cc: Chris Wilson <[email protected]> Cc: Joonas Lahtinen <[email protected]> Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/1136 Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Fixes: 8e7cb1799b4f ("drm/i915: Extract intel_frontbuffer active tracking") Reviewed-by: Chris Wilson <[email protected]> (cherry picked from commit 553c23bdb4775130f333f07a51b047276bc53f79) Signed-off-by: Jani Nikula <[email protected]>
2021-02-09Revert "drm/amd/display: Update NV1x SR latency values"Alex Deucher1-2/+2
This reverts commit 4a3dea8932d3b1199680d2056dd91d31d94d70b7. This causes blank screens for some users. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1482 Cc: Alvin Lee <[email protected]> Cc: Jun Lei <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-02-09drm/radeon: Simplify bool comparisonJiapeng Chong1-1/+1
Fix the following coccicheck warning: ./drivers/gpu/drm/radeon/rs690.c:190:6-35: WARNING: Comparison to bool. Reported-by: Abaci Robot <[email protected]> Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: Simplify bool comparisonJiapeng Chong1-2/+2
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h:319:11-23: WARNING: Comparison to bool. Reported-by: Abaci Robot <[email protected]> Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09Revert "drm/amd/display: Update NV1x SR latency values"Alex Deucher1-2/+2
This reverts commit 4a3dea8932d3b1199680d2056dd91d31d94d70b7. This causes blank screens for some users. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1388 Cc: Alvin Lee <[email protected]> Cc: Jun Lei <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-02-09drm/amdgpu: fix unnecessary NULL check warningsTian Tao1-2/+1
Remove NULL checks before vfree() to fix these warnings: drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c:102:2-8: WARNING: NULL check before some freeing functions is not needed. Signed-off-by: Tian Tao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm: make the error log more clear for fine grain tuning functionXiaojian Du3-3/+5
This patch is to make the error log more clear for fine grain tuning function, it covers Raven/Raven2/Picasso/Renoir/Vangogh. The fine grain tuning function uses the sysfs file -- pp_od_clk_voltage, but only when another sysfs file -- power_dpm_force_performance_level is switched to "manual" mode, it is allowed to access "pp_od_clk_voltage". Signed-off-by: Xiaojian Du <[email protected]> Acked-by: Huang Rui <[email protected]> Acked-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: extend MAX_KIQ_REG_TRY to 1000Jiawei Gu1-1/+1
Extend retry times of KIQ to avoid starvation situation caused by long time full access of GPU by other VFs. Signed-off-by: Jiawei Gu <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: 3.2.122Aric Cyr1-1/+1
This version brings along following fixes: - Fix error handling in dc/dcn10/dcn10_hw_sequencer_debug.c - DIO Supported for virtual displays - memset dmub_rb_cmd to 0 which fixes issues talking with firmware - fix 64bit division issue on 32bit OS - move edp sink present detection to hw init to fix hang - reverts a patch that caused 3x4K60 displays over MST with DSC enabled to not light up Signed-off-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: [FW Promotion] Release 0.0.51Anthony Koo1-4/+25
Add new definition and union for dmub_rb_cmd_dig1_transmitter_control Signed-off-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: fix type mismatch error for return variableDale Zhao1-1/+1
It is possible for ret_vsnprintf to be assigned negative value in error cases. As an unsigned variable, negative values which are stored in their 2's complement form gets treated as a positive number. This will led to treating bad cases as good ones. eg: -1 gets stored as 0xFFFFFFFF on a 32 bit system Signed-off-by: Dale Zhao <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: DIO Supported for virtual displaysWesley Chalmers8-10/+19
[WHY] Virtual displays do not use the backend of the pipe, and so have infinite backend bandwidth. [HOW] Add a skip_dio_check bool to the VBA struct, which is used to override the DIOSupport calculations. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Acked-by: Chris Park <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: Initialize dmub_rb_cmd unions to 0Wyatt Wood4-3/+13
[Why] Since dmub_rb_cmds are not initialized to 0, the header is filled with invalid data. This is causing issues on the fw side. [How] Initialize dmub_rb_cmd unions to 0. Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Josip Pavic <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: fix 64bit division issue on 32bit OSLang Yu3-4/+5
Replace "/" with div_u64 for 64bit division on 32bit OS. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: move edp sink present detection to hw initEric Yang2-18/+24
[Why] At SW init, we may not be ready to do detect eDP sink. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: revert support for DID2.0 dsc passthroughJun Lei3-23/+14
3x4K60 displays over MST with DSC enabled was not able to light up due to this patch. Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: DP HDCP Compliance 1A-08/09 tests failQingqing Zhuo1-0/+2
[Why] Current implementation of mod_hdcp_hdcp2_validate_ake_cert() does not process HDCP status message TA_HDCP2_MSG_AUTHENTICATION_STATUS__SIGNATURE_CERTIFICAT_ERROR. As a result, when there is a signature certificate error, mod_hdcp_hdcp2_validate_ake_cert would return the default status, which is success. [How] For all messages other than TA_HDCP2_MSG_AUTHENTICATION_STATUS__SUCCESS and TA_HDCP2_MSG_AUTHENTICATION_STATUS__RECEIVERID_REVOKED, return status as failure. Signed-off-by: Qingqing Zhuo <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: Add DIG_CLOCK_PATTERN in the transmitter controlDerek Lai3-1/+27
[Why and How] VBIOS program DIG_CLK_PATTERN using engine ID instead of PHY ID. Workaround by writing value for 0x1f (for HDMI) after calling vbios. Signed-off-by: Derek Lai <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: Add return code instead of boolean for future useFangzhi Zuo1-4/+4
Signed-off-by: Fangzhi Zuo <[email protected]> Reviewed-by: Mikita Lipski <[email protected]> Acked-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: enable gpu recovery for dimgrey_cavefishTao Zhou1-0/+1
As dimgrey_cavefish driver is stable enough, set gpu recovery as default in HW hang for dimgrey_cavefish. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm: enable LCLK DSKenneth Feng1-0/+3
Enable LCLK deep sleep and it works if we enable ASPM: modprobe amdgpu aspm=1 Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: reset runpm flag if device suspend failsAlex Deucher1-1/+3
If device suspend fails when we attempt to runtime suspend, reset the runpm flag. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: use runpm flag rather than fbcon for kfd runtime suspend (v2)Alex Deucher1-2/+2
the flag used by kfd is not actually related to fbcon, it just happens to align. Use the runpm flag instead so that we can decouple it from the fbcon flag. v2: fix resume as well Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Rajneesh Bhardwaj <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: drop extra drm_kms_helper_poll_enable/disable callsAlex Deucher2-4/+0
These are already called in amdgpu_device_suspend/resume which are already called in the same functions. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/nv: add PCI reset supportAlex Deucher1-1/+6
Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/soc15: add PCI reset supportAlex Deucher1-10/+14
Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/si: add PCI reset supportAlex Deucher1-14/+23
Use generic PCI reset for GPU reset if the user specifies PCI reset as the reset mechanism. This should in general only be used for validation. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: add generic pci reset as an optionAlex Deucher3-3/+17
This allows us to use generic PCI reset mechanisms (FLR, SBR) as a reset mechanism to verify that the generic PCI reset mechanisms are working properly. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/vi: minor clean up of reset codeAlex Deucher1-22/+14
Drop duplicate reset method logging, whitespace changes. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/cik: minor clean up of reset codeAlex Deucher1-22/+11
Drop duplicate reset method logging, whitespace changes. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu/si: minor clean up of reset codeAlex Deucher1-5/+2
Drop duplicate reset method logging, whitespace changes. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm: add support for hwmon control of slow and fast PPT limit on vangoghXiaomeng Hou6-18/+204
Implement hwmon API for reading/setting slow and fast PPT limit. APU power is managed to system-level requirements through the PPT (package power tracking) feature. PPT is intended to limit power to the requirements of the power source and could be dynamically updated to maximize APU performance within the system power budget. Here FAST_PPT_LIMIT manages the ~10 ms moving average of APU power, while SLOW_PPT_LIMIT manages the configurable, thermally significant moving average of APU power (default ~5000 ms). User could read slow/fast ppt limit using command "cat power*_cap" or "sensors" in the hwmon device directory. User could adjust values of slow/fast ppt limit as needed depending on workloads through command "echo ## > power*_cap". Example: $ echo 15000000 > power1_cap $ echo 18000000 > power2_cap $ sensors amdgpu-pci-0300 Adapter: PCI adapter slowPPT: 9.04W (cap = 15.00 W) fastPPT: 9.04W (cap = 18.00 W) v2: align with existing interfaces for the getting/setting of PPT limits. Encode the upper 8 bits of limit value to distinguish slow and fast power limit type. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm: modify the power limit level parameter from bool to enum typeXiaomeng Hou3-5/+21
The original smu_get_power_limit callback accepts the power limit level parameter as bool which limits to max and current. For possible needs to retrieve other level like min, extend the parameter type using enum. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm: update the smu v11.5 smc header for vangoghXiaomeng Hou2-1/+9
Add PP messages for reading/setting Fast PPT and Slow PPT limit. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: enable wave limit on non high prio cs pipesNirmoy Das2-2/+94
To achieve the best QoS for high priority compute jobs it is required to limit waves on other compute pipes as well. This patch will set min value in non high priority mmSPI_WCL_PIPE_PERCENT_CS[0-3] registers to minimize the impact of normal/low priority compute jobs over high priority compute jobs. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: Add otg vertical interrupt0 support in DCN1.0Wayne Lin3-0/+54
[Why & How] On DCN1.0, need otg vertical line interrupt to get appropriate timing to achieve specific feature request. Add otg vertical interrupt0 support for registers which operation is vertical sensitive. Signed-off-by: Wayne Lin <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: Add otg vertical IRQ SourceWayne Lin1-0/+1
[Why & How] In order to get appropriate timing for registers which read/write is vertical line sensitive, add new IRQ source variable. This interrupt is triggered by specific vertical line, Signed-off-by: Wayne Lin <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: optimize list operation in amdgpu_xgmiKevin Wang1-6/+4
simplify the list operation. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/pm/swsmu: unify the init soft gpu metrics functionKevin Wang11-47/+45
the soft gpu metrics is not asic related data structure. unify them to reduce duplicate code. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: support rom clockgating related function for NV familyLikun Gao2-0/+40
Add functions to support enable/disable rom clock gating and get rom clock gating status. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: switch to use smuio callbacks for NV familyLikun Gao1-3/+15
Switch to smuio callbacks: use smuio v11_0_6 callbacks for Sienna_cichlid and forward ASIC, use smuio v11_0 callbacks for the other NV family ASIC. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: implement smuio v11_0_6 callbacksLikun Gao3-1/+73
Implement smuio v11_0_6 callbacks which will used by Sienna_Cichlid and forward ASIC. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: add SMUIO 11.0.6 register headersLikun Gao2-0/+76
Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amdgpu: support ASPM for some specific ASICLikun Gao3-6/+124
Support to program ASPM and LTR for Sienna Cichlid and forward ASIC. Disable ASPM for Sienna Cichlid and forward ASIC by default. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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