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2024-04-09drm/amd/swsmu: Update smu v14.0.0 headers to be 14.0.1 compatiblelima10026-43/+413
update ppsmc.h pmfw.h and driver_if.h for smu v14_0_1 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: lima1002 <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu : Increase the mes log buffer size as per new MES FW versionshaoyunl2-3/+3
From MES version 0x54, the log entry increased and require the log buffer size to be increased. The 16k is maximum size agreed Signed-off-by: shaoyunl <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu : Add mes_log_enable to control mes log featureshaoyunl4-3/+20
The MES log might slow down the performance for extra step of log the data, disable it by default and introduce a parameter can enable it when necessary Signed-off-by: shaoyunl <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/pm: fixes a random hang in S4 for SMU v13.0.4/11Tim Huang1-1/+11
While doing multiple S4 stress tests, GC/RLC/PMFW get into an invalid state resulting into hard hangs. Adding a GFX reset as workaround just before sending the MP1_UNLOAD message avoids this failure. Signed-off-by: Tim Huang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: refine function signature of amdgpu_aca_get_error_data()Yang Wang2-6/+8
refine function signature of amdgpu_aca_get_error_data(); Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amd/display: add DCN 351 version for microcode loadLi Ma1-1/+6
There is a new DCN veriosn 3.5.1 need to load Signed-off-by: Li Ma <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: Reset dGPU if suspend got abortedLijo Lazar1-0/+25
For SOC21 ASICs, there is an issue in re-enabling PM features if a suspend got aborted. In such cases, reset the device during resume phase. This is a workaround till a proper solution is finalized. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2024-04-09drm/amdgpu: add IP's FW information to devcoredumpSunil Khatri1-0/+129
Add FW information of all the IP's in the devcoredump. Signed-off-by: Sunil Khatri <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu/umsch: reinitialize write pointer in hw initLang Yu1-0/+2
Otherwise the old one will be used during GPU reset. That's not expected. Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: Refine IB schedule error loggingLijo Lazar1-2/+5
Downgrade to debug information when IBs are skipped. Also, use dev_* to identify the device. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/amdgpu: make amdgpu device attr_update() function more efficientYang Wang2-2/+43
v1: add a new enumeration type to identify device attribute node, this method is relatively more efficient compared with 'strcmp' in update_attr() function. v2: rename device_attr_type to device_attr_id. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Ma Jun <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-04-09drm/xe/xe2hpm: Add initial set of workaroundsGustavo Sousa2-0/+36
Define the initial set of workarounds for Xe2_HPM. Signed-off-by: Gustavo Sousa <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2hpg: Introduce performance tuning changes for Xe2_HPG.Shekhar Chauhan1-3/+3
Introduces performance tuning guide changes for Xe_HPG. v2: Switched to open upper bound for "Tuning: L3 Cache" setting. BSpec: 72161 Signed-off-by: Shekhar Chauhan <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2hpg: Add initial GT workaroundsHaridhar Kalvala2-2/+70
Add the initial set of Xe2_HPG gt/engine/lrc workarounds. v2: Removed WA_16020183090 which is no more applicable Extended WA_18033852989,18034896535 also to xe2hpg Signed-off-by: Haridhar Kalvala <[email protected]> Signed-off-by: Clint Taylor <[email protected]> Signed-off-by: Gustavo Sousa <[email protected]> Signed-off-by: Dnyaneshar Bhadane <[email protected]> Signed-off-by: Shekhar Chauhan <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2: Add workaround 18034896535Bommu Krishnaiah1-0/+5
Add 18034896535 as driver permanent workaround. v2: 18034896535 and 16021540221 are two independent workarounds that just happen to have the same implementation, hence keeping it. Signed-off-by: Bommu Krishnaiah <[email protected]> Reviewed-by: Tejas Upadhyay <[email protected]> Cc: Tejas Upadhyay <[email protected]> Cc: Matt Roper <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2hpg: Remove extra allocation of CCS pages for dgfxAkshata Jahagirdar1-0/+3
On Xe2 dGPU, compression is only supported with VRAM. When copying from VRAM -> system memory the KMD uses mapping with uncompressed PAT so the copy in system memory is guaranteed to be uncompressed. When restoring such buffers from system memory -> VRAM the KMD can't easily know which pages were originally compressed, so we always use uncompressed -> uncompressed here. so this means that there's no need for extra CCS storage on such platforms. v2: More description added to commit message Signed-off-by: Akshata Jahagirdar <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Himal Prasad Ghimiray <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2hpg: Determine flat ccs offset for vramHimal Prasad Ghimiray2-2/+42
on Xe2 dgfx platform determine the offset using Flat CCS size bitfield of XE2_FLAT_CCS_BASE_RANGE_[UPPER/LOWER] mcr registers. v2: function argument tile_size changed from pass by reference to pass by value Bspec: 68023 Signed-off-by: Himal Prasad Ghimiray <[email protected]> Signed-off-by: Akshata Jahagirdar <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/bmg: Program an additional discrete-specific PAT settingMatt Roper1-0/+7
Discrete Xe2 platforms require programming of one additional row of PAT settings which controls the access characteristics for PPGTT and LMTT page tables. Integrated GPUs do not need this programming and will leave the register at its hardware default value. Bspec: 71582 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Himal Prasad Ghimiray <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/bmg: Add BMG mocs tableBalasubramani Vivekanandan1-0/+1
BMG uses the same MOCS table as LNL. Bpsec: 71582 CC: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Matt Roper <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/bmg: Add BMG platform definitionMatt Roper3-0/+8
BMG is a discrete GPU based on the Xe2 architecture. No device ids are bound to the BMG platform descriptor yet. BMG device ids will be added once we have all the basic required platform enabling patches landed. v2: Removed device ids, deferring it to a later patch v3: Squash in compat header IS_BATTLEMAGE() patch. (Lucas) Bspec: 68090 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2: Recognize Xe2_HPM IPMatt Roper1-1/+2
Xe2_HPM uses the same general feature flags as Xe2_LPM. Xe2_HPM is identified as version 13.01 in the GMD_ID register. Bspec: 68090, 67163 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/xe2: Recognize Xe2_HPG IPMatt Roper1-1/+2
Xe2_HPG uses the same general feature flags as Xe2_LPG. Xe2_HPG is identified as version 20.01 in the GMD_ID register. Bspec: 68090 Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Balasubramani Vivekanandan <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/vmwgfx: Enable DMA mappings with SEVZack Rusin1-5/+6
Enable DMA mappings in vmwgfx after TTM has been fixed in commit 3bf3710e3718 ("drm/ttm: Add a generic TTM memcpy move for page-based iomem") This enables full guest-backed memory support and in particular allows usage of screen targets as the presentation mechanism. Signed-off-by: Zack Rusin <[email protected]> Reported-by: Ye Li <[email protected]> Tested-by: Ye Li <[email protected]> Fixes: 3b0d6458c705 ("drm/vmwgfx: Refuse DMA operation when SEV encryption is active") Cc: Broadcom internal kernel review list <[email protected]> Cc: [email protected] Cc: <[email protected]> # v6.6+ Reviewed-by: Martin Krastev <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/hwmon: Cast result to output precision on left shift of operandKarthik Poosa1-2/+2
Address potential overflow in result of left shift of a lower precision (u32) operand before assignment to higher precision (u64) variable. v2: - Update commit message. (Himal) Fixes: 4446fcf220ce ("drm/xe/hwmon: Expose power1_max_interval") Signed-off-by: Karthik Poosa <[email protected]> Reviewed-by: Anshuman Gupta <[email protected]> Cc: Badal Nilawar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-09drm/xe/hwmon: Update xe_hwmon_get_reg to return struct xe_regKarthik Poosa1-21/+26
Return struct xe_reg instead of reg.raw from xe_hwmon_get_reg to have abstracted usage of struct xe_reg. v2: - Use xe_reg_is_valid function instead of XE_REG_IS_VALID macro as it is removed. Signed-off-by: Karthik Poosa <[email protected]> Suggested-by: Lucas De Marchi <[email protected]> Cc: Badal Nilawar <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-09drm/xe: Define xe_reg_is_validKarthik Poosa1-0/+5
Add a function to check if struct xe_reg has valid address. v2: - Rebase. - Make xe_reg_is_valid as inline function instead of a macro. (Badal). - Update commit msg. Signed-off-by: Karthik Poosa <[email protected]> Suggested-by: Lucas De Marchi <[email protected]> Cc: Badal Nilawar <[email protected]> Reviewed-by: Badal Nilawar <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-09drm/i915: Introduce intel_crtc_joined_pipe_mask()Ville Syrjälä3-6/+13
Add a small helper to compute the set of pipes that the current crtc is using. And we have at least one trivial place in intel_ddi_update_active_dpll() where we can use it immediately, so let's do that. v2: Use the name 'pipe_crtc' for the per-pipe crtc pointer Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Arun R Murthy <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/i915: Pass connector to intel_dp_need_bigjoiner()Ville Syrjälä3-6/+10
Pass the connector explicitly to intel_dp_need_bigjoiner() so that it'll actually check the correct place for the bigjoiner force flag. Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/i915/mst: Check intel_dp_joiner_needs_dsc()Ville Syrjälä1-4/+6
intel_dp_mst_compute_config() is missing the "does the joiner need DSC?" check despite claiming to have a lot of other joiner/dsc stuff in there (albeit disabled). Replicate the logic from the SST side. TODO: refactor all this duplicated code! Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/i915: Extract intel_dp_joiner_needs_dsc()Ville Syrjälä3-18/+15
Pull the "does joiner need DSC?" check into a helper. MST will want to use this too at some point. Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/i915: s/intel_dp_can_bigjoiner()/intel_dp_has_bigjoiner()/Ville Syrjälä2-3/+3
Rename intel_dp_can_bigjoiner() to intel_dp_has_bigjoiner() to better reflect its function. Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Vandita Kulkarni <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/lnl: Enable GuC Wa_14019882105Badal Nilawar3-7/+39
Enable GuC Wa_14019882105 to block interrupts during C6 flow when the memory path has been blocked v2: Make helper function generic and name it as guc_waklv_enable_simple (John Harrison) v3: Make warning descriptive (John Harrison) v4: s/drm_WARN/xe_gt_WARN/ (Michal) Cc: John Harrison <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Reviewed-by: John Harrison <[email protected]> Signed-off-by: Michal Wajdeczko <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/xe/guc: Add support for workaround KLVsBadal Nilawar3-3/+66
To prevent running out of bits, new workaround (w/a) enable flags are being added via a KLV system instead of a 32 bit flags word. v2: GuC version check > 70.10 is not needed as base line xe doesnot support anything below < 70.19 v3: Use 64 bit ggtt address for future compatibility (John Harrison/Daniele) v4: %s/PAGE_SIZE/SZ_4K/ (Michal) Cc: John Harrison <[email protected]> Signed-off-by: Badal Nilawar <[email protected]> Reviewed-by: John Harrison <[email protected]> Signed-off-by: Michal Wajdeczko <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-09drm/i915: use check_add_overflow() and drop local variantsJani Nikula2-17/+3
Prefer common check_add_overflow() from overflow.h over the locally rolled versions of it. While check_add_overflow() does require a variable to assign to, unlike add_overflows_t(), it's still better than having multiple versions around. Cc: Kees Cook <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Jani Nikula <[email protected]>
2024-04-09drm/i915: move pipestat_irq_mask to display substructJani Nikula4-9/+8
The info is related to display, and should be placed under i915->display. Reviewed-by: Ville Syrjälä <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/2e2f1c9576126927ea63a54639077c01d44ad5b6.1712599670.git.jani.nikula@intel.com
2024-04-09drm/i915: move de_irq_mask to display substructJani Nikula4-17/+14
The info is related to display, and should be placed under i915->display. Reviewed-by: Ville Syrjälä <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/733fc96df9153c6af8979d9b23d3aa3734937b56.1712599670.git.jani.nikula@intel.com
2024-04-09drm/i915: move display_irqs_enabled to display substructJani Nikula6-15/+14
The info is related to display, and should be placed under i915->display. Reviewed-by: Ville Syrjälä <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/f6ac8e4c6ec8621bacf3db58a2bf156bd636f1d1.1712599670.git.jani.nikula@intel.com
2024-04-09drm/i915: move vblank_enabled to display substructJani Nikula4-10/+11
The info is related to display, and should be placed under i915->display. Start a new irq sub-substruct. Reviewed-by: Ville Syrjälä <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/eb89ed70020ea78396e1fec6f1a97693f2bdb96b.1712599670.git.jani.nikula@intel.com
2024-04-09drm/i915: move max_dotclk_freq to display substructJani Nikula14-20/+17
The info is related to display, and should be placed under i915->display. Reviewed-by: Ville Syrjälä <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/ea012aa72c93f3d436ccacf8f75683757d144b82.1712599670.git.jani.nikula@intel.com
2024-04-09drm/i915: move skl_preferred_vco_freq to display substructJani Nikula4-14/+10
The info is related to display, and should be placed under i915->display. Reviewed-by: Ville Syrjälä <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/4e9877d1641bce905cc9dd5eabe40df51ddbe9b5.1712599670.git.jani.nikula@intel.com
2024-04-09drm/i915/gt: drop display clock info from gt debugfsJani Nikula1-4/+0
The same info is available in i915_cdclk_info. Reviewed-by: Ville Syrjälä <[email protected]> Acked-by: Lucas De Marchi <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/50461f13ab09b162de25d3f3587890548f4db499.1712599670.git.jani.nikula@intel.com
2024-04-09nouveau: fix devinit paths to only handle display on GSP.Dave Airlie2-4/+9
This reverts: nouveau/gsp: don't check devinit disable on GSP. and applies a further fix. It turns out the open gpu driver, checks this register, but only for display. Match that behaviour and in the turing path only disable the display block. (ampere already only does displays). Fixes: 5d4e8ae6e57b ("nouveau/gsp: don't check devinit disable on GSP.") Reviewed-by: Danilo Krummrich <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-08drm/xe: Capture GuC CT snapshot when stoppedMatthew Brost1-1/+1
It is useful capture the GuC CT snapshot if the GuC CT has been forcefully put into the stopped state. Enable snapshot capture when in this state. Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-08drm/xe: Always capture exec queues on snapshotMatthew Brost3-25/+6
Always capture exec queues on snapshot regardless if exec queue has pending jobs or not. Having jobs or not does indicate whether the exec queue capture is useful. Example bugs that would not be easily detected by skipping capture when pending job list is empty: - Jobs pending on exec queue have dependencies - Leaking exec queue refs - GuC protocol issues (i.e. losing G2H) In addition to above bugs, in general it just useful to see every exec queue registered with the GuC and its state. Cc: Rodrigo Vivi <[email protected]> Signed-off-by: Matthew Brost <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2024-04-08drm/xe/uapi: Restore flags VM_BIND_FLAG_READONLY and VM_BIND_FLAG_IMMEDIATEFrancois Dugast2-2/+15
The commit 84a1ed5e6756 ("drm/xe/uapi: Remove unused flags") is partially reverted. At the time, flags not used by user space were removed during cleanup. Some flags now needed by the compute runtime are brought back in this commit: - DRM_XE_VM_BIND_FLAG_READONLY is used to write protect kernel ISA thus preventing accidental overwrites. - DRM_XE_VM_BIND_FLAG_IMMEDIATE is used to trigger mapping at the time of binding in order to prevent faulting at execution time. The changes in the compute runtime are ready and approved, see link below. v2: Include a link to the PR in the commit message (Matthew Brost) v3: Update kernel doc and improve commit message (Lucas De Marchi) Cc: Mateusz Jablonski <[email protected]> Cc: Michal Mrozek <[email protected]> Cc: Matthew Brost <[email protected]> Cc: Lucas De Marchi <[email protected]> Link: https://github.com/intel/compute-runtime/pull/717 Signed-off-by: Francois Dugast <[email protected]> Reviewed-by: Matthew Brost <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-08drm/xe: Remove dead clock codeLucas De Marchi2-6/+1
xe_gt_clock_cycles_to_ns() is not called from anywhere after PMU handling was removed in commit 90a8b23f9b85 ("drm/xe/pmu: Remove PMU from Xe till uapi is finalized"). Drop it. Reviewed-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Lucas De Marchi <[email protected]>
2024-04-08drm/i915/vrr: Disable VRR when using bigjoinerVille Syrjälä1-0/+7
All joined pipes share the same transcoder/timing generator. Currently we just do the commits per-pipe, which doesn't really work if we need to change switch between non-VRR and VRR timings generators on the fly, or even when sending the push to the transcoder. For now just disable VRR when bigjoiner is needed. Cc: [email protected] Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Vandita Kulkarni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Ville Syrjälä <[email protected]> (cherry picked from commit f9d5e51db65652dbd8a2102fd7619440e3599fd2) Signed-off-by: Rodrigo Vivi <[email protected]>
2024-04-08drm/i915: Disable live M/N updates when using bigjoinerVille Syrjälä1-1/+5
All joined pipes share the same transcoder/timing generator. Currently we just do the commits per-pipe, which doesn't really work if we need to change the timings at the same time. For now just disable live M/N updates when bigjoiner is needed. Cc: [email protected] Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Arun R Murthy <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Ville Syrjälä <[email protected]> (cherry picked from commit ef79820db723a2a7c229a7251c12859e7e25a247) Signed-off-by: Rodrigo Vivi <[email protected]>
2024-04-08drm/i915: Disable port sync when bigjoiner is usedVille Syrjälä1-0/+5
The current modeset sequence can't handle port sync and bigjoiner at the same time. Refuse port sync when bigjoiner is needed, at least until we fix the modeset sequence. v2: Add a FIXME (Vandite) Cc: [email protected] Tested-by: Vidya Srinivas <[email protected]> Reviewed-by: Vandita Kulkarni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Ville Syrjälä <[email protected]> (cherry picked from commit b37e1347b991459c38c56ec2476087854a4f720b) Signed-off-by: Rodrigo Vivi <[email protected]>
2024-04-08drm/i915/psr: Disable PSR when bigjoiner is usedVille Syrjälä1-0/+11
Bigjoiner seem to be causing all kinds of grief to the PSR code currently. I don't believe there is any hardware issue but the code simply not handling this correctly. For now just disable PSR when bigjoiner is needed. Cc: [email protected] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Arun R Murthy <[email protected]> Acked-by: Jouni Högander <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> (cherry picked from commit 372fa0c79d3f289f813d8001e0a8a96d1011826c) Signed-off-by: Rodrigo Vivi <[email protected]>
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