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2019-04-07drm/i915: Track the temporary wakerefs used for hsw_get_pipe_configChris Wilson1-13/+33
Haswell+ require many power wells to probe the current HW display state. Under the wakeref tracking scheme, we want each owner to store and release the wakeref they use, so we can identify callers that have leaked their wakeref. For hsw_get_pipe_config, this means we have to keep the array of all wakerefs as it current acquires its power wells piecemeal and releases them en masse. By tracking these wakerefs, we should be able to eliminate a lot of noise from the runtime-pm debug logs. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-06drm/i915: Mark GEM wedged right after marking device unpluggedJanusz Krzysztofik2-0/+8
As soon as a device is considered unplugged, not only prevent pending users from accessing the device structures but also cancel all their pending requests so all consumed resources can be cleaned up as soon as possible. Suggested-by: Chris Wilson <[email protected]> Signed-off-by: Janusz Krzysztofik <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-05drm/i915: Convert i915_reset.c over to using uncore mmioChris Wilson2-56/+89
Currently i915_reset.c mixes calls to intel_uncore, pci and our old style I915_READ mmio interfaces. Cast aside the old implicit macros, and harmonise on using uncore throughout. add/remove: 1/1 grow/shrink: 0/4 up/down: 65/-207 (-142) Function old new delta rmw_register - 65 +65 gen8_reset_engines 945 942 -3 g4x_do_reset 407 376 -31 intel_gpu_reset 545 509 -36 clear_register 63 - -63 i915_clear_error_registers 461 387 -74 A little bit of pointer dancing elimination works wonders. v2: Roll up the helpers into intel_uncore for general use With the helpers gcc was a little more eager to inline: add/remove: 0/1 grow/shrink: 1/3 up/down: 99/-133 (-34) Function old new delta i915_clear_error_registers 461 560 +99 gen8_reset_engines 945 942 -3 g4x_do_reset 407 376 -31 intel_gpu_reset 545 509 -36 clear_register 63 - -63 Total: Before=1544400, After=1544366, chg -0.00% Win some, lose some, gcc is gcc. Signed-off-by: Chris Wilson <[email protected]> Cc: Daniele Ceraolo Spurio <[email protected]> Cc: Paulo Zanoni <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-05drm/i915: Make use of 'engine->uncore'Chris Wilson1-15/+17
The engine has a direct link to the intel_uncore mmio handler, so make use of it rather than going indirectly via &engine->i915->uncore. v2: Update gen11_lock_sfc() to use engine->uncore as well Signed-off-by: Chris Wilson <[email protected]> Cc: Daniele Ceraolo Spurio <[email protected]> Cc: Paulo Zanoni <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-05drm/i915: Make RING_PDP relative to engine->mmio_baseChris Wilson4-22/+27
The PDP registers are an oddity inside the set of context saved registers in that they take the engine as a parameter to the macro and not the mmio_base as the others do. Make it accept the engine->mmio_base for consistency in programming the context registers. add/remove: 0/0 grow/shrink: 2/1 up/down: 3/-32 (-29) Function old new delta emit_ppgtt_update 324 326 +2 capture 5102 5103 +1 execlists_init_reg_state.isra 1128 1096 -32 And similar savings later! Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-05drm/i915/selftests: Fix plain use of integer 0 as NULLChris Wilson1-1/+1
Quelch a sparse warning: drivers/gpu/drm/i915/gt/selftest_lrc.c:119:54: warning: Using plain integer as NULL pointer Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-05drm/i915/execlists: Enable coarse preemption boundaries for gen8Chris Wilson3-15/+217
When we introduced preemption, we chose to keep it disabled for gen8 as supporting preemption inside GPGPU user batches required various w/a in userspace. Since then, the desire to preempt long queues of requests between batches (e.g. within busywaiting semaphores) has grown. So allow arbitration within the busywaits and between requests, but disable arbitration within user batches so that we can preempt between requests and not risk breaking GPGPU. However, since this preemption is much coarser and doesn't interfere with userspace, we decline to include it amongst the scheduler capabilities. (This is also required for us to skip over the preemption selftests that expect to be able to preempt user batches.) Michal suggested that we could perhaps allow preemption inside gen8 userspace batches if we can satisfy ourselves that the default preemption settings are viable with existing userspace (principally OpenCL which already should carry any known workaround). We could then merge the two code paths back into one, even dropping the artifical has-preemption device feature flag. Testcase: igt/gem_exec_scheduler/semaphore-user References: beecec901790 ("drm/i915/execlists: Preemption!") Fixes: e88619646971 ("drm/i915: Use HW semaphores for inter-engine synchronisation on gen8+") Signed-off-by: Chris Wilson <[email protected]> Cc: Michal Winiarski <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Michal Winiarski <[email protected]> #irc Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-05drm/i915: Use lockdep_pin_lock() over the construction of the requestChris Wilson2-0/+15
During request construction, we take the timeline->mutex to ensure exclusive access to the ringbuffer (for command emission) and the timeline itself (for command ordering). The timeline->mutex should not be dropped by callers until we release it in i915_request_add(). lockdep provides a pin/unpin lock facility to detect accidental unlocks inside critical sections, so put it to use for request construction. Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-05drm/sun4i: DW HDMI: Lower max. supported rate for H6Jernej Skrabec1-2/+7
Currently resolutions with pixel clock higher than 340 MHz don't work with H6 HDMI controller. They just produce a blank screen. Limit maximum pixel clock rate to 340 MHz until scrambling is supported. Cc: [email protected] # 5.0 Fixes: 40bb9d3147b2 ("drm/sun4i: Add support for H6 DW HDMI controller") Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-05Merge tag 'drm-misc-next-2019-04-04' of ↵Dave Airlie97-737/+7839
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.2: UAPI Changes: -syncobj: Add TIMELINE_WAIT|QUERY|TRANSFER|TIMELINE_SIGNAL ioctls (Chunming) -Clarify that 1.0 can be represented by drm_color_lut (Daniel) Cross-subsystem Changes: -dt-bindings: Add binding for rk3066 hdmi (Johan) -dt-bindings: Add binding for Feiyang FY07024DI26A30-D panel (Jagan) -dt-bindings: Add Rocktech vendor prefix and jh057n00900 panel bindings (Guido) -MAINTAINERS: Add lima and ASPEED entries (Joel & Qiang) Core Changes: -memory: use dma_alloc_coherent when mem encryption is active (Christian) -dma_buf: add support for a dma_fence chain (Christian) -shmem_gem: fix off-by-one bug in new shmem gem helpers (Dan) Driver Changes: -rockchip: Add support for rk3066 hdmi (Johan) -ASPEED: Add driver supporting ASPEED BMC display controller to drm (Joel) -lima: Add driver supporting Arm Mali4xx gpus to drm (Qiang) -vc4/v3d: Various cleanups and improved error handling (Eric) -panel: Add support for Feiyang FY07024DI26A30-D MIPI-DSI panel (Jagan) -panel: Add support for Rocktech jh057n00900 MIPI-DSI panel (Guido) Cc: Johan Jonker <[email protected]> Cc: Christian König <[email protected]> Cc: Chunming Zhou <[email protected]> Cc: Dan Carpenter <[email protected]> Cc: Eric Anholt <[email protected]> Cc: Qiang Yu <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Jagan Teki <[email protected]> Cc: Guido Günther <[email protected]> Cc: Joel Stanley <[email protected]> [airlied: fixed XA limit build breakage, Rodrigo also submitted the same patch, but I squashed it in the merge.] Signed-off-by: Dave Airlie <[email protected]> From: Sean Paul <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20190404201016.GA139524@art_vandelay
2019-04-05Merge tag 'drm-intel-fixes-2019-04-04' of ↵Dave Airlie5-11/+11
git://anongit.freedesktop.org/drm/drm-intel into drm-fixes Only one fix for DSC (backoff after drm_modeset_lock deadlock) and GVT's fixes including vGPU display plane size calculation, shadow mm pin count, error recovery path for workload create and one kerneldoc fix. Signed-off-by: Dave Airlie <[email protected]> From: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-05Merge branch 'drm-fixes-5.1' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie6-6/+33
into drm-fixes Fixes for 5.1: - Fix for pcie dpm - Powerplay fixes for vega20 - Fix vbios display on reboot if driver display state is retained - Gfx9 resume robustness fix Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-04drm/pl111: fix possible object reference leakWen Yang1-0/+4
The call to of_find_matching_node_and_match returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: drivers/gpu/drm/pl111/pl111_versatile.c:333:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function. drivers/gpu/drm/pl111/pl111_versatile.c:340:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function. drivers/gpu/drm/pl111/pl111_versatile.c:346:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function. drivers/gpu/drm/pl111/pl111_versatile.c:354:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function. drivers/gpu/drm/pl111/pl111_versatile.c:395:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function. drivers/gpu/drm/pl111/pl111_versatile.c:402:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 317, but without a corresponding object release within this function. Signed-off-by: Wen Yang <[email protected]> Cc: Eric Anholt <[email protected]> (supporter:DRM DRIVER FOR ARM PL111 CLCD) Cc: David Airlie <[email protected]> (maintainer:DRM DRIVERS) Cc: Daniel Vetter <[email protected]> (maintainer:DRM DRIVERS) Cc: [email protected] (open list:DRM DRIVERS) Cc: [email protected] (open list) Signed-off-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-04drm/vc4: vc4_debugfs_regset32() can be statickbuild test robot1-1/+1
Fixes: c9be804c8c7a ("drm/vc4: Use common helpers for debugfs setup by the driver components.") Signed-off-by: kbuild test robot <[email protected]> Signed-off-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20190403213629.GA31570@lkp-ib03
2019-04-04drm/panel: Rocktech jh057n00900: Add terminating newlines to loggingJoe Perches1-9/+10
These were missing '\n' terminations, add them. Signed-off-by: Joe Perches <[email protected]> Reviewed-by: Guido Günther <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-04drm/i915: add Makefile magic for testing headers are self-containedJani Nikula11-68/+28
The below commits added dummy files to test that certain headers are self-contained, i.e. compilable as standalone units: 39e2f501c1b4 ("drm/i915: Split struct intel_context definition to its own header") 3a891a626794 ("drm/i915: Move intel_engine_mask_t around for use by i915_request_types.h") 8b74594aa455 ("drm/i915: Split out i915_priolist_types into its own header") The idea is fine, but the implementation is a bit tedious and inflexible, and does not really scale well. Implement the same in make using autogenerated dummy sources to include the headers. v2 by Chris: - Use patsubst - Add .gitignore - Add clean-files for generated dummy sources v3 by Jani: - Fix make clean - Add the tests to i915-y instead of extra-y v4 by Jani: - quiet_cmd whitespace fix Cc: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-04drm/amd/powerplay: check for invalid profile mode before switchingEvan Quan1-3/+2
Need to check for invalid profile mode settings before determining to switch to that. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-04drm/amd/display: fix cursor black issuetiancyin1-0/+1
[Why] the member sdr_white_level of struct dc_cursor_attributes was not initialized, then the random value result that dcn10_set_cursor_sdr_white_level() set error hw_scale value 0x20D9(normal value is 0x3c00), this cause the black cursor issue. [how] just initilize the obj of struct dc_cursor_attributes to zero to avoid the random value. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Tianci Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-04drm/amdgpu: amdgpu_device_recover_vram always failed if only one node in ↵wentalou1-4/+9
shadow_list amdgpu_bo_restore_shadow would assign zero to r if succeeded. r would remain zero if there is only one node in shadow_list. current code would always return failure when r <= 0. restart the timeout for each wait was a rather problematic bug as well. The value of tmo SHOULD be changed, otherwise we wait tmo jiffies on each loop. Signed-off-by: Wentao Lou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-04drm/amdgpu: Adjust IB test timeout for XGMI configurationshaoyunl1-0/+3
On XGMI configuration the ib test may take longer to finish Signed-off-by: shaoyunl <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-04drm/i915: Fixup kerneldoc for intel_cdclk_needs_cd2x_updateChris Wilson1-0/+1
drivers/gpu/drm/i915/intel_cdclk.c:2116: warning: Function parameter or member 'dev_priv' not described in 'intel_cdclk_needs_cd2x_update' Signed-off-by: Chris Wilson <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Abhay Kumar <[email protected]> Cc: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-04drm/i915: Be precise in types for i915_gem_busyChris Wilson1-9/+10
Mixing u8 and -1u together leads to zero-extended integer expansion, and comparing 0x000000ff against 0xffffffff, causing us to report a mixed uabi-class request as not busy. The input flag is a u8, and we want to generate a u32 uABI response, mark our functions so. Fixes: c8b502422bfe ("drm/i915: Remove last traces of exec-id (GEM_BUSY)") Testcase: igt/gem_exec_balance/busy Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-04drm/amdkfd: Add picasso pci idAlex Deucher1-0/+1
Picasso is a new raven variant. Reviewed-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-04drm/i915: Update DRIVER_DATE to 20190404Joonas Lahtinen1-2/+2
Signed-off-by: Joonas Lahtinen <[email protected]>
2019-04-04drm: Add ASPEED GFX driverJoel Stanley8-0/+676
This driver is for the ASPEED BMC SoC's GFX display hardware. This driver runs on the ARM based BMC systems, unlike the ast driver which runs on a host CPU and is is for a PCI graphics device. Signed-off-by: Joel Stanley <[email protected]> Acked-by: Daniel Vetter <[email protected]> Reviewed-by: Noralf Trønnes <[email protected]> Reviewed-by: Sam Ravnborg <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-03Merge tag 'gvt-fixes-2019-04-04' of https://github.com/intel/gvt-linux into ↵Rodrigo Vivi4-10/+7
drm-intel-fixes gvt-fixes-2019-04-04 - Fix shadow mm pin count (Yan) - Fix cmd parser error path recover (Yan) - Fix vGPU display plane size calculation (Xiong) - Fix kerneldoc (Chris) Signed-off-by: Rodrigo Vivi <[email protected]> From: Zhenyu Wang <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-04drm/i915/gvt: Fix kerneldoc typo for intel_vgpu_emulate_hotplugChris Wilson1-1/+1
drivers/gpu/drm/i915/gvt/display.c:457: warning: Function parameter or member 'connected' not described in 'intel_vgpu_emulate_hotplug' drivers/gpu/drm/i915/gvt/display.c:457: warning: Excess function parameter 'conncted' description in 'intel_vgpu_emulate_hotplug' Fixes: 1ca20f33df42 ("drm/i915/gvt: add hotplug emulation") Signed-off-by: Chris Wilson <[email protected]> Cc: Hang Yuan <[email protected]> Cc: Zhenyu Wang <[email protected]> Cc: Zhi Wang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2019-04-04drm/i915/gvt: Correct the calculation of plane sizeXiong Zhang1-6/+2
stride isn't in unit of pixel, it is bytes, so calculation of plane size doesn't need to multiple bpp. Fixes: e546e281d33d ("drm/i915/gvt: Dmabuf support for GVT-g") Signed-off-by: Xiong Zhang <[email protected]> Signed-off-by: Zhenyu Wang <[email protected]>
2019-04-03drm/vc4: Disable V3D interactions if the v3d component didn't probe.Eric Anholt7-1/+50
One might want to use the VC4 display stack without using Mesa. Similar to the debugfs fixes for not having all of the possible display bits enabled, make sure you can't oops in vc4 if v3d isn't enabled. v2: Fix matching against other v3d variants (review by Paul), don't forget to set irq_enabled so that the vblank uapi works v3: Use -ENODEV instead of -EINVAL on Paul's suggestion. Signed-off-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Paul Kocialkowski <[email protected]>
2019-04-03drm/vc4: Use common helpers for debugfs setup by the driver components.Eric Anholt12-165/+125
The global list of all debugfs entries for the driver was painful: the list couldn't see into the components' structs, so each component had its own debugs show function to find the component, then find the regset and dump it. The components also had to be careful to check that they were actually registered in vc4 before dereferencing themselves, in case they weren't probed on a particular platform. They routinely failed at that. Instead, we can have the components add their debugfs callbacks to a little list in vc4 to be registered at drm_dev_register() time, which gets vc4_debugfs.c out of the business of knowing the whole list of components. Thanks to this change, dsi0 (if it existed) would register its node. v2: Rebase on hvs_underrun addition. v3: whitespace fixup Signed-off-by: Eric Anholt <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Paul Kocialkowski <[email protected]>
2019-04-03drm/i915: Expose full 1024 LUT entries on ivb+Ville Syrjälä2-43/+34
On ivb+ we can select between the regular 10bit LUT mode with 1024 entries, and the split mode where the LUT is split into seprate degamma and gamma halves (each with 512 entries). Currently we expose the split gamma size of 512 as the GAMMA/DEGAMMA_LUT_SIZE. When using only degamma or gamma (not both) we are wasting half of the hardware LUT entries. Let's flip that around so that we expose the full 1024 entries and just throw away half of the user provided entries when using the split gamma mode. Cc: Matt Roper <[email protected]> Suggested-by: Matt Roper <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]>
2019-04-03drm/i915: Expose the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props on gen2/3Ville Syrjälä1-0/+5
Just so we don't leave gen2/3 out in the cold let's advertize the legacy LUT via the GAMMA_LUT/GAMMA_LUT_SIZE props. Without the GAMMA_LUT prop we can't actually load a LUT using the atomic ioctl (in preparation for the day of 100% atomic driver). Supposedly some gen2/3 platforms have an interpolated 10bit gamma mode as well. It's slightly funkier than the i965+ mode since you have to specify the slope for the interpolation by hand. But when I tried it I couldn't get it to work, the hardware just insisted on using the 8bit more regardless of the state of the relevant PIPECONF bit. Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]>
2019-04-03drm/i915: Add "10.6" LUT mode for i965+Ville Syrjälä3-1/+71
i965+ have an interpolate 10bit LUT mode. Let's expose that so that we can actually enjoy real 10bpc. v2: Don't use I915_WRITE_FW() yet Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]>
2019-04-03drm/i915: Add 10bit LUT for ilk/snbVille Syrjälä3-10/+52
Plop in support for 10bit LUT on ilk/snb. There is no split gamma mode on these platforms, so we have to choose between degamma and gamma. That could be a runtime choice but for now let's just advertize the gamma as having 1024 entries. We'll also keep the ctm hidden for now. v2: Don't use I915_WRITE_FW() yet Introduce bool has_ctm (Maarten) Call drm_crtc_enable_color_mgmt() uncoditionally (Maarten) Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]>
2019-04-03drm/i915: Implement split/10bit gamma for ivb/hswVille Syrjälä2-24/+95
Reuse the bdw+ code to get split/10bit gamma for ivb/hsw. The hardware is nearly identical. The only slight snag is that on ivb/hsw the precision palette auto increment mode does not work. So we must increment the index manually. We'll probably want to stick to the auto increment mode on bdw+ in the name of efficiency. Also we want to avoid using the CSC for limited range RGB output as PIPECONF will take care of that on IVB. v2: Rebase due to EXT_GC_MAX/EXT2_GC_MAX changes Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]>
2019-04-03drm/i915: Don't use split gamma when we don't have toVille Syrjälä2-95/+92
Using the split gamma mode when we don't have to has the annoying requirement of loading a linear LUT to the unused half. Instead let's make life simpler by switching to the 10bit gamma mode and duplicating each entry. This also allows us to load the software gamma LUT into the hardware degamma LUT, thus removing some of the buggy configurations we currently allow (YCbCr/limited range RGB + gamma LUT). We do still have other configurations that are also buggy, but those will need more complicated fixes or they just need to be rejected. Sadly GLK doesn't have this flexibility anymore and the degamma and gamma LUTs are very different so no help there. v2: Apply a mask when checking gamma_mode on icl since it contains more bits than just the gamma mode v3: Rebase due to EXT_GC_MAX/EXT2_GC_MAX changes v4: s/advertize/advertise/ (Uma) Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]>
2019-04-03drm/i915: Extract ilk_lut_10()Ville Syrjälä1-16/+11
Extract a helper to calculate the ILK+ 10bit gamma LUT entry. It's already duplicated twice, and soon we'll have more. v2: s/it/bit/ (Matt) Reviewed-by: Matt Roper <[email protected]> Reviewed-by: Maarten Lankhorst <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Uma Shankar <[email protected]>
2019-04-03drm/amd/display: Prevent cursor hotspot overflow for RV overlay planesNicholas Kazlauskas1-3/+9
[Why] The actual position for the cursor on the screen is essentially: x_out = x - x_plane - x_hotspot y_out = y - y_plane - y_hotspot The register values for cursor position and cursor hotspot need to be greater than zero when programmed, but we also need to subtract off the plane position to display the cursor at the correct position. Since we don't want x or y to be less than zero, we add the plane position as a positive value to x_hotspot or y_hotspot. However, what this doesn't take into account is that the hotspot registers are limited by the maximum cursor size. On DCN10 the cursor hotspot regitsers are masked to 0xFF, so they have a maximum value of 0-255. Values greater this will wrap, causing the cursor to display in the wrong position. In practice this means that for sufficiently large plane positions, the cursor will be drawn twice on the screen, and can cause screen flashes or p-state WARNS depending on what the wrapped value is. So we need a way to remove the value from x_plane and y_plane without exceeding the maximum cursor size. [How] Subtract as much as x_plane/y_plane as possible from x and y and place the remainder in the cursor hotspot register. The value for x_hotspot and y_hotspot can still wrap around but it won't happen in a case where the cursor is actually enabled. The cursor plane needs to intersect at least one pixel of the plane's rectangle to be enabled, so the cursor position + hotspot provided by userspace must always be strictly less than the maximum cursor size for the cursor to actually be enabled. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Sun peng Li <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-03drm/amd/display: Fix "dc has no member named dml" compile errorLeo Li1-0/+2
For DCN disabled builds, dc->dml is stripped out. Therefore, guard usage in dc_create_state() with CONFIG_DRM_AMD_DC_DCN1_0. It fixes the following error: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c: In function 'dc_create_state': >> drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:1237:34: error: 'struct dc' has no member named 'dml' memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib)); ^~ Signed-off-by: Leo Li <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-03drm/amd/display: Fix multi-thread writing to 1 stateAidan Wood15-203/+252
[Why] Multiple threads were writing back to one global VBA in DC resulting in multiple threads overwriting eachother's data [How] Add an instance of DML (which contains VBA) to each context and change all calls that used dc->dml to use context->dml. Created a seperate copy constructor for linux in a case where there is no access to DC. Signed-off-by: Aidan Wood <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-03drm/panel: otm8009a: Set clock to 29.70 MhzYannick Fertré1-7/+7
The panel does not support clock frequency over 30.74 MHz. The clock rate has been reduced to 29.70 MHz & new timings have been computed to get a framerate of 50 fps. Signed-off-by: Yannick Fertré <[email protected]> Reviewed-by: Philippe Cornu <[email protected]> Tested-by: Philippe Cornu <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-03drm/panel: rm68200: No error msg if probe deferredYannick Fertré1-1/+2
Do not print an error message if the regulator framework returns EPROBE_DEFER. Signed-off-by: Yannick Fertré <[email protected]> Reviewed-by: Philippe Cornu <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-03drm/panel: otm8009a: No error msg if probe deferredYannick Fertré1-1/+2
Do not print an error message if the regulator framework returns EPROBE_DEFER. Signed-off-by: Yannick Fertré <[email protected]> Reviewed-by: Philippe Cornu <[email protected]> Tested-by: Philippe Cornu <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-03drm/panel: otm8009a: Add delay at the end of initializationYannick Fertré1-0/+3
At the end of initialization, a delay is required by the panel. Without this delay, the panel could received a frame early & generate a crash of panel (black screen). Signed-off-by: Yannick Fertré <[email protected]> Reviewed-by: Philippe Cornu <[email protected]> Tested-by: Philippe Cornu <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-03drm/panel: Add Rocktech jh057n00900 panel driverGuido Günther3-0/+400
Support Rocktech jh057n00900 5.5" 720x1440 TFT LCD panel. It is a MIPI DSI video mode panel. The panel seems to use a Sitronix ST7703 look alike (most of the commands look similar to the ST7703's data sheet but use a different number of parameters). The initial version of the DSI init sequence (including sleeps) were provided by the vendor. Sleeps were reduced considerably though to speed up initialization. Signed-off-by: Guido Günther <[email protected]> Reviewed-by: Sam Ravnborg <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/1a9ce687be283c66dfb26d1dfb52a7bf695090fa.1554114302.git.agx@sigxcpu.org
2019-04-03drm/panel: Add Feiyang FY07024DI26A30-D MIPI-DSI LCD panelJagan Teki3-0/+282
Feiyang FY07024DI26A30-D is 1024x600, 4-lane MIPI-DSI LCD panel. Add panel driver for it. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Sam Ravnborg <[email protected]> Tested-by: Bhushan Shah <[email protected]> Tested-by: Merlijn Wajer <[email protected]> Signed-off-by: Thierry Reding <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-03drm/i915: Skip modeset for cdclk changes if possibleVille Syrjälä4-34/+163
If we have only a single active pipe and the cdclk change only requires the cd2x divider to be updated bxt+ can do the update with forcing a full modeset on the pipe. Try to hook that up. v2: - Wait for vblank after an optimized CDCLK change. - Avoid optimization if the pipe needs a modeset (or was disabled). - Split CDCLK change to a pre/post plane update step. v3: - Use correct version of CDCLK state as old state. (Ville) - Remove unused intel_cdclk_can_skip_modeset() v4: - For consistency call intel_set_cdclk_post_plane_update() only during modesets (and not fastsets). v5: - Remove the logic to update the CD2X divider on-the-fly on ICL, since only a divider of 1 is supported there. Clint also noticed that the pipe select bits in CDCLK_CTL are oddly defined on ICL, it's not clear yet whether that's only an error in the specification. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Abhay Kumar <[email protected]> Tested-by: Abhay Kumar <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-03drm/i915: Remove redundant store of logical CDCLK stateImre Deak1-2/+0
We copied the original state into the atomic state already earlier in the function, so no need to do it a second time. Cc: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-03drm/i915: Save the old CDCLK atomic stateImre Deak3-2/+23
The old state will be needed by an upcoming patch to determine if the commit increases or decreases CDCLK, so move the old state to the atomic state (while keeping the new one in dev_priv). cdclk.logical and cdclk.actual in the atomic state isn't used atm anywhere after the atomic check phase, so this should be safe. v2: - Use swap() instead of opencoding it. (Ville) Suggested-by: Ville Syrjälä <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-03drm/i915: Force 2*96 MHz cdclk on glk/cnl when audio power is enabledVille Syrjälä5-23/+86
CDCLK has to be at least twice the BLCK regardless of audio. Audio driver has to probe using this hook and increase the clock even in absence of any display. v2: Use atomic refcount for get_power, put_power so that we can call each once(Abhay). v3: Reset power well 2 to avoid any transaction on iDisp link during cdclk change(Abhay). v4: Remove Power well 2 reset workaround(Ville). v5: Remove unwanted Power well 2 register defined in v4(Abhay). v6: - Use a dedicated flag instead of state->modeset for min CDCLK changes - Make get/put audio power domain symmetric - Rebased on top of intel_wakeref tracking changes. Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Abhay Kumar <[email protected]> Tested-by: Abhay Kumar <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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