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2019-04-10drm/amdgpu: sdma use amdgpu_ras_feature_enable_on_bootxinhui pan1-2/+2
handle ras enable on boot. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-10drm/amdgpu: gmc use amdgpu_ras_feature_enable_on_bootxinhui pan1-2/+2
handle ras enable on boot. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-10drm/amdgpu: gfx use amdgpu_ras_feature_enable_on_bootxinhui pan1-2/+2
handle ras enable on boot. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-10drm/amdgpu: Introduce another ras enable functionxinhui pan2-0/+30
Many parts of the whole SW stack can program the ras enablement state during the boot. Now we handle that case by adding one function which check the ras flags and choose different code path. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: xinhui pan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-10drm/amdgpu: Make default ras error type to nonexinhui pan1-9/+15
Unless IP has implemented its own ras, use ERROR_NONE as the default type. Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-10drm/amd/powerplay: simplify the code of [get|set]_activity_monitor_coeffKevin Wang2-74/+7
use smu_update_table_with_arg to replace old code logic Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-10drm/amd/powerplay: optimization function of smu_update_tableKevin Wang2-3/+9
in fact, the firmware need 2 parameter: 1.table_id, 2.XferArg so change the function interface to match the firmware code Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-10drm/i915/dp: Expose force_dsc_enable through debugfsManasi Navare1-0/+2
Currently we use force_dsc_enable to force DSC from IGT, but we dont expose this value to userspace through debugfs. This patch exposes this through the same dsc_fec_support debugfs node per connector so that we can restore its value back after the tests are completed. Suggested-by: Imre Deak <[email protected]> Cc: Imre Deak <[email protected]> Cc: Lyude Paul <[email protected]> Cc: Anusha Srivatsa <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Imre Deak <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-10drm/i915/dp: revert back to max link rate and lane count on eDPJani Nikula1-59/+10
Commit 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow") started to optize the eDP 1.4+ link config, both per spec and as preparation for display stream compression support. Sadly, we again face panels that flat out fail with parameters they claim to support. Revert, and go back to the drawing board. v2: Actually revert to max params instead of just wide-and-slow. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959 Fixes: 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow") Cc: Ville Syrjälä <[email protected]> Cc: Manasi Navare <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Matt Atwood <[email protected]> Cc: "Lee, Shawn C" <[email protected]> Cc: Dave Airlie <[email protected]> Cc: [email protected] Cc: <[email protected]> # v5.0+ Reviewed-by: Rodrigo Vivi <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Tested-by: Albert Astals Cid <[email protected]> # v5.0 backport Tested-by: Emanuele Panigati <[email protected]> # v5.0 backport Tested-by: Matteo Iervasi <[email protected]> # v5.0 backport Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit f11cb1c19ad0563b3c1ea5eb16a6bac0e401f428) Signed-off-by: Rodrigo Vivi <[email protected]>
2019-04-10drm/i915/icl: Fix port disable sequence for mipi-dsiVandita Kulkarni2-4/+4
Re-enable clock gating of DDI clocks. v2: Fix the default ddi clk state for mipi-dsi (Imre) Fixes: 1026bea00381 ("drm/i915/icl: Ungate DSI clocks") Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 942d1cf48eae3fcd7e973cfb708d5c4860f0c713) Signed-off-by: Rodrigo Vivi <[email protected]>
2019-04-10drm/i915/icl: Ungate ddi clocks before IO enableVandita Kulkarni1-0/+6
IO enable sequencing needs ddi clocks enabled. These clocks will be gated at a later point in the enable sequence. v2: Fix the commit header (Uma) v3: Remove the redundant read (Ville) Fixes: 949fc52af19e ("drm/i915/icl: add pll mapping for DSI") Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit c5b81a325263a891d5811aabe938c87e03db4c37) Signed-off-by: Rodrigo Vivi <[email protected]>
2019-04-10drm/i915/icl: Don't warn on spurious interruptsMika Kuoppala1-7/+1
There is a chance we can see spurious interrupts in live now. We have more engines enabled and that with more elaborate access patterns with pm and display, increases the chances hardware just makes a social call, without anything to work on. Remove the error as we have tests to actually probe if we really miss interrupt, instead of getting spurious ones. Note that now we do write to intr_dw even with a zero value. This is considered advantegous as the write is an ack that sw is done. Cc: Chris Wilson <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-10drm/i915/icl: Handle rps interrupts without irq lockMika Kuoppala1-1/+20
Unlike previous gens, we already hold the irq_lock on entering the rps handler so we can't use it as it is. Make a gen11 specific rps interrupt handler without locking. v2: return early (Chris) Cc: Chris Wilson <[email protected]> Signed-off-by: Mika Kuoppala <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-10drm/nouveau/nvkm: mark expected switch fall-throughsGustavo A. R. Silva10-0/+28
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. This patch aims to suppress 29 missing-break-in-switch false positives. Addresses-Coverity-ID: 1456891 ("Missing break in switch") Addresses-Coverity-ID: 1324063 ("Missing break in switch") Addresses-Coverity-ID: 1324063 ("Missing break in switch") Addresses-Coverity-ID: 141432 ("Missing break in switch") Addresses-Coverity-ID: 141433 ("Missing break in switch") Addresses-Coverity-ID: 141434 ("Missing break in switch") Addresses-Coverity-ID: 141435 ("Missing break in switch") Addresses-Coverity-ID: 141436 ("Missing break in switch") Reviewed-by: Kees Cook <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]>
2019-04-10drm/i915/dp: revert back to max link rate and lane count on eDPJani Nikula1-59/+10
Commit 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow") started to optize the eDP 1.4+ link config, both per spec and as preparation for display stream compression support. Sadly, we again face panels that flat out fail with parameters they claim to support. Revert, and go back to the drawing board. v2: Actually revert to max params instead of just wide-and-slow. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109959 Fixes: 7769db588384 ("drm/i915/dp: optimize eDP 1.4+ link config fast and narrow") Cc: Ville Syrjälä <[email protected]> Cc: Manasi Navare <[email protected]> Cc: Rodrigo Vivi <[email protected]> Cc: Matt Atwood <[email protected]> Cc: "Lee, Shawn C" <[email protected]> Cc: Dave Airlie <[email protected]> Cc: [email protected] Cc: <[email protected]> # v5.0+ Reviewed-by: Rodrigo Vivi <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Tested-by: Albert Astals Cid <[email protected]> # v5.0 backport Tested-by: Emanuele Panigati <[email protected]> # v5.0 backport Tested-by: Matteo Iervasi <[email protected]> # v5.0 backport Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-10drm/i915/icl: Fix port disable sequence for mipi-dsiVandita Kulkarni2-4/+4
Re-enable clock gating of DDI clocks. v2: Fix the default ddi clk state for mipi-dsi (Imre) Fixes: 1026bea00381 ("drm/i915/icl: Ungate DSI clocks") Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-10drm/i915/icl: Ungate ddi clocks before IO enableVandita Kulkarni1-0/+6
IO enable sequencing needs ddi clocks enabled. These clocks will be gated at a later point in the enable sequence. v2: Fix the commit header (Uma) v3: Remove the redundant read (Ville) Fixes: 949fc52af19e ("drm/i915/icl: add pll mapping for DSI") Signed-off-by: Vandita Kulkarni <[email protected]> Reviewed-by: Uma Shankar <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/lima: include used header file explicitlyQiang Yu1-0/+1
To prevent build fail on some platform which does not have it in the include file chain. Reviewed-by: Neil Armstrong <[email protected]> Suggested-by: Randy Dunlap <[email protected]> Fixes: a1d2a6339961 ("drm/lima: driver for ARM Mali4xx GPUs") Signed-off-by: Qiang Yu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/lima: add missing Kconfig dependencyQiang Yu1-0/+3
Current implementation does not support MMU-less plarforms. Suggested-by: Randy Dunlap <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Fixes: a1d2a6339961 ("drm/lima: driver for ARM Mali4xx GPUs") Signed-off-by: Qiang Yu <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/mediatek: no change parent rate in round_rate() for MT2701 hdmi phyWangyan Wang4-16/+20
This is the third step to make MT2701 HDMI stable. We should not change the rate of parent for hdmi phy when doing round_rate for this clock. The parent clock of hdmi phy must be the same as it. We change it when doing set_rate only. Signed-off-by: Wangyan Wang <[email protected]> Signed-off-by: CK Hu <[email protected]>
2019-04-09drm/mediatek: using new factor for tvdpll for MT2701 hdmi phyWangyan Wang1-5/+3
This is the second step to make MT2701 HDMI stable. The factor depends on the divider of DPI in MT2701, therefore, we should fix this factor to the right and new one. Test: search ok Signed-off-by: Wangyan Wang <[email protected]> Signed-off-by: CK Hu <[email protected]>
2019-04-09drm/mediatek: remove flag CLK_SET_RATE_PARENT for MT2701 hdmi phyWangyan Wang4-8/+8
This is the first step to make MT2701 hdmi stable. The parent rate of hdmi phy had set by DPI driver. We should not set or change the parent rate of MT2701 hdmi phy, as a result we should remove the flags of "CLK_SET_RATE_PARENT" from the clock of MT2701 hdmi phy. Signed-off-by: Wangyan Wang <[email protected]> Signed-off-by: CK Hu <[email protected]>
2019-04-09drm/mediatek: make implementation of recalc_rate() for MT2701 hdmi phyWangyan Wang4-14/+42
Recalculate the rate of this clock, by querying hardware to make implementation of recalc_rate() to match the definition. Signed-off-by: Wangyan Wang <[email protected]> Signed-off-by: CK Hu <[email protected]>
2019-04-09drm/meson: Add G12A support for the DW-HDMI GlueNeil Armstrong2-38/+157
The Amlogic G12A embeds the same Synopsys DW-HDMI Controller, but with : - a "backport" of the HDR signaling registers from more recent DW-HDMI controllers, this will need a tweak since it's not normally present on this version of the DW-HDMI controller - A direct mapping of TOP and DW-HDMI registers instead of an internal bus accessed using read/write registers - Support for RX-SENSE, but not yet implemented - Support for HDMI 2.1 Dynamic HDR, but not yet implemented - Different registers mapping for the HDMI PHY setup This patchs adds support for these changes while providing exact same support as the previous GXBB, GXL & GXM SoCs. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/meson: Add G12A compatibleNeil Armstrong1-0/+1
Finally add the Amlogic G12A SoC compatible for the VPU driver. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/meson: Add G12A Video Clock setupNeil Armstrong1-11/+108
While switching to the Common Clock Framework is still Work In Progress, this patch adds the corresponding G12A HDMI PLL setup to be on-par with the other SoCs support. The G12A has only a single tweak about the high frequency setup, where the HDMI PLL needs a specific setup to handle correctly the 5.94GHz DCO frequency. Apart that, it handls ecorrectly all the other HDMI frequencies and can achieve even better DMT clock frequency precision with the larger fractional dividier width. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/meson: Add G12A support for CVBS EncoderNeil Armstrong2-9/+27
The Meson G12A SoCs uses the exact same CVBS encoder except a simple CVBS DAC register offset and settings delta. Signed-off-by: Neil Armstrong <[email protected]> [narmstrong: fixed subject typo] Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/meson: Add G12A support for plane handling in CRTC driverNeil Armstrong2-52/+221
This patch adds support for the new OSD+VD Plane blending module in the CRTC code by adding the G12A code to manage the blending module and setting the right OSD1 & VD1 plane registers. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/meson: Add G12A Support for the Overlay video planeNeil Armstrong1-2/+8
Amlogic G12A SoC supports the same set of Video Planes, but now are handled by the new OSD plane blender module. This patch uses the same VD1 plane for G12A, using the exact same scaler and VD1 setup registers, except using the new blender register to disable the plane. Signed-off-by: Neil Armstrong <[email protected]> [narmstrong: fix typo in commit log] Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/meson: Add G12A support for OSD1 PlaneNeil Armstrong1-2/+13
Amlogic G12A SoC supports now up to 3 OSD planes (1 more than the previous SoCs) and a brand new OSD plane blender module. This patch uses the same OSD1 plane for G12A, using the exact same scaler and OSD1 setup registers, except using the new blender register to disable the plane. Signed-off-by: Neil Armstrong <[email protected]> [narmstrong: fixed typo in commit log] Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/meson: Add G12A Support for VIU setupNeil Armstrong1-5/+67
Amlogic G12A SoC needs a different VIU setup code, handle it. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/meson: Add G12A Support for VPP setupNeil Armstrong1-22/+29
Amlogic G12A needs a different VPP setup code, handle it here. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/meson: Add registers for G12A SoCNeil Armstrong1-0/+247
This patch adds the new VPU registers added since the Amlogic GXM SoCs. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/meson: Switch PLL to 5.94GHz base for 297Mhz pixel clockNeil Armstrong1-2/+2
On Amlogic G12A SoC, the 2,97GHz PLL frequency is not stable enough to provide a correct 297MHz pixel clock, so switch the PLL base frequency with a /2 OD when the 297MHz pixel clock is requested. This solves the issue on G12A and also works fine on GXBB, GXL & GXM. Signed-off-by: Neil Armstrong <[email protected]> Tested-by: Jerome Brunet <[email protected]> Reviewed-by: Jerome Brunet <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/mediatek: fix the rate and divder of hdmi phy for MT2701Wangyan Wang1-2/+2
Due to a clerical error,there is one zero less for 12800000. Fix it for 128000000 Fixes: 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623") Signed-off-by: Wangyan Wang <[email protected]> Signed-off-by: CK Hu <[email protected]>
2019-04-09drm/i915/guc: Replace preempt_client lookup with engine->preempt_contextChris Wilson1-1/+1
Circumvent the dance we currently perform to find the preempt_client and lookup its HW context for this engine, as we know we have already pinned the preempt_context on the engine. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-09drm/mediatek: fix possible object reference leakWen Yang1-0/+1
The call to of_parse_phandle returns a node pointer with refcount incremented thus it must be explicitly decremented after the last usage. Detected by coccinelle with the following warnings: drivers/gpu/drm/mediatek/mtk_hdmi.c:1521:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1509, but without a corresponding object release within this function. drivers/gpu/drm/mediatek/mtk_hdmi.c:1524:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1509, but without a corresponding object release within this function. Signed-off-by: Wen Yang <[email protected]> Cc: CK Hu <[email protected]> Cc: Philipp Zabel <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Matthias Brugger <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: CK Hu <[email protected]>
2019-04-08drm/i915: Get power refs in encoder->get_power_domains()Imre Deak4-38/+35
Push getting the reference for the encoders' power domains into the encoder get_power_domains() hook instead of doing this from the caller. This way the encoder can store away the corresponding wakerefs. This fixes the DSI encoder disabling, which didn't release these power references it acquired during HW state readout. Note that longtime ownership for the corresponding wakerefs can be thus acquired / released in two ways. Nevertheless there is always only one owner for them: After HW readout (booting/system resume): - encoder->get_power_domains() acquires - encoder->disable*() releases After a modeset (calling intel_atomic_commit()): - encoder->enable*() acquires - encoder->disable*() releases * can be any of the encoder enable/disable hooks. v2: - Check that the DSI io_wakerefs are unset both during encoder HW readout and enabling. (Chris) Fixes: 0e6e0be4c9523 ("drm/i915: Markup paired operations on display power domains") Cc: Vandita Kulkarni <[email protected]> Cc: Chris Wilson <[email protected]> Signed-off-by: Imre Deak <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] (cherry picked from commit 3a52fb7e7953f0b13df8c05d0d74b56a66888f30) Signed-off-by: Rodrigo Vivi <[email protected]>
2019-04-08drm/i915/selftests: Mark live_forcewake_ops as unreliableChris Wilson1-0/+11
A couple of machines in the farm show quite frequent errors in the powerwells not being released. Either there is an external agent interferring with the powerwells, or the powerwell doesn't quite behave as we anticipate -- either way, the test is not reliable enough to be enabled by default in CI. It has served its immediate purpose in providing coverage as we made tweaks to forcewake, so keep it available for future testing. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110210 Signed-off-by: Chris Wilson <[email protected]> Cc: Daniele Ceraolo Spurio <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Daniele Ceraolo Spurio <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-08drm/i915/psr: Do not enable PSR in interlaced mode for all GENsJosé Roberto de Souza1-3/+2
This interlaced mode restriction applies to all gens, not only to Haswell. Also while at it updating the debug message to. Cc: Dhinakaran Pandiyan <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Reviewed-by: Dhinakaran Pandiyan <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-08drm/i915/psr: Initialize PSR mutex even when sink is not reliableJosé Roberto de Souza1-1/+0
Even when driver is reloaded and hits this scenario the PSR mutex should be initialized, otherwise reading PSR debugfs status will execute mutex_lock() over a mutex that was not initialized. Cc: Dhinakaran Pandiyan <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-08drm/i915: Remove unused VLV/CHV PSR registersJosé Roberto de Souza1-36/+0
PSR support for VLV and CHV was dropped in commit ce3508fd2a77 ("drm/i915/psr: Nuke PSR support for VLV and CHV") so no need to keep this registers around. Cc: Dhinakaran Pandiyan <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-08drm/i915/psr: Update PSR2 SU corruption workaround commentJosé Roberto de Souza1-4/+2
Turn out it is not a DMC bug it is actually a HW one, so this workaround will be needed for current gens, lets update the comment and remove the FIXME. BSpec: 7723 Cc: Dhinakaran Pandiyan <[email protected]> Cc: Rodrigo Vivi <[email protected]> Reviewed-by: Rodrigo Vivi <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-08drm/vmwgfx: Remove set but not used variable 'fb_offset, fb_depth'YueHaibing1-3/+1
Fixes gcc '-Wunused-but-set-variable' warning: drivers/gpu/drm/vmwgfx/vmwgfx_fb.c: In function 'vmw_fb_init': drivers/gpu/drm/vmwgfx/vmwgfx_fb.c:645:29: warning: variable 'fb_offset' set but not used [-Wunused-but-set-variable] drivers/gpu/drm/vmwgfx/vmwgfx_fb.c:645:19: warning: variable 'fb_depth' set but not used [-Wunused-but-set-variable] They're not used any more, so can be removed. Signed-off-by: YueHaibing <[email protected]> Reviewed-by: Deepak Rawat <[email protected]> Signed-off-by: Deepak Rawat <[email protected]>
2019-04-08drm/vmwgfx: Zero initialize handle in vmw_execbuf_processNathan Chancellor1-1/+1
When building with -Wsometimes-uninitialized, Clang warns: drivers/gpu/drm/vmwgfx/vmwgfx_execbuf.c:3964:7: warning: variable 'handle' is used uninitialized whenever '?:' condition is false [-Wsometimes-uninitialized] It's not wrong; however, in practice, this is never an issue because the value of handle isn't used when user_fence_rep is NULL because vmw_execbuf_copy_fence_user returns immediately when that is the case. Just zero initialize this variable so that Clang no longer warns. Link: https://github.com/ClangBuiltLinux/linux/issues/397 Signed-off-by: Nathan Chancellor <[email protected]> Reviewed-by: Nick Desaulniers <[email protected]> Signed-off-by: Deepak Rawat <[email protected]>
2019-04-08drm/vmwgfx: Use preprocessor macro for FIFO allocationDeepak Rawat17-290/+138
Whenever FIFO allocation fails an error message is printed to dmesg. Since this is common operation a lot of similar messages are scattered everywhere. Use preprocessor macro to remove this cluttering. Signed-off-by: Deepak Rawat <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]>
2019-04-08drm/vmwgfx: Fix formatting and spaces in vmwgfx_execbuf.cDeepak Rawat1-385/+302
No functional change with this change, just fixing formatting and spaces. v2: Rebase. Signed-off-by: Deepak Rawat <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]>
2019-04-08drm/vmwgfx: Use VMW_DEBUG_USER for device command buffer errorsDeepak Rawat1-8/+10
DRM_ERROR overwhelms dmesgi so use VMW_DEBUG_USER instead. Any malformed command should not really go to device so WARN_ONCE to spot this. Signed-off-by: Deepak Rawat <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]>
2019-04-08drm/vmwgfx: Clean up some debug messages in vmwgfx_execbuf.cDeepak Rawat1-12/+8
Now that vmw_cmd_check prints debug message whenever a command verifier fails, some of debug statements are unnecessary. Also rearranged some debug print-out with this patch. Signed-off-by: Deepak Rawat <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]>
2019-04-08drm/vmwgfx: Print message when command verifier returns with errorDeepak Rawat1-2/+5
Whenever command verifier function returns with an error, print a debug message using VMW_DEBUG_USER. This will make sure failing commands can be easily tracked for debugging purpose. Signed-off-by: Deepak Rawat <[email protected]> Reviewed-by: Thomas Hellstrom <[email protected]>
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